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Copyright by NXT Trang 1

HNG DN THIT K B NHN GIN

(Bi tp v nh ca thy Thun)

NI DUNG

DANH SCH HNH..........................................................................................................................................21. bi.........................................................................................................................................................32. Phn tch...................................................................................................................................................3

2.1 Cc bc thc hin.............................................................................................................................32.1.1 To project tn xxx trn Quartus..............................................................................................42.1.2 To nhn phn cng nios trn SOPC.......................................................................................52.1.3 B sung vo project xxx trn Quartus......................................................................................82.1.4 To file xxxx code C trn Nios...................................................................................................82.1.5 Test h thng trn board DE2.................................................................................................102.1.6 M phng h thng trn Modelsim.........................................................................................11

2.2 Code...................................................................................................................................................172.2.1 Code memoryDesign................................................................................................................172.2.2 Code C Nios...............................................................................................................................182.2.3 Code m phng.........................................................................................................................18

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DANH SCH HNH

Hnh 1. 1 S khi memory...........................................................................................................................3Hnh 2. 1 Cc th mc v tp tin chnh.............................................................................................................4Hnh 2. 2 Module memory

................................................................................................................................4Hnh 2. 3 Set Top-Level Entity.........................................................................................................................5Hnh 2. 4 Cc components c chn trong SOPC..........................................................................................5Hnh 2. 5 Thit lp Reset Vector v Exception Vector.....................................................................................5Hnh 2. 6 Tng hiu chnh a ch base........................................................................................................6Hnh 2. 7 Cch add component t to...............................................................................................................6Hnh 2. 8 Kim tra add thnh cng hay cha....................................................................................................6Hnh 2. 9 ng b cc tn hiu..........................................................................................................................7Hnh 2. 10 Add thnh cng component t to...................................................................................................7Hnh 2. 11 Generate h thng............................................................................................................................7Hnh 2. 12 To file Top-Level Entity................................................................................................................8Hnh 2. 13 MNios II IDE...............................................................................................................................8Hnh 2. 14 To project mi trong Nios II..........................................................................................................9Hnh 2. 15 Kim tra ni dung cc th vin.......................................................................................................9Hnh 2. 16 Kim tra a ch.............................................................................................................................10Hnh 2. 17 To code C....................................................................................................................................10Hnh 2. 18 Np phn cng xung DE2...........................................................................................................11Hnh 2. 19 Np phn mm xung DE2...........................................................................................................11Hnh 2. 20 To project mi trong Modelsim...................................................................................................12Hnh 2. 21 Add files vo project.....................................................................................................................12Hnh 2. 22 To file m phng.........................................................................................................................13Hnh 2. 23 Lnh vsim......................................................................................................................................13Hnh 2. 24 Mca s dng sng.....................................................................................................................14Hnh 2. 25 Add tn hiu cn quan st..............................................................................................................14Hnh 2. 26 Chuyn sang Hex...........................................................................................................................14Hnh 2. 27 Lu dng sng...............................................................................................................................15Hnh 2. 28 Chy m phng.............................................................................................................................15Hnh 2. 29 Quan st dng song m phng......................................................................................................15Hnh 2. 30 So snh ni dung memory gia Nios v Modelsim......................................................................16Hnh 2. 31 - So snh ni dung onchip_mem gia Nios v Modelsim...............................................................17Hnh 3. 1 Code verilog thit k.......................................................................................................................17Hnh 3. 2 Code C vit trong Nios II................................................................................................................18Hnh 3. 3 a ch vt l v a ch logic...........................................................................................................18Hnh 3. 4 Code m phng trn Modelsim.......................................................................................................19

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1. bi Thit k memory 4x32 bits, c cc tn hiu

clk (CLOCK_50) cs (chip_select) re (read_enable) we (write_enable) addr[1:0] (address) data_in[31:0] data_out[31:0]

Hnh 1. 1 S khi memory

Lu : Mt trong cc cng c hiu qu nht v s khi l Microsoft Visio 20072. Phn tch

2.1Cc bc thc hin Mt project hon chnh s c cc th mc v tp tin chnh sau (xem hnh 2. 1)9 Th mc nios_sim cha project m phngtool Modelsim9 Th mc software cha project code C tool Nios9 File xxx.sofcha RTL down xung board DE29 File onchip_mem.hex cha ni dung ca code C sau khi bin dch xong9 File cpu.vo (file ny rt quan trng)9 Cc file verilog (.v)

Lu :ng dn ci t cc tools ca Altera v cc bi tp phi khng cha khongtrng, nu c cha khong trng th khi bin dch trn Nios s c bo li

V d:

SaiE:\XT Exercises\Verilog VHDL\SampleCode\memoryDesign\ (ng dn

cha bi tp c khong trng)

OKE:\XT_Exercises\Verilog_VHDL\SampleCode\memoryDesign\

Tng t, khi ci t cc tools Altera, tt nht nn ng dn mc nh ca n l

C:\altera\72 v C:\altera\Modeltech_6.2f

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T

Hnh 2. 1 Cc th mc v tp tin chnh

2.1.1 To project tn xxx trn Quartus9 Sau khi to xong, mnh s vit code Verilog to module memory (chi tit code

s ni mc 3)

Hnh 2. 2 Module memory

9 Set file memoryDesign.v ny l top-level entity build th xem cn li haykhng. Vo Files chut phi vo memoryDesign.v chn Set as Top-Level

Entity

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Hnh 2. 3 Set Top-Level Entity

9 Sau build th. Nu ht li th sang bc 2.1.22.1.2 To nhn phn cng nios trn SOPC

MSOPC, to project tn nios, sau to nhn phn cng.

Hnh 2. 4 Cc components c chn trong SOPC

9 Nhnhp chut phi vo cpu, chn Edit, sau chn Reset Vector v ExceptionVector l onchip_mem

Hnh 2. 5 Thit lp Reset Vector v Exception Vector

9 Tip tc chut phi vo cpu, chn Auto-Assign Base Addresses

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Hnh 2. 6 Tng hiu chnh a ch base

9 K tip, add file memoryDesign.v mnh vit vo

Hnh 2. 7 Cch add component t to

9 Chn tip Signal

Hnh 2. 8 Kim tra add thnh cng hay cha

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9 Gn cc tn hiu tng ng gia module memoryDesign v Avalon bus (cc bnc th tm hiu l do ti sao gn nh vy trong sch Avalon Bus Specification)

Hnh 2. 9 ng b cc tn hiuca component t to v Avalon Bus

9 Sau khi ht li, nhn Finish, ta c component mi trong SOPC

Hnh 2. 10 Add thnh cng component t to

9 Chut phi vo cpu, chn Auto-Assign Base Addresses ln na. Sau , quaSystem Generation thc hin cc bc sau. Cui cng Generate

Hnh 2. 11 Generate h thng

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2.1.3 B sung vo project xxx trn Quartus9 To file xxx.v9 Vo file nios.v (tn file project trong SOPC), tm module nios (), copy vo

xxx.v

Hnh 2. 12 To file Top-Level Entity

9 Set li Top-Level Entity cho file xxx.v, sau build project2.1.4 To file xxxx code C trn Nios

9 Trong SOPC, nhp vo Nios

Hnh 2. 13 MNios II IDE

9 To project xxxx theo cc bc sau

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Hnh 2. 14 To project mi trong Nios II

9 Sau xa ni dung file hello_world.c, ch ni dung rng nh hnh di vbuild (nhn Ctrl+B).

Hnh 2. 15 Kim tra ni dung cc th vin

9 Sau khi build xong, vo file system.h tm a ch cc component. Khi cn dngcomponent no, ta ch quan tm n tn a ch ca component . V d khi cn

gi a ch base ca memoryDesign (0x00011000), ta ch cn gi tn

MEMORYDESIGN_INST_BASE

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Hnh 2. 16 Kim tra a ch

9 K tip, sa ni dung file hello_world.c thnh nh sau v build li ln na

Hnh 2. 17 To code C

9 Sau khi bin dch xong, Nios s to ra 3 fileo onchip_mem.hex ( cp u mc 2)o onchip_mem.dato

onchip_mem.sym Trong , 2 file cui cha trong th mc nios_simphc v cho vic m

phng

2.1.5 Test h thng trn board DE29 u tin, vo Quartus np phn cng

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Hnh 2. 18 Np phn cng xung DE2

9 Sau vo Nios np phn mm

Hnh 2. 19 Np phn mm xung DE2

2.1.6 M phng h thng trn Modelsim9 Mcng c Modelsim9 t tn project l xxxx v lu trong ../nios_sim

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Hnh 2. 20 To project mi trong Modelsim

9 Copy cc file trong th mc project Quartus vo project Modelsim, cc bn lu l khng chn file cpu.v

Hnh 2. 21 Add files vo project

9 To file m phng sim_xxx.v, sau compile project

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Hnh 2. 22 To file m phng

9 Trong ca s Transcript, g lnh vsim novopt sim_xxx (tn file m phng)

Hnh 2. 23 Lnh vsim9 Sau g view wave

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Hnh 2. 24 Mca s dng sng

9 Add cc tn hiu vo ca s wave

Hnh 2. 25 Add tn hiu cn quan st

9 Chn kiu hex cho d quan st dng sng

Hnh 2. 26 Chuyn sang Hex

9Lu li cc tn hiu add vo ca s wave s dng cho cc ln sau

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Hnh 2. 27 Lu dng sng

9 Tin hnh m phng: t thi gian m phng l 500 ns, chn Restart (bn tri),sau chn Run (bn phi)

Hnh 2. 28 Chy m phng

9 Quan st dng sng m phng

Hnh 2. 29 Quan st dng song m phng

9 Quan st gi tr memory thay i (sau khi m phng xong), ta thy kt qu ginght on code C trong nios

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Hnh 2. 30

So snh ni dung memory gia Nios v Modelsim

9 Ngoi ra, ta cn c th quan st c ni dung onchip_mem trong Modelsim

Ni dung onchip_mem trong Modelsim

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Ni dung onchip_mem trong NiosHnh 2. 31 -

So snh ni dung onchip_mem gia Nios v Modelsim2.2Code

2.2.1 Code memoryDesign12

345678910

1112131415

16171819

20212223

2425262728

29303132

module memoryDesign (// inputaddr,

re,data_in,we,clk,cs,

// output

data_out);

input we,re,

clk,cs;

input [1:0] addr;input [31:0] data_in;

output [31:0] data_out;

reg [31:0] memory [0:3];reg [31:0] data_out;

always @(posedge clk)begin

memory[addr]

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reg [DATA_WIDTH-1:0] [0:ADDR_WIDTH-1]

Trong :

DATA_WIDTH: sng d liu ADDR_WIDTH: sng a ch

V d: cn memory tn xxx c 16 ng data, 18 ng a ch (SRAM trn

board DE2), ta khai bo reg [17:0] xxx [0:15]

9 Memory nhn gi tr ghi vo khi cs (chn chip), we (cho php ghi vo) v ~re(khng cho php c ra)

9 Memory c gi tr ra khi cs (chn chip), ~we (khng cho php ghi vo) v re(cho php c ra)

2.2.2 Code C Nios12

345

678910

1112131415

#include #include

int main(){

// khai bao

volatileint * ptr = (int *) MEMORYDESIGN_INST_BASE;

*ptr = 0x99;*(ptr + 0x1) = 0x10;

*(ptr + 0x2) = 0x23;*(ptr + 0x3) = 0x567;

return 0;}

Hnh 3. 2 Code C vit trong Nios II

9 Dng 7 ptr l bin con tr ch ti vng nhbase ca memoryDesign(0x00011000). MEMORYDESIGN_INST_BASE l tn gi nhc to ra trong

system.h

9 Mi ln ptr tng ln 1 tng ng vi vic tng offset ln 4 i vi phn cng

Phn cng B nh Phn mm

offset = 0x0 0x0 0x1 0x2 0x3 ptr

offset = 0x4 0x4 0x5 0x6 0x7 ptr+1

offset = 0x8 0x8 0x9 0xa 0xb ptr+2

offset = 0xc 0xc 0xd 0xe 0xf ptr+3

Hnh 3. 3 a ch vt l v a ch logic

2.2.3 Code m phng123

456

module sim_xxx ();

reg clk;

reg reset_n;

xxx XXX(

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789

1011121314

1516

171819

202122

// Inputsclk,

reset_n);

initialclk = 1b0;

always#10 clk

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