thermal design of soc at the micron scale

3/19/20083/19/2008 © 2008 Gradient Design Automation© 2008 Gradient Design Automation 11

Thermal Design of SoCat the Micron Scale

Rajit Chandra, Ph.D.Founder, CTO

Gradient Design AutomationSanta Clara, California

www.gradient-da.com


Electronic thermal management

Package designs that meet TJ-MAX specs, given the total chip power dissipation

Designing effective chip-package cooling solutionsMinimizing package costs


Meeting the TJ-MAX Specs

Constanttemperature

Geometry associatedpower map

Area averagedpower map

Total chip powerΘJC

Calculate the average temperature of package-die interface:

Estimate the temperature variation within the die


Transitioning from mm-- to micron-scale


Google Earth for chip temperature


Micron-scale thermal profile


Micron-scale thermal hazard

∆T ≈

8ºC


Higher power densities on the chip ⇒ Larger temperature variations⇒ Steeper thermal gradients on the chip

Why micron-scale temperatures?


Adding to SoC thermal challenges

Miniature form factor ⇒ increasing thermal resistance of IC packages (or the lack thereof)

SiP, multi-die assemblies, stacked chips, CoF


Coarse-grain analysis Fine-grain analysis

Tj-max

Tj-actualTj-predicted

Coarse-grain

Fine-grain

IC cross section IC cross section

Tem

pera

ture

pro

file

Distance Distance

Tem

pera

ture

pro

file Actual

marginPredicted

margin


Micron-scale thermal modeling

To get at all the micron-scale

details, painlessly, the chip thermal

tools must integrate with the chip design tools

and dataThermal profile of

RF Power Amp transistor segments


Micron-scale modeling – Standard cell

Die stack-up, metal layers, standard cells and/or

transistors are modeled explicitly from EDA data

Standard Cell


How hot are the metal lines?

At 90, 65 and 45nm: Power densities are very highMetal line current densities can also be very highI2R self-heating in the metal lines can be significantLow-K dielectric has low heat conductivity Intel 65nm BEOL cross-section

Source: Intel Corp.


Visualization of hotspots on wires:Exposes signal wire electromigration


Gradient user quote:Managing heat is important in high-power design; too much heat can … contribute to reliability problems like electromigration and thermal run-away. The thermal map of a circuit can be used as a floorplanning tool … to reduce temperature deltas in sensitive areas of the design; … this may translate to greater efficiency.[CircuitFire] runs successive simulations ... A designer can then look at the thermal map and make decisions about how the heat producing elements can be placed, …

“Using Thermal Analysis as a Tool to Aid Analog Floorplanning,” David Schwan, Senior CAD and Layout Manager, Sirenza Microdevices Inc (now RF Micro Devices). http://www.cadence.com/cdnlive/na/2007.highlights.aspx


Gradient user quote:During the initial design of our automotive chip, our engineers didn't find any problems with Spectre. During testing of fabricated parts, our part was found to have a serious problem … It took 3 ECO’s … to figure out what was wrong … When we simulated in Spectre the circuit in the same mode that caused it to fail on the test floor, the circuit functioned correctly!If we had run CircuitFire at the chip level *before* tape-out, we would have spotted the problem before going to silicon.

ESNUG, “One user’s eval of the Gradient CircuitFire tool”, Morgan Ercanbrack of AMI Semiconductor.http://www.deepchip.com/items/0465-12.html


Integrate with chip design tools & data

Designlayout

Powermodeling

Packagemodeling

Thermaltechfile

Micron-Scale Thermal

Simulation

Reliabilitymodeling

Functionalitymodeling

Timingmodeling

Die stack-up


Summary

We have seen significant temperature variations at the micron scale, some of which have caused chips to failPackage engineers are responsible for thermal management

Package thermal tools today are not suited for simulating temperature variations at the chip-scale

For ease of use, the chip thermal tools must integrate with the chip design tools and data, to get at all the micron-scale details, painlesslyMicron-scale thermal analysis requires suitably detailed package model from package engineers

thermal design of soc at the micron scale

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