Thermal and Electrical Simulation of Smart Power Circuits by Network Analysis

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Introduction Simulation principle Cross section of lateral power transistor on SOI Column concept

Column presentation EKV transistor models

Accuracy (measurement versus simulation)Simulated temperature evolution on die and package heat spreader

Thermal mapping versus simulationMultiple grid simulation

Example measurement vs. electro-thermal simulation

The 17th International Symposium on Power Semiconductor Devices &ICs, ISPSD'05 Santa Barbara, California, USA

May 2005

Example output characteristics

Applications

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20052 ms

200ºC

switching on two 12 V 21 W lamps, 40 ms distant

Lamp 1 Lamp 2

Heat spreaderdie

PCB

Si

6.5 mmCu

6.5 mm

12 V

5 V

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40 ms

2 x 21 W

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Added terminals:

• temperature input and

• power output

• Non-linear bias-dependence of drift-resistance on drain and gate voltage • The model uses the formulation of this bias dependence as given in [3]. • Combined non-linear drift-resistance with a low-voltage MOS model for HVMOS modelling. • Core MOS model EKV-model [4] due to its proven suitability for analogue design• Reduced complexity compared to other recent MOS models, whereas the drift-resistance takes care of the HVMOS-specific effect of quasi-saturation.

[3] N. Hefyene “Bias-dependent drift resistance modelling for accurate DC and AC simulation of asymmetric HV-MOSFET”, SISPAD 2002, pp. 203-206[4] M. Bucher, C. Lallement, C. Enz, F. Krummenacher “Accurate MOS modelling for Analog Circuit Simulation Using the EKV Model”, ISCAS, 1996, pp. 703-706see also: D.M. Binkley, C.E. Hopper, S.D. Tucker, B.C. Moss, J.M. Rochelle, and D.P. Foty: "A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design",IEEE Trans. Computer-Aided Design, vol. 22, No. 2, Feb. 2003

BSIM versus EKV

BSIM: ~ 100 parameters

EKV: ~ 25 parameters

A

S

G

D

mobilitythreshold

v to v

Tambient

Tjunction

or spatial thermalnetworkPdiss

T P

symbol

Pulse measurement: 100 ns, 5 µs, 50 µs

Transistor area: 0.12 mm², SOI, QFN48

0.00.10.20.30.40.50.60.70.8

0.91.01.11.21.31.41.51.6

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drain source voltage / V

Idra

in/ A

100n

5u

50u

100 ns

5 µs

50 µs20 W, 163W/mm²

52 W, 423W/mm²

Check for short and medium term behaviour of the electro-thermal model and thermal network

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tem

per

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TempPT100/°C

simulation

PCBIC

PT100

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Long time temperature response dominated by the PCB

The data were derived from the measured temperature evaluation caused by a constant power source of the same size as the package (use the package itself)

measured and modelled in realistic application (e.g. cooling)

simple optimisation of third order Cauer network by several simulation runs

Implementation of the thermal performance of a PCB

Electro-thermal FEM simulation

J. Teichmann, W. Kraus, F. Liebermann, G. Täschner, C. WallnerAtmel Germany, Theresienstraße 2, D 74072 Heilbronn, Germany, Phone: 0049 7131 67-0

e-mail: juergen.teichmann@hno.atmel.com

o Spectre-based method is described for complex electrical-thermal transient simulations

o Packaged circuit is divided into numerous small columns

o A large electrical representation of the thermal network is formed (FEM method)

o The electrical circuit sends the dissipated power to the thermal network and receives the temperature

o All grid points have individual temperatures

o All grid point devices of the system have the same temperature

o An EKV transistor model with temperature input and power output is used

o Transient simulations and measurements are compared

o Application in smart power circuits

temperature

spatial(thermal)RC network(top view)

electrical inputs and outputs

electricalnetwork

y

x

chip

heatspreader

°C VPCB

othercircuitrypower

dissipationgrid

Column pad Column Cu Column Si

Au wire

1500

mｵ

Cu 70 mｵFilled drillholes

Cu 70 mｵ

mould compound 450 mｵ

Si 250 mｵ

Si

SiO2

adhesiveCu 200 mｵ

PC

B

chip

IC and PCB Package + PCB cross section

Thermal domain Electrical domain

Temperature T / °C Voltage V /V

Heat flow P / W Current I / A

Thermal resistance

Rth/ K/W Resistance R /

Thermal Capacitance

Cth / J/K Capacitance C / F

Cross-section of a SOI lateral power transistor

2 *pitch

Power transistor

D S B D S B D S BS B

Pitch 5...8 µm

Buried oxide

Heat generated by individual transistors has uniform power dissipation

M3

M2

M1

Si BOX

Lines of power dissipation

E. Roger et al.: A 2GHz., 60 V –Class SOI-Power....,ISPSD‘03 (PS4P1.pdf):

B

location of transistor or device

e5n5

w5

s5u

e4n4

w4

s4

e3n3

w3

s3

e2n2

w2

s2

e1n1

w1

s1

Si

SiO2

Si

Si

Adhesive, solder

Cu

Si

mold compound

e0n0

w0

s0

t

250 µm

e0n0

w0

s0

t

metallization

250 µm

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S6

S7

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B

T

Temp out

Power inT

N[0:7]

B

E[0:7]

W[0:7]

S[0:7]

Temp out

Power in

Spectre symbol

Used grid sizes:

lateral:13 µm, 50 µm, 250 µm

vertical: 8 layers, 18 layers (Si vertical: 83 µm, 18 µm)

Easy creation of huge networks PCB

Non linear Si heat conduction in Spectre: device “phy_res”. Polynomial, third degree

3 slices Si

14 s

lice

s S

i

Only material data and their dimensions are implemented

201 °C measurement (temp. diode in transistor middle)

211°C simulation

µs response

Power, max. 273 W

660 W/mm²

5.3W /mm

junction temperature, centre of heating transistor

ms response

simulated

measuredmeasured

179 °C

simulated

Imax=8 A, P=24 W, VDS=3 V

145 °C

500 ms

11 mm²

201°C

400 µs

Impact on simulation accuracy:

o Is the lateral and vertical grid sufficient?

o Validity and availability of all used material constants

o Thickness (tolerances!) of all layers

o Accuracy of transistor models up to 300…400°C

o Physical and electrical data of the actual measured sample

o Time delay of temperature diodes (incl. cross talk) in µs range

o Matching features of temperature diodes

o Are leakage currents accurately included in models?

o Impact of non ideal heat drill holes in the printed board

o Accuracy of thermal mapping (snap shot or “sequential read”)

o Accuracy of current probes

o Preliminary device size estimation in feasibility phase

o Calculation of critical temperature rises

o Package selection

o Complex circuit simulations

Note, the current of a device is a correct representation of the integral temperature of a device

die networkHeat spreader network

50 µm grid

250 µm grid

18255 nodes 65795 equations 8619 capacitors

8866 phy_res 12283 resistors 20 HV transistors

Linux, Dell precision 360, red head 7.3:

200 ms --> 344 s CPU

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15 mm SOI transistor 200 ms, 25 V, Pav=17 W

blackeningLateral temperature resolution 10 µm

Measured temperature profile,

10 µm grid

temperature diode

simulation

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temperature / °C

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Max temperature gradient:

50 K/50 µmMax temperature gradient:

125 K/50 µm

Exposure time:

313 µs