the world leader in high performance signal processing solutions a/d and d/a conversion cosimo...

The World Leader in High Performance Signal Processing Solutions

A/D and D/A Conversion

Cosimo Carriero

Analog Dialogue SeminarNovember 2011

Agenda

Fundamentals of sampled data systems A/D Converters Architectures

SARSigma-DeltaFlashPipelined

D/A Converters Architectures1 Bit DACThe Kelvin Divider or String DACThermometer DACBinary-Weighted DACR-2R Ladder DACSegmented DACOversampling Interpolating DACMultiplying DAC

A/D and D/A Converters State of the Art

3

Imagine a world without ADCs

SoundLight intensityTemperature

ForcepH...

in other words...

...the Real World

VoltageCurrent

ImpedanceTime*

in other words...

...the Analog World

Digital...... storage... display

... manipulation... communication

in other words...

..the Digital World

ADCSensor

4

Analog vs. Digital Options... back to the future

Analog Digital

Storage (& retrieval !!!)

Magnetic tapeChart recorder

Hard disk driveMemory Card..

DisplayCathode Ray Oscilloscope

Moving coil metersOptical indicators

Digital OscilloscopeLCD Displays

7-segment display

ManipulationAmplifiers

Analog ComputersDigital Signal Processing

Communication4-20mA loop

FM radio transmissionEthernet

USB, GSM


Analog Devices Confidential – © 2008 – Version 1a

Fundamentals ofData Converters

6

Sampled Data System

LPFORBPF

N-BITADC

DSPN-BITDAC

LPFORBPF

fa

t

fs fs

AMPLITUDEQUANTIZATION DISCRETE

TIME SAMPLING

fa

1fs

Ts=

tTs 2Ts 3Ts 4Ts 5Ts 6Ts 7Ts

7

Aliasing in the Time Domain

1fs

INPUT = faALIASED SIGNAL = fs – fa

NOTE: fa IS SLIGHTLY LESS THAN fs

t

Sampling Theorem

If the Fourier Transform of a function f(t) is zero above a certain frequency ωc, F(ω) = 0 for |ω| > ωc, then f(t) can be uniquely determined from its values

at a sequence of equidistant points, distance π/ωc, apart.

In fact f(t) is given by

cn nff

n c

cn nt

ntftf

sin

)(

Nyquist's Criteria

A signal with a maximum frequency fa must be sampled at a rate fs > 2fa or information about the signal will be lost because of aliasing.

Aliasing occurs whenever fs < 2fa

A signal which has frequency components between fa and fb must be sampled at a rate fs > 2 (fb – fa) in order to prevent alias components from overlapping the signal frequencies

The concept of aliasing is widely used in communications applications such as direct IF-to-digital conversion.

Aliasing in the Frequency Domain

0.5fs fs 1.5fs 2fs 2.5fs

fa I I I I

1st Nyquist Zone

2nd Nyquist Zone

3rd Nyquist Zone

4th Nyquist Zone

5th Nyquist Zone


faI I I I

A

B

Aliasing in the Frequency Domain


fa

1st Nyquist Zone

2nd Nyquist Zone

3rd Nyquist Zone

4th Nyquist Zone

5th Nyquist Zone


A

B

Oversampling Relaxes Requirements on Baseband Antialiasing Filter

BA

DR

fs

fa fs - faKfs - f

afa

fs2

KfsKfs2

STOPBAND ATTENUATION = DR

TRANSITION BAND: fa to fs - fa

CORNER FREQUENCY: fa

STOPBAND ATTENUATION = DR

TRANSITION BAND: fa to Kfs - fa

CORNER FREQUENCY: fa

13

Quantization:The Size of a Least Significant Bit (LSB)

RESOLUTIONN

2-bit

4-bit

6-bit

8-bit

10-bit

12-bit

14-bit

16-bit

18-bit

20-bit

22-bit

24-bit

2N

4

16

64

256

1,024

4,096

16,384

65,536

262,144

1,048,576

4,194,304

16,777,216

VOLTAGE(10V FS)

2.5 V

625 mV

156 mV

39.1 mV

9.77 mV (10 mV)

2.44 mV

610 V

153 V

38 V

9.54 V (10 V)

2.38 V

596 nV*

ppm FS

250,000

62,500

15,625

3,906

977

244

61

15

4

1

0.24

0.06

% FS

25

6.25

1.56

0.39

0.098

0.024

0.0061

0.0015

0.0004

0.0001

0.000024

0.000006

dB FS

– 12

– 24

– 36

– 48

– 60

– 72

– 84

– 96

– 108

– 120

– 132

– 144

*600nV is the Johnson Noise in a 10kHz BW of a 2.2k Resistor @ 25°C

Remember: 10-bits and 10V FS yields an LSB of 10mV, 1000ppm, or 0.1%.All other values may be calculated by powers of 2.

1.14

Quantization Noise as a Function of Time

t

+q2

–q2

SLOPE = s

+q2s

–q2s

e(t)

MEAN-SQUARE ERROR =

ERROR =

ROOT-MEAN-SQUARE ERROR =

error

analog input

Digital output

q = 1LSB

stte )(s

qt

s

q

22

12)()(

22/

2/

22 qdtst

s

qte

sq

sq

12)(2

qteerms

Theoretical Quantization Noise Ideal N-Bit Converter

)sin(2

2)sin()( 0 t

qtVtv

N

)_(_

)_(__log20 10 rmsNoiseonQuantizati

rmsSinewaveScaleFullSNR

22

2

2)( 0

NqVrmsv

2

3log20)2log20(

12

22

2log20 101010

Nq

qSNR

N

76.102.6)( NdBSNR

02.6

76.1)(

dBSNRENOB

1.16

Quantization Noise Spectrum

fs2

RMS VALUE = q

12q = 1 LSB

MEASURED OVER DC TO fs2

q / 12

fs / 2

NOISESPECTRALDENSITY

SNR = 6.02N + 1.76dB + 10log10 FOR FS SINEWAVEfs

2•BW

BW

Process Gain

18

Basic ADC and DAC

VDD

VSSGND

ANALOGINPUT

VREF

SAMPLING CLOCK EOC, DATA READY, ETC.

DIGITALOUTPUTADC

VDD

VSSGND

ANALOGOUTPUT

VREF

(ANALOG INPUT)

DIGITALINTPUT DAC

Transfer Functions for Ideal 3-Bit DAC and ADC

DIGITAL INPUT

ANALOGOUTPUT

FS

000 001 010 011 100 101 110 111 ANALOG INPUT

DIGITALOUTPUT

FS

000

001

010

011

100

101

110

111

QUANTIZATIONUNCERTAINTY

QUANTIZATIONUNCERTAINTY

DAC ADC

Static (DC) Errors in Converters

FS

IDEAL

ACTUAL

OFFSET ERROR

FS

IDEAL

ACTUAL

GAIN ERROR

FS

IDEAL

ACTUAL

INTEGRAL LINEARITY ERROR

LINEARITY ERROR 1.5LSBDNL=+0.5LSB

0.5LSBDNL=-0.5LSB

DIFFERENTIAL LINEARITY ERROR

Transfer Functions for Non-Ideal 3-Bit DAC and ADC

DIGITAL INPUT

ANALOGOUTPUT

FS

000 001 010 011 100 101 110 111

NON-MONOTONIC

ANALOG INPUT

DIGITALOUTPUT

FS

000

001

010

011

100

101

110

111

MISSING CODE

DAC ADC

DIGITAL INPUT

ANALOGOUTPUT

FS

000 001 010 011 100 101 110 111

NON-MONOTONIC

DIGITAL INPUT

ANALOGOUTPUT

FS

000 001 010 011 100 101 110 111

NON-MONOTONIC

ANALOG INPUT

DIGITALOUTPUT

FS

000

001

010

011

100

101

110

111

ANALOG INPUT

DIGITALOUTPUT

FS

000

001

010

011

100

101

110

111

MISSING CODE

DAC ADC

1.22

Quantifying Data Converter Dynamic Performance

Signal-to-Noise Ratio (SNR) Harmonic Distortion Worst Harmonic Total Harmonic Distortion (THD) Total Harmonic Distortion Plus Noise (THD + N) Signal-to-Noise-and-Distortion Ratio (SINAD) Effective Number of Bits (ENOB) Analog Bandwidth (Full-Power, Small-Signal) Spurious Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion (IMD) Multi-tone Intermodulation Distortion Noise Power Ratio (NPR) Adjacent Channel Leakage Ratio (ACLR) Noise Figure Settling Time, Overvoltage Recovery Time

Sample-and-Hold FunctionRequired for Digitizing AC Signals

ADCENCODER

TIMINGSAMPLINGCLOCK

SWCONTROL

ANALOGINPUT

SAMPLE

HOLD

SAMPLE

C

ENCODER CONVERTSDURING HOLD TIME

SWCONTROL

N

Input Frequency Limitations of Non-Sampling ADC (Encoder)

N-BITSAR ADC ENCODER

CONVERSION TIME = 8µs

EXAMPLE:

dv = 1 LSB = qdt = 8µsN = 12, 2N = 4096

fmax = 9.7 Hz

v(t) = 2N

2sin (2 f t )

dvdt

2N

22 f cos (2 f t )=

dvdt max

= 2(N–1) 2 f

dvdt max

2(N–1) 2 qfmax =

fs = 100 kSPS

ANALOG INPUTN

dvdt max

q 2Nfmax =

q

q

q

Aperture Time – Aperture Delay Time

Effective Aperture Delay TimeMeasured with Respect to ADC Input

SAMPLINGCLOCK

ANALOG INPUTSINEWAVE

ZERO CROSSING

+FS

-FS

0V

+te–te

te

' '

'

27

Effects of Aperture Jitter and Sampling Clock Jitter

ADC

45.0

50.0

55.0

60.0

65.0

70.0

75.0

80.0

85.0

90.0

100 1000

50 fs

100 fs

200 fs

400 fs

800 fs

Fullscale Analog Input (sinewave)

84dB

78dB

AIN = 200 MHz

Each line shows constant RMS clock jitter in femtoseconds (fs)

72dB

66dB

60dB

300MHz

400MHz

500MHz

SNR of ADC @ 200 MHz AIN varies with clock jitter

ADC

Analog Input

Sampling Clock

SNR

Digital Output

Sampling theory requires at least 2x over sampling of desired signal bandwidth

SNR performance is a function of input clock jitter and input center frequency

Trade offSNR over given signal bandwidth vs clock jitter vs input

frequency

Ana

log

Inpu

t

Spurious Free Dynamic Range - SFDR

29

DAC Settling Time

DEADTIME

RECOVERYTIME

LINEARSETTLING

SLEWTIME

t = 0

ERROR BAND

ERROR BAND

SETTLING TIME (INPUT TO OUTPUT)

SETTLINGTIME (OUTPUT)

30

DAC Signal Construction – Glitch Impulse Area

t

SAMPLEDSIGNAL

t

RECONSTRUCTED SIGNAL

1

fc

IDEAL TRANSITION TRANSITION WITH

DOUBLET GLITCH

TRANSITION WITH

UNIPOLAR (SKEW) GLITCH

t t t

31

DAC sin x/x Roll Off(Amplitude Normalized)

0.5fc fc 1.5fc 2fc 2.5fc 3fc

A = sin

f

fc f

fc

1

f

A

t

–3.92dB

RECONSTRUCTED SIGNAL

0

1

fc

IMAGESIMAGES

IMAGES

FS – FOUT FS + FOUT 2FS – FOUT 2FS + FOUT

32

LPF Required to Reject Image Frequency

33

Analog Filter Requirements for fo = 10MHZ:

fc = 30MSPS, and fc = 60MSPSfCLOCK = 30MSPS

dB

IMAGE

10 20 30 40 50 60 70 80

fo

ANALOG LPF

10 20 30 40 50 60 70 80

IMAGE

ANALOGLPF

FREQUENCY (MHz)

IMAGEIMAGEIMAGE

IMAGE

fo

fCLOCK = 60MSPS

dB

A

B



Analog to Digital ConvertersArchitectures

1.35

ADC Architectures, Applications, Resolution, Sampling Rates

10 100 1k 10k 100k 1M 10M 100M 1G8

10

12

14

16

18

20

22

24

-

-

INDUSTRIALMEASUREMENT

VOICEBAND,AUDIO

VIDEO, IF SAMPLING, SOFTWARE RADIO, ETC.

SAMPLING RATE (Hz)

RE

SO

LUT

ION

(B

ITS

)

CURRENT STATE-OF-THE-ART(APPROXIMATE)

PIPELINE

SAR

DATA ACQUISITION

Precision : ≤ 10MSPSHigh Speed: > 10MSPS

37

The Comparator: A 1-Bit ADC

+

–

DIFFERENTIALANALOG INPUT

LOGICOUTPUT

LATCHENABLE

DIFFERENTIAL ANALOG INPUT

COMPARATOR OUTPUT

"0"

"1"

0

VHYSTERESIS

1.38

Basic Successive Approximation ADC

SHA

CONTROLLOGIC:SUCCESSIVEAPPROXIMATIONREGISTER(SAR) DAC

TIMING

CONVERTSTART

EOC,DRDY,OR BUSY

OUTPUT

ANALOGINPUT COMPARATOR

1.39

Successive Approximation ADC Algorithm Analogy Using Binary Weights

XTEST

IS X 32 ? YES RETAIN 32 1

ASSUME X = 45

IS X (32 +16) ? NO REJECT 16 0

IS X (32 +8) ? YES RETAIN 8 1

IS X (32 +8 + 4) ? YES RETAIN 4 1

IS X (32 +8 + 4 + 2) ? NO REJECT 2 0

IS X (32 +8 + 4 + 2 + 1) ? YES RETAIN 1 1

X = 32 + 8 + 4 + 1 = 4510 = 1011012 TOTALS:

1.41

4-Bit Switched Capacitor ADC

+

_

Vin

Vref

C C/2 C/4 C/8 C/8Comparator

S1

S2

S3 S4 S5 S6 S7

Sample Mode

1.42

4-Bit Switched Capacitor ADC

+

_

Vin

Vref


S1

S2

S3 S4 S5 S6 S7

Hold Mode

-Vin

+

_

Vin

Vref


S1

S2

S3 S4 S5 S6 S7

Redistribution Mode

0V

•AD7626 – 16-Bit -10MSPS•16 steps required for oneConversion •160MHz internal frequency•6.25ns each step.

Driving the AD7944 – 18b 1.33MSPS

2.44

First-Order Sigma-Delta ADC

+

-

+VREF

–VREF

DIGITALFILTER

ANDDECIMATOR

+

_

CLOCKKfs

VIN N-BITS

fs

fs

A

B

1-BIT DATASTREAM1-BIT

DAC

LATCHEDCOMPARATOR(1-BIT ADC)

1-BIT,

Kfs

SIGMA-DELTA MODULATOR

INTEGRATOR

Vref

-Vref

VinVB

VA

CK

t

t

t

t

2.45

Oversampling, Digital Filtering, Noise Shaping, and Decimation

fs2

fs

Kfs2

Kfs

KfsKfs2

fs2

fs2

DIGITAL FILTER

REMOVED NOISE

REMOVED NOISE

QUANTIZATIONNOISE = q / 12 q = 1 LSBADC

ADCDIGITALFILTER

MOD

DIGITALFILTER

fs

Kfs

Kfs

DEC

fs

NyquistOperation

Oversampling+ Digital Filter+ Decimation

Oversampling+ Noise Shaping+ Digital Filter+ Decimation

A

B

C

DEC

fs

Noise Shaping

ΣAnalog Filter

H(f)=1/fΣ

X

Y

X-Y

+

-

(1/F)(X-Y)Q

+

+

QYXf

Y )(1

11

1

f

fQ

fXY

ΣVin

Y

+-

ΣY

+-

+-

CK

1-BitDAC

DigitalFilter

47

Multi-Bit Sigma-Delta ADC

DIGITALFILTERANDDECIMATOR

+

_

CLOCKKfs

VINN-BITS

fs

fs

A

B

n-BIT DATASTREAM

n-BITDAC

n-BIT,

Kfs

SIGMA-DELTA MODULATOR

INTEGRATOR

n-BITFlash ADC

IN+

IN-

OUT- OUT+

+5V

2 mV/VSensitivity

Exceptional precision for low speed & high speed Weigh Scale applications 8.5 nV rms noise (Gain = 128, 4.7 Hz Output Update Rate) 16 bits of noise free resolution (Gain =128, 2.4 kHz Output Update Rate)

Lowest Offset Drift @ 5 nV/°CPower Save Mode via programmable Bridge Power Down Switch (BPDSW)

48

AD719x – Application ExampleWeigh Scale Loadcell or Pressure Sensor Measurement

1.49

3-Bit All-Parallel (Flash) Converter

N

R

PRIORITYENCODER

AND LATCH

ANALOGINPUT

DIGITALOUTPUT

+VREF

R

R

R

R

R

0.5R

STROBE

1.5R

+

–

+

–

+

+

+

+

+

–

–

–

–

–

A KEY BUILDING BLOCK FOR PIPELINED ADCs

1.50

6-Bit Two-Stage Subranging ADC

SAMPLEAND HOLD

_

+

OUTPUT REGISTER

ANALOGINPUT

DATA OUTPUT, N-BITS = N1 + N2 = 3 + 3 = 6

CONTROL

SAMPLINGCLOCK

See: R. Staffin and R. Lohman, "Signal Amplitude Quantizer,"U.S. Patent 2,869,079, Filed December 19, 1956, Issued January 13, 1959

RESIDUESIGNAL

N1 MSBs (3) N2 LSBs (3)

GN1-BIT(3-BIT)SADC

N1-BIT(3-BIT)SDAC

N2-BIT(3-BIT)SADC

51

Residue Waveforms at Input of N2 SADC

MISSING CODES

MISSING CODES

R = RANGEOF N2 SADC

X

R

Y

(A) IDEAL N1 SADC

(B) NON LINEAR N1 SADC

1.53

Generalized Pipeline Stages in a Subranging ADC with Error Correction

SADCN1 BITS

SDACN1 BITS

T/H+

–

+

–

+

– SADCN2 BITS

SDACN2 BITS

+

–

TO ERROR CORRECTING LOGIC

T/H,1

T/H,2

SADCN1 BITS

S MDACN1 BITS

T/H+

–T/H+

–

SADCN2 BITS

S MDACN2 BITS

(B)

TO ERROR CORRECTING LOGIC

(A)

ADC Output Configurations

ADC ADC ADC

N

PLL PLL

Fdata

FdataFdata

Fs Fs Fs

FCLKDCO

DCO

Parallel CMOS Fdata max = 150 MSPS

DDR LVDS Fdata max = 420 MSPS

Interface available in lower cost FPGAs

Pins = ADC resolution plus DCO

High pin count

Fdata max = 840Mbps? Serial LVDS

Fs max = Fdata * # of data lanes / ADC resolution

On chip PLL required Higher-end FPGA

typically required Pins = # of data lanes

plus Frame CLK and Data CLK

Fdata = 3.125Gbps+ Encoded serial CML Fs max = data packet

length + overhead On chip PLL required High-end FPGA

required Clock recovery

Slower customer adoption rate

2 pins

PARALLEL SERIAL LVDS SerDes

54

55

TRX System Architectures

Today’s solution Solution with JESD204A Serial Interface

FPGA

32 wires

16 wires

Dual 16B DAC

14B ADC

Tight timingrequirements

Large # of I/Os

ToAntenna 1

32 wires

18 wires

Dual 16B DAC

14B ADC

ToAntenna 2

CPRI/OBSAI

FPGA

FPGA

Dual16B DAC

14B ADC

ToAntenna 1

Dual 16B DAC

14B ADC

ToAntenna 2

CPRI/OBSAI

FPGA

2 to 4

Serial pairs

RelaxedTiming requirements

Minimum # of I/Os

2 to 4

Serial pairs

1

Serial pair

1

Serial pair

Serdes?

SE

RD

ES

chip

56

IF Sampling Rx

IF Sampling and IF Synthesis

TX/RXDIPLEXER PLL

VGA

POWERCONTROL

LNA

MIXER

MIXER

DACPA

VGA ADC

FPGA

FPGAADCDRIVER

IF Synthesis Tx

POWER MANAGEMENT& SUPERVISORY

CLOCK GEN/DIST



Digital to Analog Converters

Architectures

64

1-Bit DAC:Changeover Switch (SPDT)

VREF

OUTPUT

Sampled Data System: Sampling and Quantization

Sigma-Delta DAC

DigitalInterpolation

Filter

DigitalΣΔ

Modulator

1-BitDAC

AnalogOutputFilter

N-Bits @ fs N-Bits @ K fs 1-Bit @ K fsAnalog Signal

2 LevelsAnalog Output

Single Bit

DigitalInterpolation

Filter

DigitalΣΔ

Modulator

1-BitDAC

AnalogOutputFilter

N-Bits @ fs N-Bits @ K fs M-Bits @ K fsAnalog Signal

2M LevelsAnalog Output

Multi Bit

68

Simplest Voltage Output Thermometer DAC: The Kelvin Divider ( AKA - "String DAC")

3-TO-8DECODER

3-BITDIGITALINPUT

ANALOGOUTPUT

VREF

8

TOSWITCHES

R

R

R

R

R

R

R

R

69

Digital Potentiometer

3-TO-8DECODER

3-BITDIGITALINPUT

TAP

8

TOSWITCHES

R

R

R

R

R

R

R

Terminal A

Terminal B

70

The Simplest Current Output Thermometer (Fully-Decoded) DAC

3-BITDIGITALINPUT

CURRENTOUTPUT INTO

VIRTUALGROUND

(USUALLY ANOP-AMP I-V

CONVERTER)

VREF

3-TO-7DECODER

R R R R R R R

TOSWITCHES

7

71

Voltage-Mode Binary Weighted Resistor DAC

R/8 R/4 R/2 R

V

V

REF

OUT

MSBLSB

72

Current-Mode R-2R Ladder Network Resistor-Based DAC

2R

RRR

2R2R2R2R

VREF

MSB LSB

CURRENTOUTPUTINTOVIRTUALGROUND

<< R

*

* GAIN TRIM IF REQUIRED

73

Segmented Voltage Output DACsKELVIN-VARLEY DIVIDER("STRING DAC")

VREFVREF

OUTPUT

KELVIN DIVIDER ANDR-2R LADDER NETWORK

NOTE:MSB OF R-2R LADDER

ON RIGHT

IF THE R-2R LADDER NETWORKIS MONOTONIC, THE

WHOLE DAC ISMONOTONIC

OUTPUT

(A) (B)

A

B

A

B

A

B

A

B

A

A

B A

B

74

Oversampling Interpolating Txdac™Simplified Block Diagram

fo

K•fcfc

LATCH LATCH DAC

LPF

DIGITALINTERPOLATION

FILTER

PLL

N N N N

TYPICAL APPLICATION: fc = 160MSPSfo = 50MHz

K = 2 Image Frequency = 320 – 50 = 270MHz

75

Multiplying DAC

2R

RRR

2R2R2R2R

VREF

MSB LSB

CURRENTOUTPUTINTOVIRTUALGROUND

<< R

*

* GAIN TRIM IF REQUIRED

MDACAnalog Output

Digital Input

Vref

Analog Output = Vref x Digital Input x K



ADCs State of the Art

SAR Converters

The Need For Speed16-bit PulSAR ADCs

Technology Leadership: Meeting customer need for faster

sampling rate No compromise on performance,

keeping power to a minimum

AD7677

0.6um1 MSPS

2002

Spe

ed M

SP

S

Year of Release2005 2008

AD7622

0.25um2 MSPS

AD7621

0.25um3 MSPS

AD7625

0.25um6 MSPS

AD7626

0.25um10 MSPS

10

9

8

7

6

5

4

3

2

1

77

2010

AD7626 and AD762516-Bit, 10MSPS and 6MSPS PulSAR® Differential ADCsFeatures Fast Throughput, High Performance

10 MSPS (AD7626) 6 MSPS (AD7625)

SAR architecture 16-bit resolution with no missing codes SNR: 92 dB Typ, 90dB Min @ 1MHz INL: ±1 LSB Typ, ±2 LSB Max DNL: ±0.3 LSB Typ, ±1 LSB Max Differential input range: ± 4.096V No latency/no pipeline delay Serial LVDS interface On-Board 4.096V Reference Power dissipation 130 mW @ 10 MSPS,

100 mW @ 6 MSPS

78

16-Bit

Resolution

4.096

Input

1

Channels

2LSB

INL, Max

Serial-LVDS

Interface

32-lead LFCSP

Package

The World Lowest Power 16-Bit ADC Lowest Power: 7mW @ 1MSPS Power scales linearly with sampling rate

like 70W @ 10kSPS The World Smallest Package in > 0.2MSPS 16-Bit

ADC LFSCP/QFN (SOT23 size) or MSOP Pin-Pin compatible with AD768x

The World fastest MSOP/QFN 16-Bit ADC Outstanding DC and AC Performance

16-Bit No Missing Code +/-1.5LSB INL Max 20bit effective resolution @ 10kSPS

Ease of use 2.5V main supply 0 to REF input (up to 5V) - lower cost opamp - 5V/3.3V/2.5V serial SPI Multiple ADC Daisy Chain, Busy Indicator

For Data acquisition, ATE, Smart Sensors and Portable Medical equipments

For Data acquisition, ATE, Smart Sensors and Portable Medical equipments

AD7980- 1MSPS, 7mW 16 Bit ADCAD7980- 1MSPS, 7mW 16 Bit ADC in MSOP/QFN in MSOP/QFN

3mm

EE Times Chinaconverter Winner

EE Times Chinaconverter Winner

AD7982 PulSAR ADC: 18-Bit, 1MSPS, 7mW

The World Lowest Power 18-Bit ADC 7mW @ 1MSPS

(30x lower than competition) Power scales linearly with sampling rate:

70W @ 10kSPS The World Smallest Package 18-Bit ADC

LFSCP/QFN (SOT23 size) or MSOP(5x smaller than competition)

Pin-pin compatible with AD769x Outstanding DC and AC Performance

18-bits NMC, +/-2LSB INL max 22.7 bit effective resolution @ 1kSPS

Ease of use Easy design for ANY input ranges 0 to REF input (up to 5V) - lower cost opamp - 5V/3.3V/2.5V serial SPI Multiple ADC daisy chain, busy indicator

Released

AD7986High Speed 2MSPS 18-bit ADC, Low Power 15mW, 4.096V Reference, 20L-LFCSP High Performance

Maintains leadership position: Smallest, Fastest, Lowest Power

FeaturesLowest power: 15mW@ 2MSPS w/o reference 26mW@ 2MSPS w/referenceThroughput: 2MSPS Turbo= HIGH 1.5MSPS Turbo= LOW1.8V/2.5V/2.7V serial SPISNR 97dB w/external VREFPin for pin with AD7985 (16b), AD7944 (14b)

Resolution Input Channels INL, Max Interface Package

18-bits DIFF +/-VREF 11LSB typ2.5LSB max

SPI QFN-20

AD7986

18-bit, 2MSPS

Motor ControlMotor ControlEnergy Energy Process ControlProcess Control

AD7609 : 18 Bit, 8-Channel Simultaneous Sampling ADCMulti-Market Building Block for High Dynamic Range Applications simultaneous sampling

InstrumentationInstrumentation

FeaturesFeatures 8 channels simultaneous sampling 200KSPS for all 8 Channels Single 5V supply operation Differential Analog Inputs +/-20V & +/-10V 40V Differential Analog Input Range Sensors with differential output can connect directly to the AD7609 Analog Inputs can withstand 7KV HBM ESD +/-16.5V Analog input clamp protection 1Meg Resistor input impedance 2nd Order Analog Anti-Alias Filter Backend Digital filter 2.5V reference and reference buffer SPI and Parallel interface. 64 lead LQFP Package

PerformancePerformance 18 Bits No Missing Codes INL +/- 2.5LSB (Typ) 91 dB SNR @ 200k 105 dB DR @3.125ksps (digital filter on, OSR = 64)

100mW Power (Typ) NFS/PFS Code 0.1% FSR over Temperature




Precision Sigma-Delta (Σ-Δ)

Precision Σ-Δ ADCs – Most Recent

16/24-bit single ch

11 nV Noise; 4.8 kHz2/4-Channel

8.5 nV Noise; 4.8 kHz2/4-Channel

16-bit pk-pk @ 2.4kHz; G=128

16-/20-/24-bit 3-ch PGA + ref+ exc currents

16-/24-bit 6-ch PGA + ref+ exc currents 16-/24-bit 3-ch PGA

Low Power / Highly integrated with PGA

Pin Programmable15 nV Noise; 120 Hz

2/4-Channel

4/8-Channel

8/16-Channel

Bridge Sensor ADCs24/20-bit; 380 µA

Tiny Pkg 12/16-bit ADCs

Highest Precision + PGA

Ease-of-Use

16-/24-bit 1-ch PGA 16-/24-bit 1-ch PGA 16-/24-bit 2-ch PGA

Ultralow Power / Small Package

Released

AD7190

AD7191

AD7192

AD7193

AD7194

AD7780/81

AD7170/71

AD7798/99

AD7796/97AD7792/85/93

AD7794/95

AD7788/89 AD7790/91 AD7787

AD7195

AD7190 PerformanceWith AC Excitation

25mm2 CSP pkg

400-500 uA max

4 Hz – 470HzTemp

PressureWeighscale

500 uA max10 Hz/ 16.7 HzWeighscales

PressurePortable

5.6 mA-7.35 mA max4 Hz – 4.8 kHz

PLCWeighscale

130 uA max9.5 Hz to 120 HzGas Detectors

Portable

128/64/32kHz8mW, 115dB, 16-Bit INL

312kHz, 115dB,Diff Amp& Ref Buffer

2.5MHz/625kHz100dB,

Diff Amp & Ref BufferProgrammable filter

High Dynamic Range24-Bit DAQVibration

Medical (EEG)

AD7766/66-1/66-2

AD7764

AD7760/2/3128/64/32kHz8mW, 115dB, 18-Bit INL

AD7767/67-1/67-2

AD7765

156kHz, 115dB,Diff Amp& Ref BufferFlexible Decimation

WideBandwidth DC & AC

Low Power – 400 μA typical Low Noise – 40 nV rms Programmable Integrated Features for

Temperature Sensing(RTDs, Thermocouples, Thermistors)

Instrumentation Amplifier (binary gains 1 to 128) Excitation Current Sources (10 / 210 / 1000 µA) Voltage Reference, Clock Input Buffer, Temp Sensor

Superior offset & gain drift specs Offset = 10 nV/°C; Gain = 1 ppm/°C

Simultaneous 50 & 60 Hz Rejection 4 Hz to 470 Hz Output Data Rate Supply: 2.7 V to 5.25 V Temp: -40°C to +105°C

+125°C option for AD7794

AD7785/92/93/94/95 – Product DescriptionLow Power, Highly Integrated Σ-Δ ADC for Temperature Sensing

AD7792/85/9316-/20-/24-bit Σ-Δ ADC 3 Differential Channels 16-TSSOP Package

AD7795/9416-/24-bit Σ-Δ ADC6 Differential Channels24-TSSOP Package

Temperature Measurement RTD Sensor

KEY APPLICATION BENEFITSKEY APPLICATION BENEFITS

3-wire RTD 2 matched excitation currents 40 nV RMS @ Gain = 64 Ratiometric Configuration 50 & 60 Hz Rejection (-70 dB)

RL1

RL2

RL3

RTD

GND VDD

AD7793

SERIALINTERFACE

ANDCONTROL

LOGIC

INTERNALCLOCK

CLK

SIGMA DELTAADC

IOUT1

MUXIN-AMP

REFIN(+) REFIN(-)BANDGAPREFERENCE

GND

SPI SERIALINTERFACE

IOVDD

VDD

GND

IOUT2

REFIN

AIN1

RREF

EXCITATIONCURRENTS

Temperature Measurement Thermocouple Sensor

KEY APPLICATION BENEFITSKEY APPLICATION BENEFITS Thermocouple

Internal Reference 40 nV RMS @ Gain = 64, 4 Hz Update Rate Differential Analog Input On-chip VBIAS Centers the Sensor Range 50 & 60 Hz Rejection

KEY APPLICATION BENEFITSKEY APPLICATION BENEFITS Cold Junction

Second Channel In-Amp (Gain 1-64) Excitation Currents Ratiometric Measurement

THERMOCOUPLEJUNCTION

GND VDD

AD7793

SERIALINTERFACE

ANDCONTROL

LOGIC

INTERNALCLOCK

CLK

SIGMA DELTAADC

AIN1

IOUT1

AIN2

REFINRREF

MUX IN-AMP

REFIN(+) REFIN(-)BANDGAPREFERENCE

GND

SPI SERIALINTERFACE

IOVDD

VDD

GND

VBIAS

CC

R

R

EXCITATIONCURRENTS

GND VDD

AD7794

SERIALINTERFACE

ANDCONTROL

LOGIC

INTERNALCLOCK

CLK

IN-AMP

AIN1

IOUT1AIN3

VDD

GND

PWRSWGND

AIN2

IN+

IN-

OUT+OUT-

IN+

IN-

OUT+OUT-

VDD

REFIN1(+)

EXCITATIONCURRENTS

MUX SIGMA DELTAADC

IOVDD

SPI SERIALINTERFACE

THEMISTOR

RREF

REFIN1(-)

REFIN2(+)

REFIN2(-)

Flow MeasurementFlow Sensor

KEY APPLICATION BENEFITSKEY APPLICATION BENEFITS Flow Sensor

Several channels required 40 nV RMS Noise (In-Amp Gain = 64)REFIN up to AVDD

Ratiometric Configuration50 & 60 Hz Rejection (-70 dB)

Pressure Measurement Weigh Scale (Bridge Sensor / Loadcell)

KEY APPLICATION BENEFITSKEY APPLICATION BENEFITS 27 nV noise (In-Amp Gain = 128, 4 Hz Update Rate) REFIN up to AVDD Ratiometric Configuration Medium/High Range Weigh Scales (1 count in 112, 000 (±10 mV Input Range)) 50 & 60Hz Rejection (-70 dB)

+5V

GND AVDD AD7799

SERIALINTERFACE

ANDCONTROL

LOGIC

SIGMADELTA ADC

REFERENCEDETECT

INTERNALCLOCK

AIN1(+)

AIN1(-)

MUX IN-AMP

REFIN(+)

REFIN(-)

DOUT/RDYDIN

SCLK

CS

DVDD

VDD

GND

PWRSW

IN+

IN-

OUT- OUT+

AIN2

AIN3/P1/P2

2 mV/VSensitivity

10 mV max

90

AD7190 – Product Description2/4 Channel 4.8 kHz Ultralow Noise 24-Bit Σ-Δ ADC with PGA 8.5 nV rms Noise

20.5 bits noise free resolution Gain = 128, Output Data Rate = 4.7 Hz

22.5 bits noise free resolution Gain = 1, Output Data Rate = 4.7 Hz

16 bits noise free resolution Gain = 128, Output Data Rate = 2.4 kHz

Output Data Rates up to 4.8 kHz PGA: Gains from 1 to 128 INL 15ppm max (1ppm typ G=1) Offset Drift 5 nV/°C Gain Drift 1 ppm/°C Specified Drift Over Time AVdd = 5V; DVdd = 3V / 5V

24-TSSOPSPI4.7 Hz – 4.8 kHz2 / 46 mA24-Bit

PackageInterfaceOutput Data RateChannelsCurrentResolution

-40°C to +105°C

Temperature

Scientific, Test & Commercial InstrumentsWeigh Scales (Retail, Laboratory,

Industrial Hopper & Conveyer Scales)Chromatography for Chemical AnalysisData Acquisition / AnalyzersDataloggers

Industrial AutomationPLC/DCS Analog

Input Module Front-EndsTemperature ControllersPressure Measurement

Medical InstrumentationPatient Monitoring

Blood Pressure Measurement,Temperature Measurement, Blood Analysis

91

AD7190 – Applications4.8 kHz Ultralow Noise 24-Bit Σ-Δ ADC with PGA

IN+

IN-

OUT- OUT+

+5V

2 mV/VSensitivity

Exceptional precision for low speed & high speed Weigh Scale applications 8.5 nV rms noise (Gain = 128, 4.7 Hz Output Update Rate) 16 bits of noise free resolution (Gain =128, 2.4 kHz Output Update Rate)

Lowest Offset Drift @ 5 nV/°CPower Save Mode via programmable Bridge Power Down Switch (BPDSW)

92

AD719x – Application ExampleWeigh Scale Loadcell or Pressure Sensor Measurement

93

AD7760 24 Bit, 2.5MSPS Sigma Delta ADCKEY BENEFITSKEY BENEFITS High SNR allows accurate digitization

112dB at 78kHz, 100dB at 2.5 MHz Reduced anti aliasing filtering

(Sigma/Delta) Flexibility

Filter Programmability allows application customization

Comprehensive Solution On Chip Buffer/Amplifiers simplify

design - no need for user to select expensive external components

AD7762 AD7763625 kSPS VersionParallel Interface

625 kSPS ThroughputSerial Interface

Resolution Speed Interface Power Supply

Package

24-Bit 2.5 MHz Parallel 5V , 2.5V 64-TQFP_EP

AD7760 Filter Response




Pipelined Converters

ADI : New High Speed ADC Products20

-60M

Hz

SamplingNewly released

75M

Hz

95

DP

D /

>10

0MH

z

AD946716 bit 250MSPS

Highest Ain Performance

AD9648 fam.Dual 14b 125MSPS

100mW/ch – Par LVDS

AD9650Dual 16 bit 105MSPSHighest SNR (375mW/Ch)

AD9253 fam.Quad/Octal 14b

125MSPS 100mW/ch – Par LVDS

AD9434 12-Bit, 370/500 MSPS, 1.8 V ADC

KEY SPECIFICATIONSKEY SPECIFICATIONS A/C Performance at 500Msps

SNR = 65.2 dBFS @ Ain up to 250 MHz ENOB of 10.5 @ fIN up to 250 MHz SFDR = 75 dBc @ fIN up to 250 MHz

LVDS SDR at 500 MSPS (ANSI-644 levels) 1.2 GHz full power analog bandwidth On-chip reference, no external decoupling

required Programmable via SPI

Integrated input buffer and S/H Programmable input voltage range:

1.18 V to 1.6 V, 1.5 V nominal

Low power dissipation 660 mW @ 500 MSP—LVDS SDR mode

Single 1.8 V supply operation SPI Port for configuration and control

Selectable output data format (offset binary, twos complement, Gray code)

Power down Output Test patterns Output timing adjustments

Package Price @ 1k

56-lead LFCSPAD9434-500: $125AD9434-370: $90

Sampling Final Release

Now March2011

AD9434

Key Benefit Lower Power and High Sample Rate Pin Compatible with AD9230: 12-bit 250Msps

AD9484 8-Bit, 500 MSPS, 1.8 V ADC

KEY SPECIFICATIONSKEY SPECIFICATIONS A/C Performance at 500Msps

SNR = 47 dBFS @ Ain up to 250 MHz ENOB of 7.5 @ fIN up to 250 MHz SFDR = 83 dBc @ fIN up to 250 MHz

LVDS SDR at 500 MSPS (ANSI-644 levels) 1.2 GHz full power analog bandwidth On-chip reference, no external decoupling

required Programmable via SPI

Integrated input buffer and S/H Programmable input voltage range:

1.18 V to 1.6 V, 1.5 V nominal

Low power dissipation 670 mW @ 500 MSP—LVDS SDR mode

Single 1.8 V supply operation SPI Port for configuration and control

Selectable output data format (offset binary, twos complement, Gray code)

Power down Output Test patterns Output timing adjustments

Package Price @ 1k

56-lead LFCSP AD9484-500: $36


Now March2011

Key Benefit Lower Power and High Sample Rate Pin Compatible with AD9230: 12-bit 250Msps

AD9467 – 16-Bit, 250 MSPS ADCKey Benefit High effective resolution at high sampling rate.

Temp Package

-40°C – +85°C72 pin 9x9mmPb-Free LF-CSP


Now Oct 2010

KEY BENEFITSKEY BENEFITSOutstanding Performance

SNR = 75.5 dBfs @ Fin = 210 MHz @ 250 MSPSSFDR = 90 dBFs @ Fin = 300 MHz @ 250 MSPSSFDR = 92 dBFs @ Fin = 170 MHz @ 250MSPSSFDR = 100dBFs @ Fin = 100MHZ @ 160MSPS

Excellent LinearityDNL = ±0.5 LSB (16-bit Typical)INL = ±3.5 LSB (16-bit Typical)

LVDS DDR at 250 MSPS (ANSI-644 levels) 900 MHz Full Power Analog Bandwidth Power Dissipation = 1.32W 2.0V p-p to 2.5 Vp-p (default) Input Voltage

RangeIntegrated input buffer

External Reference supportedData Clock Output Provided1.8V and 3.3V supply operation User Controls via Serial port interface

Output Data Format OptionClock Duty Cycle StabilizerOutput Test patternsPower down modes



DACs State of the Art

Product-Market Focus

ADI Confidential

Core Markets

Core Products

101

20-TSSOPSPI1µs1PPM1PPM20-Bit

PackageInterfaceRefresh RateINLDNLResolution

-40°C to +125°C

Temperature

AD5791 – Product Description1uS Update, 1ppm DAC in 0.29cm2

1ppm Linearity 20bit Resolution 1ppm DNL & INL

<1ppm Noise 0.025ppm Low freq Noise 9nV√Hz Wide Band Noise

1µs Settling Time ¼ to ¾ scale settling

<1ppm Drift Offset Drift 0.05ppm/°C

Low Glitch 0.4nV·s (5v); 1nV·s (10v)

Output Spans +5V to ±10V ± 7.5 V to ±15 V Power Supply

AD5791 Functional Block Diagram

102

±10V±5V+10V+5V

±10V ±5V +10V +5V

±10V ±5V +10V +5V

INPUTSHIFT

REGISTERAND

CONTROLLOGIC

POWER-ON-RESET& CLEAR LOGIC

DACREG

20-BITDAC

A1

+

-

Feedback & “Matched Resistors” – Eases Drive Amp Selection

MRI DAC Requirements:High Resolution/Accuracy

18-20 bits minimum for ≥3.0Tesla SystemsLow Noise

Lessens unwanted image artifacts therebyreducing the need for multiple MRI scans

Low DriftEliminates system

calibrationsFast Settling Time

Reduces scan time

AD5791 Ideal for MR Imaging ApplicationsExceeds All Digital-to-Analog Converter Requirements for MRI

103

AD5791 Exceeds AllAD5791 Exceeds AllMRI DAC RequirementsMRI DAC Requirements

Magnet

RF Coil

Patient

GradientCoil

DigitalControl

AD57911ppm DAC

Amp ADC

Amp

HV

-HV

HV Gradient CoilSupply Control 20-Bits

www.analog.com

AD5422 Current Source & Voltage Out DAC– 16 Bit, 4-20mA , ±10V Single Channel Configuration for Isolated

PLC Systems 16-Bit Resolution

IOUT 4mA-20mA, 0mA-20mA or 0mA-24mA ±0.01% FSR TUE 4ppm/oC Output Drift

VOUT 0-5V, 0-10V, ±5V, ±10V 10% over-range 0.01% FSR TUE 3ppm/oC Output Drift Force & Sense capability

Functionality Internal 5V 10ppm/oC Reference Diagnostics/Fault detection Output Loop compliant AVDD-2.5V

Resolution Features Temp Range Interface Power Supply Package

16-Bit Fault Detection

-40oC to +85oC Serial

12V to 48V or±12V to ±24V

24 – TSSOP40 - LFCSP

Related ProductsAD5412

12 Bit Version Similar Functionality

www.analog.com

Sensor i/ps : Thermocouple, RTD, Loadcell, Pt100, Gas, Flow etc

XTAL Sensor

Mux

Sensor SensorSensor

LCD Display A

Du

MA

Du

M

DSP

Measures climate,

gas, light intensity,

Flow rate, temp etc.

AD779xAD719x ADC

Vout to 4-20mACircuitry

DAC

Reference

Standard 4 to 20mACommunication or bipolar Voltage Output

AD5422

16-Bit Quad Industrial V/I Output DAC with Thermal Control

IOUT Range: 4-20mA, 0-20mA or 0-24mA 0.06% TUE Accuracy 5ppm/oC Output Drift

VOUT Range: 0-5V, 0-10V, ±5V, ±10V 20% Over-range. 0.04% TUE Vsense + & Vsens -

Functionality Flexible Digital Interface On-chip Diagnostics Integrated per channel DC-DC for

Dynamic Power Control Internal 5ppm/oC Reference Housed in 64 – LFCSP (9 x 9mm)

AD5755 – Quad 16 bit V/I DAC with Dynamic Power Control

Sampling , Release Spring 2011

Related ProductsAD5735 AD5755-1

12 Bit Version Similar

Functionality

16bit version HART Compliant Vsense +

AD5755 Block DiagramSmart and High-

Efficiency DynamicPower Control (DPC)

Smart and High-Efficiency DynamicPower Control (DPC)

PrecisionLinear SignalProcessing

PrecisionLinear SignalProcessing

Precision 16-bit DAC

Precision 16-bit DAC

No Calibration Required (Full Channel Spec)I/P O/P

107

Leverages ADICore Technologies

4 X Output (V/4-20mA) Channels

4 X Output (V/4-20mA) Channels

DiagnosticsDiagnostics

www.analog.com

AD5764 – ±15V 16-Bit Accurate Quad DAC- Bipolar Cores KEY BENEFITSKEY BENEFITS Small: 32 lead TQFP Full 16 Bit Accuracy

1 LSB DNL 1 LSB INL(C-Grade)2/4 LSB INL (B/A-Grade)

Ease of Application On chip reference buffersBipolar output generated from single 5V Ref

Output control during power on/offOutput clamped to 0V during power on/off

Resolution Output Channels INL, Max Interface Package

16 Bits ± 10.5V 4 1 LSB SPI 32-TQFP Released

Status

Related ProductsAD5764R AD5744/44R AD5762R

Same Functionality 16 bit, Quad Internal 10ppm Reference.

Same Functionality 14 Bit, Quad 44 R – Int 10ppm Ref

Same Functionality 16 bit, Dual Internal 10ppm Reference

ADI Confidential

KEY FEATURESKEY FEATURES

16-Bit ±1LSB INL & DNL Low Noise 12nV/rtHz 3V and 5V Operation

VDD = 2.7V to 5.5V Fast Settling @ 1µs Low Glitch: 1.1nV-sec VLOGIC Pin with 1.8V operation

Gain Error TC: ±0.1ppm/ºC Zero-Code Error TC: ± 0.05ppm/ºC Bipolar Zero TC: ±0.2ppm/ºC (AD5542) 50MHz SPI compatible Interface

Increased Interface Flexibility

AD5541A/2A –16-Bit ±1LSB, 1ɥs, DACUpgrade to AD5541/42

Related ProductsAD5512A AD5551/52

12 – bit Similar Functionality Feedback resistors

for bipolar outputs

Similar Functionality 14 bit version 8 & 14 ld SOIC

Resolution Feature Temp range Interface Power Supply Package

16-Bit 1µs Settling -40oC to +125oC Serial 2.7V to 5.5V

8 & 10 – LFCSP (41) 10 – MSSOP (41)10 &16 – LFCSP (42) 16 – TSSOP (42)

ADI Confidential

AD5664R –16-Bit Quad nanoDACTM in 3x3 LFCSP package

KEY BENEFITSKEY BENEFITS High Performance

16-Bit Resolution, 12LSB INL 10-MSOP / 3x3 10-LFCSP….and also includes an on-chip 5ppm/°C Reference70% Space saving over competition

Ideal for base-stations, optical transceiversReference and non reference optionsDual Configuration also available

Resolution Output Channels INL, Max Interface Package

16-Bits 0-5 V 4 ± 12 LSB SPI 10-LFCSP/MSOP

AD5644R/24R AD5663R/43R/23R AD5664/24 & AD5663 Same as AD5664R except 14/12-Bits Resolution

Same as AD5664 except 16/14/12 Bits Dual Configuration

Same as AD5664R except No on-chip reference Quad and Dual configuration

A Member of the nanoDAC family

AD5291/2 – 256/1024 Tap, 30V or ±15V, 1% R-Tol, 20-TP Wiper Memory digiPOT+KEY FEATURESKEY FEATURESSingle-Channel, 256/1024 Tap resolution20 kΩ, 50 kΩ and 100 kΩ Nominal

ResistanceCalibrated 1% Nominal Resistor Tolerance+4.5V to +30V Single-Supply Operation±4.5V to ±15V Dual-Supply Operation20-TP – 20-Time Programmable Memory

ApplicationsApplicationsMechanical potentiometer replacement Instrumentation: gain, offset adjustmentProgrammable voltage to current

conversionProgrammable filters, delays, time

constantsProgrammable power supplySensor calibration

AD5291: $2.29AD5292: $2.62

-40°C to 105°C

Price @ 1KTemp

High Speed DAC Category Overview

TxDAC® Low Power Base Band DAC 8-16b ; Up to 500MSPS

TxDAC+ ® : IF ClassSignal Processing DACsUp to 1.25GSPSw/ Interpolation & NCO

RF DACUp to 2.5GSPSw/ Interpolation & NCO + MixModeTM

Sam

ple

Rat

e, I

nte

gra

tio

n,

Per

form

ance

Frequency (GHz)

0.5 1.0 1.5 2.0 2.5 3.0

FDAC

Signal

Image

Frequency (GHz)

IF FDAC

Frequency (GHz)

FDAC

Frequency (GHz)

FDAC

MixMode

112

Baseband-Class TxDAC®

High Performance / Low Power Transmit DACs

AD9117/16/15/1414-8b, 125 MSPSCMOS Inputs40p QFN (6x6)

Dual

AD9747/46/45/43/4116-8b, 250 MSPSCMOS Inputs72p QFN (10x10)

Dual

AD9783/81/8016-12b, 500 MSPSLVDS Inputs72p QFN (10x10)

Dual

AD9717/16/15/1414-8b, 125 MSPSCMOS Inputs40p QFN (6x6)2mA output current

Dual

AD9707/06/05/0414-8b, 175 MSPSCMOS Inputs32p QFN (5x5)2mA output current

Single

Hig

her

Ban

dw

idth

Lo

w P

ow

er

Sm

all

Fo

otp

rin

tReleased

IF-Class Signal Processing TxDAC+®

AD912516b, 1.0 GSPSInterpolation + Fine NCO72p QFN (10x10)

AD914816b, 1.0 GSPSInterpolation + Fine NCO196b BGA (12x12)

AD914616b, 1.25 GSPSInterpolation + No NCO48p QFN (7x7)

AD912216b, 1.25 GSPSInterpolation + Fine NCO72p QFN (10x10)

AD9788/87/8516-12b, 800MSPSInterpolation + Fine NCO100p QFP (16x16)

CMOS Interface LVDS Interface

Du

al D

AC

Qu

ad D

AC

Preferred

Not Preferred

RF-Class TxDAC® & TxDAC+® High Performance MixMode™ DACs

AD973914b, 2.5 GSPS

Single

AD978914b, 2.4 GSPSHighly Integrated

Single

AD9736/35/3414-10b, 1.2 GSPS2x Interpolation

Single

1st Generation 2nd Generation

All LVDS Inputs

Preferred

Not Preferred

MxFE® RoadmapIntegrated Mixed-Signal Front-End

AD9963/61Low Power

AD9863/2/1/0

PartTx Rx

PackageResolution Fs

Resolution Fs

AD9860 10b128

MSPS10b 64 MSPS 128p LQFP (16 x 22)

AD9861 10b200

MSPS10b

50 / 80 MSPS

64p LFCSP (9 x 9)

AD9862 14b128

MSPS12b 64 MSPS 128p LQFP (16 x 22)

AD9863 12b200

MSPS12b 50 MSPS 64p LFCSP (9 x 9)

AD9963/61 12b/10b130

MSPS12b/10b 100 MSPS

72p LFCSP (10 x 10)

1st Generation 2nd Generation

Preferred

Not Preferred

Cosimo CarrieroSenior Field Applications Engineer

[email protected]

Mobile: +39.334.6533599

Cosimo CarrieroSenior Field Applications Engineer

[email protected]

Mobile: +39.334.6533599

the world leader in high performance signal processing solutions a/d and d/a conversion cosimo...

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