the wire in ics

7/26/2019 The Wire in ICs

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THE WIREIn the first lessons we have studied the main devices of the CMOS process, i.e., the MOS transistor as main

element and the diode as parasitic element. In truth, in digital integrated circuits, there is another parasitic

element: the wire. This element is acuiring more and more importance as the device dimensions shrin!

and the operating freuenc" is increased. #ntil now, we have alread" considered the wire as a short circuit,

a simple line carr"ing the signals with no apparent effect on circuit performance. $ctuall", the wire is a

mi%ture of resistances, inductances and capacitances. &e aware that these elements are not located in a

specific point, 'ut the" are rather distri'uted over the length of the wire.

The effects of these parasitics on digital circuits are:

(. an increase in propagation dela" or, euivalentl", a drop in d"namic performance)

*. an increase of the energ" dissipation +due to the capacitance associated to the wire)

-. an introduction of e%tra noise sources, which affects the relia'ilit" of the circuit, due for e%ample to

the capacitive coupling 'etween adacent wires.

In this lesson we will focus on the effect of a wire in terms of propagation dela".

/et us ma!e an e%ample to understand how comple% is the modeling of the interconnection s!etching a

simple wire, for e%ample in metal (, supposing that this interconnect is 'uilt near another wire in metal (.

0o other interconnections are present. O'viousl", we need to consider the su'strate that acts as a ground

plane. It1s a ver" simplistic case. The most complete model of this wire has to ta!e into account the

inductance, the resistance and the capacitance that are distri'uted over the length of the line, as well as

the coupling capacitances. The resulting model is ver" comple%2

0ow the uestion is: is it worthwhile to consider all these parasitics to assess the contri'ution of a wire3

O'viousl" the answer is negative, especiall" for a first order and hand4made anal"sis.

In order to simplif" the pro'lem of modeling a wire, we must consider three important rules:

( Inductance can be neglected if the wire resistance is large or if the rise/fall time of the input

signal is large.

5e will come 'ac! to this point later, when we 'riefl" anal"6e the transmission line model. In

general, in an integrated circuit the inductance of the line can 'e neglected. It 'ecomes an issueonl" at 'oard level where the wire resistance is small and the time4of4flight of the electromagnetic

wave is no longer negligi'le or for advanced technologies where low4resistivit" material, such

copper, is used for the interconnections.

* When the wire is short and when the equivalent resistance of the driver is large, the wire

resistance can be serenel neglected.

In this case, the wire is a capacitance. The wire can 'e modeled with a capacitance to ground or

with capacitances to the neigh'oring wires. The latter can give rise to coupling effect worsening the

relia'ilit" of the circuit.

- When the separation between nearb wires is large or when the wires run for a short distance,

the inter!wires capacitance can be neglected.

The designer must own the a'ilit" to discriminate 'etween dominant and secondar" effects and to choose'etween different models. 0ow, let1s discuss more in detail how to evaluate the capacitance, the resistance


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and the inductance of a wire. $fter this discussion, different models suited to catch the contri'ution to the

dela" of a wire will 'e presented.

"#$#"IT#%"E/et us consider a rectangular wire placed a'ove the su'strate.

If the width 5 of the wire is su'stantiall" larger than its thic!ness 7, it ma" 'e assumed that the electrical4

field lines are orthogonal to the capacitor plates, and that its capacitance can 'e modeled '" the parallel!

plate capacitance, also called area capacitance. The capacitance is

pp di

di

WLC

t= ,

where distands for the dielectric permittivit" given '" the product of r8. di is the relative permittivit",

while 8 is the permittivit" of the vacuum eual to 9.9; % (84(*

, (=- of the silicon permittivit" +((.?. Silicon 0itride is not used as

insulating material due to a larger relative permittivit" +?.. It1s onl" used as sacrificial la"er in the CMOS

process steps. In the future, to reduce the capacitance of the wires, aerogel can 'e adopted since it

features a lower permittivit" +see the ne%t ta'le.

The important message from the previous euation is that the capacitance is proportional to the

overlapping area.

#nfortunatel", a wire rarel" presents a width much larger than its thic!ness. $ small width is desira'le to

shrin! the la"out and to lessen the overhead, thus to !eep the resistance low the height cannot 'e too

much low. In our reference technolog", a metal * for e%ample has a minimum width of 8.;m and a height

of (m. Thus, the aspect ratio, i.e. the ratio 'etween the width and the thic!ness of the wire, can 'e lower

than (. #nder these circumstances, the parallel plate appro%imation is no longer valid. In fact, the

contri'ution of the side4walls to the su'strate cannot 'e longer ignored. The contri'ution due to the

sidewall is also called fringing capacitance. In fact, fringe means edge.

The pro'lem can 'e simplif" considering that a wire with a height 7 and a width 5 can 'e decomposed as

the sum of a c"linder having a diameter of 7 and a rectangular wire with a width eual to w@547=*.


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Thus, considering a wire of length /, the overall capacitance results

*

*ln (

tot

di di

didi

C w

tL tH

+

+

.

The point is that the fringing capacitance is a mild function, 'eing the logarithm a mild function of its

argument, of the ratio 'etween the dielectric thic!ness and the height of the wire. The fringing capacitance

is usuall" the most dominant contri'ution, also '" a factor of 4(8, for 5=t di ratio lower than (,

appro%imatel".

/et1s tr" to plot the two contri'utions, the parallel4plate and the fringing capacitance, as function of the

5=tdi ratio, normali6ed to the wire length / and considering the silicon dio%ide as dielectric. The former

contri'ution increases linearl" with the aforementioned ratio, the latter instead is almost independent. The

following graph reports the area capacitance and the overall capacitance for two values of the 7= tdiratio,

8. and (. The difference is light. It1s worth pointing out that the overall capacitance is appro%imatel"

constant for 5=tdiratio lower than (. O'serve that "our reference 'oo! is ust a 'it mess" since it indicatesthe dielectric thic!ness first with tdiand then with 7.

The previous graph refers to the so called microstripline, which is a wire surrounded '" dielectric a'ove a

ground plane. The situation is more complicated if "ou consider that toda"1s processes offer man" la"ers of

interconnect. In this scenario, the assumption that a wire is completel" isolated from its surrounding

structures and is onl" coupled to ground 'ecomes unrealistic.

The situation can 'e li!e the one depicted in the following figure.

W

H

W/tdi

H/tdi=1H/tdi=0.5Cpar-plate

Htdi

W


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Considering the top4left wire, its capacitive components are not towards the grounded su'strate, rather

than to the near'" wires. &oth parallel4plate and fringing contri'utions are present. Clearl", this situation is

ver" tangled and difficult to anal"6e. The overall parasitic capacitance affecting the considered wire can 'e

evaluated '" means of a parasitic e%tractor in the la"out environment. 7owever, it1s clear that this situation

is not the 'est in term of capacitance. The 'est scenario is when the wire is not close to other wires and

well distant from the su'strate, i.e., with a small 5=tdiratio.0ow, if I want to estimate '" hand the parasitic capacitance of a wire, li!e the one ust considered, what

can I do3 T"picall", for a given technolog" process, a ta'le is given reporting the parallel4plate and the

fringing capacitance contri'utions for a wire in a certain la"er with respect to another wire in another la"er.

This ta'le reports the contri'utions for the 8.*m process technolog". The parallel4plate capacitance is

reported in the white lines e%pressed in a


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The metal wires displa" the highest inter4wire capacitance due to the largest height. It1s clear that this

metal has to 'e used to distri'ute around the chip the glo'al signals, li!e the cloc! and the power supplies.

/et1s ma!e an e%ample to show how to compute the capacitance of a wire. Consider a wire in aluminum of

(8cm length and (m width routed in the metal( la"er of our 8.*4m CMOS process. This wire is no

surrounded '" other wires. The capacitance to ground can 'e computed considering the first ta'le as

*-8 (8 ( ;8 * (8 - 9 ((

tot

WL L

aF aF C m m m pF pF pF m m

+ = + =

.

The factor of * in the a'ove e%pression ta!es into consideration the two sides of the wire in order to

correctl" evaluate the perimeter of the wire.

0ow, let us suppose that a second wire in metal( is 'uilt alongside the first one, at the minimum distance.

5e can estimate the inter4wire capacitance from the second ta'le as

int> (8 >.

L

aFC m pF

m

=

.

Clearl", adding this wire alongside the first one reduces the contri'ution due to the fringing capacitance,

since some of the field lines do not close to ground 'ut to the adacent wire. This e%ample shows how much

the evaluation of the wire capacitance can 'e trou'lesome.

RE&I&T#%"EThe resistance of a wire can 'e calculated '" means of the well4!nown e%pression:

LR

WH=

where is the resistivit" of the material in m.

The most commonl"4used material is the aluminum which a resistivit" of *.?%(849

m. 5e !now that it1s

commonl"4used due to its low cost and for its compati'ilit" with the CMOS process.

The tungsten, which is sometimes adopted for the first level of metali6ation la"er since it does not feature

pro'lems of electro4migration, has a larger resistivit". It1s a factor of * larger than the aluminum resistivit".The copper, which is material adopted for the upper level metals in advanced technologies, is less resistive,

'ut it is not commonl" implemented since the copper deposition is not trivial.

/oo!ing to the e%pression of the resistance, since 7 is a constant for a given technolog", the resistance can'e e%pressed as

L LR R

H W W

= =

.

The ratio H is !nown as sheet resistance and it1s e%pressed in per suare. In fact, considering a wire

with 5@/, i.e., a suare, the resistance of the wire is R

. To assess the resistance of a certain wire, it1s

sufficient to multipl" the sheet resistance '" the ratio /=5, which represents the num'er of suares.

In the following ta'le, "ou can o'serve the sheet resistance of the various interconnect la"ers in a modern

ICs.


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The n4 or p4well has a sheet resistance of appro%imatel" (!per suare. The nA or pA diffusion has a sheet

resistance which is a factor (8 lower, appro%imatel" (88per suare. If we silicide the diffusion, i.e. a la"er

of a compound material is added on the surface of the diffusion, the resistance per suare is reduced '" a

factor larger than (8. The silicide is a compound material formed '" silicon and a conductive material, li!e

Tungsten Bisilicide +5Si* or Titanium Bisilicide +TiSi*.


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8(

r r

cv

lc = = ,

where c8is the light speed in free air +-%(89m=s or euivalentl" -8cm=ns, while rand rare the relative

permittivit" and permea'ilit", respectivel", of the surrounding dielectric. Thus, 'eing r@-.> and r@( for

the silicon dio%ide, the speed of an electromagnetic wave is a'out half the light speed.

/et1s ma!e an e%ample considering a wire in the first la"er of aluminum in our reference process

surrounded '" the dielectric and a'ove the su'strate which acts as ground plane. The capacitance per unit

length can 'e estimated as

( )-8 * ;8c W aF m= + .

5e can derive the inductance per unit lenght from the previous formula +8 r rv c = as

*

8

r rlc c

=

.

Thus, for 5@(m the capacitance per unit length is ((8ap7=m, close to the value estimated 'efore for '" means of the inductance formula. 0ow, assuming a

resistance of 8.8?=um, we can evaluate at which freuenc" the inductive impedance is eual to the

resistance of the wire. It comes out

* -8*

rfl r f GHz

l

= = .

These num'ers indicate that the inductance 'ecomes an issue in integrated circuits for freuencies that are

well a'ove (8 D76.

E)E"TRI"#) *+'E)ntil now, we have studied how to compute the capacitance, the resistance and the inductance of a wire.

0ow, we are interested in evaluating the effect of this parasitics on the propagation dela".


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( the distri'uted C model is complicated and there is no closed form solution)

* we want to o'tain a first estimate in a short time, rather than a more correct solution, which can 'e

easil" o'tained '" means of a simulator)

- finall", as we will see in the following, adopting the lumped C model, we are a'le to appro%imate

the distri'uted model of the wire.

/et1s come 'ac! to the previous pro'lem with an inverter driving a wire and a capacitive load. In order toassess the propagation dela" we can model our inverter as a voltage generator +turned on at the time t@8

in series to the euivalent resistance, the lumped C model of the wire and the load. It result in a *4pole

networ!, as depicted on the right.

7ow can we assess the propagation dela"3 To this aim, a famous theorem ma" come in hand": the so called

Jlmore theorem.

E)*+RE THE+RE*

This theorem allows to assess the dela" of a networ! '" evaluating the first4order time constant of the

networ! +which is euivalent to the first moment of the impulse response. The theorem can 'e applied if

three conditions are verified:

(. the networ! has a single input node)

*. all the capacitors are 'etween a node and ground)

-. the networ! does not contain an" resistive loops +which ma!es it a tree.

These conditions are verified in our previous e%ample.

0ow, let us consider a node i where we want to evaluate the dela" of the input signal. The time constant

associated to this node can 'e assessed as

(

N

Di k ik

k

C R=

= .


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0ote that appl"ing the Jlmore theorem to this networ! having different 'ranches it1s euivalent to shift the

capacitors C*and C;onto the path from the source to the output node, neglecting the resistances *and ;.

Then, the dominant time constant of the new networ! has to 'e evaluated.


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The voltage at the node i of this networ! can 'e determined '" solving the following differential euation

( ) ( )( (i i i i i V V V V Vc Lt r L

+ =

,

with / that tends to 8.

It "ields the famous diffusion euation:*

*

V Vrc

t x

=

where K is the voltage at a particular point of the line and % is the distance 'etween that point and thesource.

This euation is difficult to 'e solved and no closed form solution e%ists for this pro'lem. The voltage at the

end of the line can 'e appro%imated as:

( )

( )

*

*.-> >.;;(

out

8* tEEC

;

K ( (.- 8.-

*erf+ : d

tLLC

out

t t

t

RC

x

RC

RCV t erf

t

t e e

x e t

=

= +

=

where and C are the overall resistance and capacitance of the line, respectivel".

0ow, if we plot the solution of this differential euation for different point of the line we get the following

graph. 0ote how the voltage diffuses from the onset to the end of the line and note how the dela"increases moving rightwards.

Moreover, we can compare the results o'tained '" solving the diffusion euation with the results of the

lumped C model:

0ow, loo! at the propagation dela" evaluated with the distri'uted model. This dela" is 8.-9C, which is

roughl" half the dela" estimated '" the lumped model.


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$nd what did we get when we considered the wire as formed '" 0 cells having the same resistance and the

same capacitance and appl"ing the Jlmore dela" formula3 $ppro%imatel" the same result, that is,

ln+*C=*@8.-;C. Thus, from now on, we can consider that a line with a resistance and a capacitance C

gives a dela" eual to ln+*C=*, instead of ln+*C, in order to ta!e into consideration the distri'uted effect

of capacitance and resistance.

0ow, let1s consider again the wire with a length /, specific capacitance c and specific resistance r, so thatw@r/ and Cw@c/.

In order to ta!e into the right consideration the effect of the distri'uted line, we can adopt for the line the

so called model or the T model, which 'oth give the same result, and then appl" the Jlmore formula.

$ppl"ing the model, we get

( ) ( ) ( )int e e int * * *w w w w

D q q w w eq

C C C R

C R C C

= + + + = + + .If we appl" the T4model we get the same result, 'eing

( ) ( )int e e int * *

w w w

D q q w eq

R C RC C C C

= + + = + +

.

0ote that the last contri'ution is the time constant of the line +thus it1s dela" evaluated with the

distri'uted model.

0ow, a designer ma" as! whether 'rea!ing a long wire in small pieces and inserting an inverter 'etween

two adacent segments of the line can lead to an improvement in terms of overall propagation dela". This

e%pedient comes from the fact that the propagation dela" of a wire is a uadratic function of its length.

7ence, 'rea!ing the line in small segments helps to reduce this uadratic dependence. Clearl", the pri6e of

this techniue is that we have to insert 'uffers that add their dela" while dissipating power consumption./et us consider a wire of length / featuring a specific resistance r and a specific capacitance c +w@r/ and

Cw@c/. This wire is driven '" a minimum4si6e inverter and terminated '" a similar inverter.


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The dela" time is now( ) ( )int e e int e

*

N

D q q q

cL rL rLN C C

N N N

= + + + +

.

&" differentiating this euation with respect to the varia'le 0 +the num'er of digital 'uffer, also !nown in

this case as repeaters and euating this derivative to 6ero, we can o'tain the optimum num'er of

segments for the considered wire.

It results( ) *

int e *

int e

* 8* ;

N

D

q

q

d crL cr C N L

dN N C

= = = .

5hen the following condition is verified +ust su'stituting 0 with * in the previous euation,

int e( qCL

cr ,

it1s convenient to 'rea! the line and insert 'uffers.


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/et us consider our first level of aluminum metal in the 8.*m CMOS process that we use as reference

technolog". In this case, [email protected]?=um, c@((8ap7=m, 8@8and v@c=*@(ns=cm.

The previous ineualit" results

988rt

L mlc

.

5e can plot the two ineualities in a graph having as hori6ontal a%is the rise time and as vertical a%is thelength of the wire.

0ote that, since in our reference technolog" there can no e%ist a rise time lower than (8ps, the inductance

never matters. If we consider a metal, which has a larger height and thus a lower specific resistance, the

hori6ontal line translates upwards and the region where inductance matters 'ecomes larger. $t a 'oard

level, i.e., on a printed circuit 'oard, where the wires are thic!er and so the specific resistance is much

smaller, the transmission line model can 'e the most appropriate one in certain cases.

$lso in the advanced integrated technologies, where copper is adopted for the upper level

interconnections, this model can come in hand".

In fact, let1s assume a copper wire with a characteristic impedance of *88and a resistance of 8.8*=m.The resulting ma%imum wire length euals 9mm. This length corresponds to a critical rise time of -psec,

which is feasi'le in advanced technologies.

1ps 10ps 100ps 1nstr

10um

100um

1mm

10mm

L

RC delay dominates

rise time dominates

inductance matters


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I*$#"T +- TE"H%+)+ &"#)I% +% WIRE $ER-+R*#%"ESimilar to what we have done for the MOS transistor, it is worthwhile to e%plore how the wire parameters

are affected '" the technolog" scaling.

$s transistor dimensions are reduced, also the interconnect dimensions have to 'e reduced to ta!e full

advantage of the scaling process.

The simple approach consists in scaling down all the ph"sical dimensions of the wires '" the same factor S,

e%cept for the length. Thus, the minimum width 5, the height 7 and the dielectric thic!ness tdiare scaled

down '" S. $s far as the length of the wire is concerned, we need to distinguish 'etween local and glo'al

interconnections. Concerning the local interconnections, it can 'e inferred that their length decreases since

transistors are closer '" the same factor S. Instead, concerning the glo'al interconnections, we !now that,

while transistor dimensions have continued to shrin! over the last decades, the chip si6es have graduall"

increased. In fact, the chip si6e increases '" a'out N per "ear. Thus, we can assume that the glo'al

interconnections are scaled '" a factor of SC, 'eing SCless than (.

#nder these conditions, the wire performance show the trend depicted in the following ta'le. &e aware

that this is onl" a first4order anal"sis. It does not ta!e into account such aspects li!e fringing capacitance

and advanced features, li!e low4! dielectrics and low4resistance interconnect materials.

0ote that in local interconnections the resistance increases while the capacitance decreases, so that the

dela" does not scale down and remains constant. The pro'lem is e%acer'ated in glo'al interconnections

where the dela" even increases2 This is the reason wh" with the technolog" scaling the wire acuires moreand more importance and need to 'e treated and modeled at the manner of the transistors.

It1s evident that the ideal scaling approach clearl" has pro'lems, as it causes a rapid increase in wire

resistance. This has suggested a new wa" of scaling the wires, which can 'e identified as constant

resistance where the thic!ness of the wire is not scaled 'ut left unchanged. This approach seems

advantageous 'ut it 'rings to foreground the effects of fringing capacitance and inter4wire capacitance.

5e can introduce the factor c+cL( that ta!es into account the increases of the lateral capacitance of

the wire, alwa"s considering that the parallel4plate capacitance contri'ution is decreased '" the reduced

dimensions of the wire. 5e get the following ta'le.

Considering cES we have a small advantage concerning the local interconnections while the pro'lem of an

increased dela" in the glo'al wires is still present.This consideration e%plains wh" the technologists are tr"ing to improve the wire material +copper instead of

aluminum and the insulation material +low4! dielectrics.

the wire in ics

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