Upload File

the verilog primer - university of torontobharrington/cscb58/labs/verilogprimer.pdf · by steve...

  • Home
  • Documents
  • The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in
47
The Verilog Primer By Steve Engels

Upload: others

Post on 31-Oct-2020

3 views

Category:

Documents


0 download

Report

TRANSCRIPT

Page 1: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

TheVerilogPrimerBySteveEngels

Page 2: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

SoyouwanttolearnVerilog

§  VerilogisanewlanguagethatisusedalotintheCSCB58labs.It’snothardtolearn,butitisdifferentfromotherlanguagesthatyou’veseenbefore.

§  ThisprimerismeanttogiveyouasenseofwhatVerilogisabout,andwhatyouneedtoknowinordertogetbyinthelabs.

§  It’salivingdocument,soifthere’sanythingthat’smissingorunclear,letusknow!

Page 3: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

UnderstandingVerilog

§  ThefirstthingtorealizeaboutVerilogisthatitisnotaprogramminglanguage,butisahardwaredescriptionlanguage(HDL).

§  It’susedtodescribewhatthe circuitlayoutneedstolooklike, oncewestartdesigningcircuits thataretoolargeorcomplicated toimplementwithactualchips andwires.

Page 4: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

BasicVerilogExample

§  Forinstance,thisisasimpleANDgate:

§  IfyouhadtocreateasoftwarelanguagethatwouldallowyoutospecifyanANDgatewiththeseinputsandoutputs,whatwouldthespecificationlooklike?

A B

Y

Page 5: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

BasicVerilogExample(cont’d)

§  Itwouldhavetohavea namethatyoucoulduse todescribethegate.ú  e.g.“and”

§  Itwouldhavetoallowyoutospecifytheinputsandoutputsofthegate.ú  e.g.and(Y, A, B) ú  Sincegatescanhavemanyinputsbutonlyoneoutput,theoutputislistedfirst,followedbyallofthegate’sinputs.

A B

Y

Page 6: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ThebasicsofVerilog

§  Verilogisbasedofftheideathatthedesignerofthecircuitneedsasimplewaytodescribethecomponentsofacircuitinsoftware.

§  ThereareseveralbasicprimitivegatesthatarebuiltintoVerilog.

ú  two-inputgatesshownhere,butmulti-inputalsopossible.

Ø  and(out,in,in) Ø  or(out,in,in) Ø  not(out,in)

Ø  nand(out,in,in) Ø  nor(out,in,in) Ø  buf(out,in)

Ø  xor(out,in,in) Ø  xnor(out,in,in)

Page 7: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Creatingmodules

§  Usingbuilt-ingatesisonething,butwhatifyouwanttocreatelogicalunitsofyourown?

§  Moduleshelptospecifyacombinationofgateswithasetofoverallinputandoutputsignals.ú  SpecifiedsimilarlytoCand Pythonfunctions.

ú  Lesslikefunctionsthough, andmorelikespecifyinga partofacar.

Page 8: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample

§  MakinganXORgate.ú  AnXORgatecanbe representedwiththe followinglogicstatement:

ú  Howwouldwedescribealogicequationlikethisinahardwaredesignlanguage?

A B

Y

Y = A·B + A·B

Page 9: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample(cont’d)§  Nottohardtorepresentitinlogicgates.

§  HowwouldyouspecifytheANDandORgates?

A B

A B

Y

and(__,B,__) and(__,A,__) or(Y,__,__)

Page 10: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample(cont’d)

§  Wiresthatareusedinternallyinthecircuittoconnectcomponentstogetheraredeclaredandlabeledusingthewirekeyword.ú  Labeltheoutputofeachgate,sothatyoucanrefertoitwhenspecifyingtheinputsofothergates.

A B

A B

Y and(__,B,__) and(__,A,__) or(Y,__,__)

Page 11: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample(cont’d)

§  Note:thewirenamesarenotbuiltinornamedaccordingtoanyconvention.Thenamesofthewiresisatthediscretionofthedesigner.

A B

A B

Y

not_a

not_b

b_not_a

a_not_b

Page 12: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample(cont’d)§  Theresultis thecircuit description ontheright.

§  Theorderof thefivelines atthebottom doesn’tmatter.ú  Remember:Verilogisahardwaredescription,notaprogramminglanguage,sotheresultisthesame.

wire not_a, not_b wire a_not_b, b_not_a and(b_not_a, B, not_a) and(a_not_b, A, not_b) or(Y, b_not_a, a_not_b) not(A, not_a) not(B, not_b)

Page 13: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample(cont’d)

§  Themoduleisnearlydone!

§  Onlymissingthreethings:1.  Semicolonsat

theendofeachline.

2.  Statementsdescribingthecircuit’sinputandoutputs.

input A, B; output Y; wire not_a, not_b; wire a_not_b, b_not_a; and(b_not_a, B, not_a); and(a_not_b, A, not_b); or(Y, b_not_a, a_not_b); not(A, not_a); not(B, not_b);

Page 14: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample(cont’d)§  Lastmissingfeature:3.  Keywords

layingoutthestartandendofthemodule,aswellastheinputandoutputsignals.

module xor_gate(A, B, Y); input A, B; output Y; wire not_a, not_b; wire a_not_b, b_not_a; and(b_not_a, B, not_a); and(a_not_b, A, not_b); or(Y, b_not_a, a_not_b); not(not_A, A); not(not_B, B); endmodule

Page 15: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Modulereview

§  Creatingamodulefollowsafewsimplesteps:1.  Declarethemodule(alongwithitsname,itsinput

andoutputsignals,andwhereitends).2.  Specifywhichofthemodule’sexternalsignalsare

inputsandwhichareoutputs.3.  Providelabelsfortheinternalwiresthatwillbe

neededinthecircuit.4.  Specifythecomponentsofthecircuitandhow

they’reconnectedtogether.

Page 16: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

AnoteaboutStep#4§  Therearealternatewaystoexpresstheinternallogicofamodule.ú  assignstatements.

and(Y, A, B); assign Y = A & B;

or(Y, A, B); assign Y = A | B;

not(Y, A); assign Y = ~A;

Page 17: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Verilogoperators

§  CandPythonhaveoperators,suchas:ú  +,-,<,==,etc.

§  Verilogoperatorsú  “Bitwise”operations takemulti-bitinput values,andperform theoperationon thecorresponding bitsofeachvalue.

ú  Moreoperatorsexist, butthisisenoughfornow.

Operator Operation

~ BitwiseNOT(1’scomplement)

& BitwiseAND

| BitwiseOR

^ BitwiseXOR

! NOT

&& AND

|| OR

== Testequality

Page 18: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ModuleExample,revisited

§  Thisalsoworks,butcanbeeasiertoexpress.

module xor_gate(A, B, Y); input A, B; output Y; assign Y = A & ~B | B & ~A; endmodule

Page 19: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Usingmodules

§  Onceamoduleiscreated,itcanbeusedasacomponentofothermodulesthatyoucreate.ú  Example:halfaddercircuit.

module half_adder(X, Y, C, S); input X, Y; output C, S; and(C, X, Y); xor_gate(S, X, Y); endmodule

Page 20: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

MakingamuxinVerilog

§  Rememberhowamuxworks:

module mux(X, Y, S, M); input X, Y, S; output M; assign M = X & ~S | Y & S; endmodule

Y M

X

S

0

1 M = X·S + Y·S

Page 21: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

3-bitmuxinVerilog

§  Howaremultipleinputs handledbyVerilog?ú  e.g.3-inputmultiplexers.

§  Usesquarebracketcharacterstoindicatearangeofvaluesforthatsignal.

Y

M X

S

n

n

n 0

1

module mux(X, Y, S, M); input [2:0] X, Y; // 3-bit input input S; // 1-bit input output [2:0] M; // 3-bit output ...

Page 22: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

3-bitmuxinVerilog

§  Continuing3-bitmuxexample:

module mux(X, Y, S, M); input [2:0] X, Y; // 3-bit input input S; // 1-bit input output [2:0] M; // 3-bit output assign M[0] = X[0] & ~S | Y[0] & S; assign M[1] = X[1] & ~S | Y[1] & S; assign M[2] = X[2] & ~S | Y[2] & S; endmodule

Page 23: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Anoteaboutranges

§  Whenindicatingthatalabeledsignalrepresentsseveralinputwires,thenotationfortherangecanvary:ú  e.g.input [2:0] X, Y; or

input [0:2] X, Y;

§  Botharelegal;thefirstmeansthatthefirstbitsoftheinputsarereferredtoasX[2]andY[2].ThesecondmeansthatthefirstbitsoftheinputsarereferredtoasX[0]andY[0].

Page 24: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Endofcombinationaldesign

§  Everythingsofarhasbeenaboutspecifyingcombinationalcircuits.ThenextsectionwilldiscusstheelementsofVerilogthatarisewhenyouincorporatesequentialcircuits.

§  Ifyou’vebeenreadingalltheseslidesinonesitting,thisisagoodtimetostandup,getsomethingtoeatordrink,andstretchwhileyouabsorbthethingsyou’vejustread.

Page 25: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in
Page 26: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

ReflectionsonVerilog

§  Bynow,you’veseenseveralelementsoftheVeriloglanguage,butit’sgoodtoputthemintoperspectiveagain.

§  Verilogisusedtospecifycircuitdiagrams.ú  Ifyouhadtodescribeacircuitdiagramintextform,theresultwouldstronglyresembleVerilogsyntax.

“IneedtwoANDgates,onewithinputsAandB,theotherwithinputsCandD,withanORgatewhoseinputsaretheoutputsofthetwoANDgatesandwith

anoutputcalledY…”

wire ab, cd; and(ab, A, B); and(cd, C, D); or(Y, ab, cd);

Page 27: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

MorereflectionsonVerilog

§  Ifyoucandescribeacircuitdiagram,youhavetheabilitytospecifyyourcircuitinVerilog!

§  Verilogalsotriestoprovideshortersyntaxfordescribingcertaincircuits.ú  Example:Simplebooleancircuits:

wire ab, cd; and(ab, A, B); and(cd, C, D); or(Y, ab, cd);

assign Y = A & B | C & D;

*Quartusmakestheseequivalentatcompiletime!

Page 28: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Othersimplificationsyntax§  Whataboutsequentialcircuits?

ú  i.e.circuitsinvolvingflip-flops.§  Onewaytospecifythemisusinggatedesign:

// A gated D latch module d_latch (D, Clk, Q); input D, Clk; output Q; wire R, S, Qa, Qb /* synthesis keep */ ; nand (R, D, Clk); nand (S, ~D, Clk); nand (Qa, R, Qb); nand (Qb, S, Qa); assign Q = Qa; endmodule

Page 29: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Othersimplificationsyntax§  Anotherwayofspecifyingthislatchis:

ú  “SetQtothevalueofDwheneverClkishigh.”   Thisisbasedontheconceptofpolling,wherethesoftwarekeepscheckingthevaluesofDandClktoseeiftheoutputQneedstobeupdated.

   Thebetterversionisbasedoninterrupts,wherethecircuitreactswhencertainsignalvalueschange…

ú  “WheneverDorClkchange,dothefollowing.”

always @ (D, Clk) begin ... end

Page 30: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Usingalways

§  Thealwayskeywordprovidesevenmoreabstractionthanbooleanequations,butintheend,everythingistranslatedintosimplegates.

§  Otherrelated high-level keywords:ú  if/else ú  for ú  case

Page 31: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Usingalways

§  Besttoshowalwaysthroughexamples.ú  Example#1:AnRSlatch.

   IfRandSare0and0,outputisunchanged.   IfRandSare1and0,QissethighandQissetlow.   IfRandSare0and1,QissetlowandQissethigh.   IfRandSare1and1,QandQarebothsetlow.

Page 32: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Alwaysexample:SRlatch module sr_latch(R, S, Clk, Q, Q_not); input R, S, Clk; output reg Q, Q_not; always @ (R, S, Clk) if (Clk & (R | S)) begin if (R & ~S) Q_not = 1; else Q_not = 0; if (S & ~R) Q = 1; else Q = 0; end endmodule

R Q

S Q

Page 33: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Usingif,else&elseif

§  Theifandelsekeywordsaremostusefulwithinanalwaysblock.ú  Usingthemoutsidethealwaysblockdoesn’twork.ú  Theif/elsestatementsaremeanttoturnsignalsonoroffinresponsetocertainconditions.ThealwaysstatementisneededtotelltheVerilogcompilerwhentotestforthoseconditions.

§  Theif,else ifandelsestatementscanbenested,justlikeanyotherlanguage.

Page 34: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

if/else,beginandend§  Justlikeinotherlanguages,

theifconditioncanbefollowedbyasinglestatement.

§  Ifyouwantthecircuittoperformmultiplestatementsinresponsetoacondition,usethebeginandendkeywords,likebracesinCorJava.ú  Note:Ifyouforgettousebegin

andend,thecompilerwillassumethatonlythenextlinebelongsintheifstatement.

if (S & ~R) Q = 1; else Q = 0;

if (S & ~R) begin Q = 1; Q_not = 0; end

Page 35: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

alwaysandinitial

§  Thealwayskeywordtellsthecompilertolistenforconditionsincertainsignals,andmakethecircuitrespondinthosecases.

§  Theinitialkeyworddoessomethingsimilar(makesthecircuitperformasetofoperations),butonlywhenthecircuitstarts.ú  Onlyoccursonce,atbeginning.ú  Usefulforinitiatingcircuitelements.

Page 36: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

forloops

§  Theinitialkeywordandforloopsgowelltogether,asaresult.ú  forloopsyntaxissimilartoCandJava:

reg [15:0] memory [255:0]; integer index; initial begin for(index = 0; index < 256; index = index + 1) begin memory [index] = 0; end end

Page 37: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

casestatements

§  Onemoreimportantcontrolstatement!§  ThecasestatementworkssimilarlytoitsPython,

CandJavacounterparts:

§  Goodforcreatingdecoders,orreactingtoinputsthatcouldhavemanypossiblevalues.

case (<variable name>) < case1 > : < statement > < case2 > : < statement > ... default : < statement > endcase

Page 38: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

caseexample:7-segdecoder

§  Easiertospecifydecodersliketheseven-segmentdecoderusingcasesyntax.ú  Resultisthe

sameastheversionobtainedthroughK-mapsandreduction.

module SevenSegmentDisplayDecoder(ss_out, bcd_in); output reg [6:0] ss_out; input [3:0] bcd_in; always @(bcd_in) case (bcd_in) 4'h0: ss_out = 7'b0111111; 4'h1: ss_out = 7'b0000110; 4'h2: ss_out = 7'b1011011; 4'h3: ss_out = 7'b1001111; 4'h4: ss_out = 7'b1100110; 4'h5: ss_out = 7'b1101101; 4'h6: ss_out = 7'b1111101; 4'h7: ss_out = 7'b0000111; 4'h8: ss_out = 7'b1111111; 4'h9: ss_out = 7'b1100111; 4'hA: ss_out = 7'b1110111; 4'hB: ss_out = 7'b1111100; 4'hC: ss_out = 7'b0111001; 4'hD: ss_out = 7'b1011110; 4'hE: ss_out = 7'b1111001; 4'hF: ss_out = 7'b1110001; default: ss_out = 7'b1111001; endcase endmodule

Page 39: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Reflectiontime

§  Remember:Thiscourseisaboutcircuits,notVerilogJ§  However…designingandtestingthesecircuitsis

easierwithtoolsorspecificationlanguages.ú  Designingcomplexcircuitsbywiringchipsandgates

togethercantakeforeverandbefullofbugs.ú  Designinggate-by-gateinVerilogisfaster,reproducible,

andyieldsfewerbugs.ú  Morepowerfulkeywordslikealways,if/elseandcase

createthesamelogicwithlesswork,bysimplyspecifyingthebehaviourthatyouwantinsteadofthespecificcircuit.   LikespecifyingstringanddictionarybehaviourinPythonorC,insteadofcreatingyourownobjectsfromscratch.

Page 40: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Reflectiontime

§  Takeamomenttothinkaboutthis!Peopleoftengetundulydistressedabouthigher-levelVerilogstatements.

§  Reallythough,these statementsmakelife aloteasier,onceyou getthehangofusing thesekeywordstosay whatthecircuit’s behaviourshouldbe.

Page 41: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Storingandassigningdata

§  Flip-flopsandsequentialcircuitsallowustodesigncircuitsthatcanstorevalues.ú  Someareimplicit,inlatch-stylefeedbackcircuits.ú  Otherscanbemadeexplicit,usingregvalues.

§  We’veusedregbefore, intheSRlatchexample.

Page 42: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Storingandassigningdata

§  Labelscanbegiventobothwireandregvalues.ú  Maindifference:regvaluescandriveoutput;wire valuescan’t.

module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule

A B

Y

module reg_example( a, b, y); input a, b; output y; reg y; wire a, b; always @ ( a or b) begin y = a & b; end endmodule

Page 43: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Regversuswire

§  “Drivingoutput”?Whatdoesthatmean?ú  RememberthatVerilogisusedtospecifyacircuitlayout.Thewirekeywordspecifieswhereanactualwirewouldbe,andconnectingtwopointswithawire(orwire)justmakesthemlogicallyequivalent.

ú  Areg(shortforregister)canactuallystoreavalueanddriveanoutputsignal.Anyalwaysorinitialblocksthatneedtosetavaluemustdosobysettingregvalues.   Similarly,wirescan’tbereassignedtoconnectnewpointstogetherpartwaythroughacircuit’soperation.

Page 44: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Literalvalues

§  Sometimesyouneedtoassignasetofwireorregvaluesatthesametime.ú  Example:theseven-segmentdisplay.ú  Possibletoassigneachsegmentoneatatime,buteasiertoassignthemallatonce.

§  LiteralvaluesinPythonandCarevalueslike42,3.14and“Hello”.

§  Veriloghasliteralvaluesaswell.ú  Butexactlywhatdoes101representinVerilog?

Page 45: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Literalvalues

§  101canrepresentdifferentvalues,dependingonwhattypeofnumberitis.ú  Decimal:101=onehundredandone(base10).ú  Binary:101base2=5base10ú  Hexadecimal:101base16=257base10ú  (Octal:101base8=65base10)

§  InVerilog:ú  Binary: ‘b101 ú  Decimal: ‘d101 ú  Hexadecimal: ‘h101

Page 46: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

Example:seven-segdecoder

§  Theinstructionsinthe seven-segdecoder codetranslatetothe following:ú  “inthecasewherethe four-bitBCDinputhasahexadecimalvalueof0…”

ú  “…setthevaluess_outtoa7-digitbinaryvalueof0111111.”

Page 47: The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · By Steve Engels So you want to learn Verilog Verilog is a new language that is used a lot in

References

§  VerilogLanguageReferenceGuide:ú  http://verilog.renerta.com/

§  VerilogPage:ú  http://www.asic-world.com/verilog/

§  VerilogTutorial:ú  http://www.fullchipdesign.com/verilog_tutorial.htm


Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog Tutorial - UCSBstrukov/ece154aFall2016/labs/verilog6.pdf · Verilog Tutorial Adapted from Krste Asanovic Verilog Fundamentals •History •Data types •Structural Verilog

The Verilog Primer - University of Torontobharrington/cscb58/labs/VerilogPrimer.pdf · The basics of Verilog § Verilog is based off the idea that the designer of the circuit needs

Introduction to Verilog - Oregon State Universityeecs.oregonstate.edu/research/vlsi/teaching/ECE472_FA12/verilog... · Introduction to Verilog ... More recently Verilog is used as

Verilog-XL Reference - DMCSfiona.dmcs.pl/~rkielbik/rul/verilog-xl reference.pdf · Verilog-XL Reference Product Version 3.1 ... Verilog Rules for Expression Bit Lengths ... UDP Syntax

Verilog Tutorial - Verilog HDL Tutorial with Examples

CSCB58 - Lab 0

Quartus Laboratory Exercise Manual for Introduction to Verilog · Laboratory Exercise Manual for Introduction to Verilog. ... Introduction to Verilog Lab Overview ... select Verilog

Verilog Fundamentals Verilog 1 - Fundamentalscsg.csail.mit.edu/.../handouts/lectures/L02-Verilog-Fundamentals.pdf3 6.375 Spring 2007 • L02 Verilog 1 - Fundamentals • 5 Designers

EE577b Verilog for Behavioral Modelingee577/tutorial/verilog/verilog_lec.pdf · EE577b Verilog for Behavioral Modeling Nestoras Tzartzanis 1 February 3, 1998 Verilog for Behavioral

Analog Verilog,Verilog-A Tutorial

Altera’s Introduction to Verilog - PLDWorld.com · Verilog Overview! Basic Structure of a Verilog Model! Components of a Verilog Module – Ports – Data Types – Assigning Values

Verilog – Sequential Logic - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog for synthesis - sequential logic rev... · Verilog – Sequential Logic Verilog for Synthesis

VERILOG - RWTH Aachen Universityhpac.cs.umu.se/teaching/sem-hpsc-14/presentations/Verilog slides.pdf · What is Verilog ? Verilog is a hardware description language(HDL) Verilog is

Verilog Synthesis - TWikiwiki.di.uminho.pt/.../08-VictorWinter-Verilog-Demo.pdfOverview of a Synthesis Problem Design and Implementation An Overview of Verilog Verilog is a hardware

Verilog Hardware Description Language (Verilog HDL)

Verilog hdl by samir palnitkar for verilog know how

Verilog Fundamentals · Verilog Fundamentals. VERILOG FUNDAMENTALS ... Verilog is a HARDWARE DESCRIPTION LANGUAGE. ... Level 2 : Design a digital system using Verilog . (weightage

A Verilog Primer - University of California, Berkeleyinst.eecs.berkeley.edu/.../verilog/Verilog_Primer_Slides.pdfA Verilog Primer An Overview of Verilog for Digital Design and Simulation

Vlsi Verilog _ Fir Filter Design Using Verilog

Verilog Foundation Express with Verilog HDL … reference...• Chapter 1, “Foundation Express with Verilog HDL,” discusses general concepts about Verilog and the Foundation Express

Lecture 4 Review - University of Torontobharrington/cscb58/slides/TUT04.pdf · Question #2 §Complete the truth table R Q S Q SRQ T Q T Q T+1 Q T+1 0001 0 1 0010 1 0 01XX 0 1 10XX

Week 2 Tutorial: The Verilog Primer - University of Torontobharrington/cscb58/slides/TUT02.pdf · The basics of Verilog §Verilogis based off the idea that the designer of the circuit

CSCB58 - Lab 0bharrington/cscb58/labs/lab0.pdf · CSCB58 - Lab 0 Intro to the Lab & The DE2 Board Learning Objectives This week we will be getting you familiar with the lab and the

05-Verilog Language Concepts - Amazon S3 · PDF file2 CSE 467 Verilog Digital System Design 3 Verilog Language Concepts Module Basics (cont.) Arrays Verilog operators Verilog data

Behavioral Modeling using Verilog-A Notes/VerilogA Modeling.pdf · Verilog-AMS Verilog-AMS is an extension of Verilog-A to include digital Verilog co-simulation functionality Works

Week 2 Tutorial: The Verilog Primer - University of Torontobharrington/cscb58/slides/... · 2019-05-15 · Week 2 Tutorial: The Verilog Primer. ... 2.Specify which of the module’s

Week 2: Circuit Creation - University of Torontobharrington/cscb58/slides/...Example truth table Consider the following example: ú“Given three inputs A, B, and C, make output Yhigh

High-level description of Verilog Verilog For Computer Designpages.cs.wisc.edu/~karu/courses/cs552/spring2017//handouts/verilog... · Verilog For Computer Design ... specific gates,

Verilog Tutorial - UCSBstrukov/ece154a/labs/verilog.pdf · Verilog Tutorial Adapted from Krste Asanovic. Verilog Fundamentals •History •Data types •Structural Verilog •Functional

Verilog-A Language Reference Manualecee.colorado.edu/~ecen5837/software/verilog-a-anguage_reference... · Verilog-A Language Reference Manual Analog Extensions to Verilog HDL Version

Verilog Language Reference - Georgetown Universitypeople.cs.georgetown.edu/.../docs/verilog/VerilogLangRef.pdfVerilog Language Reference Verilog Modeling Style Guide (CFE), Product

Verilog-A Manual - · PDF file3 Table of Contents Introduction 9 What Is Verilog-A? 9 Verilog-A Language Reference Manual 9 Using Verilog-A Compiler 10 Using Verilog-A with SIMetrix

Verilog Hardware Description Language (Verilog HDL) · PDF fileVerilog HDL 2 Edited by Chu Yu Verilog HDL Brief history of Verilog HDL 1985: Verilog language and related simulator

Bucknell Verilog Manual - user.engineering.uiowa.eduuser.engineering.uiowa.edu/~hpca/BucknellVerilogManual.pdf · Bucknell Verilog Manual Verilog HDL at the architectural or behavioral