The Tunnel Field-Effect TransistorDevin Verreck,1, 2, a) Anne S. Verhulst,1 and Guido Groeseneken1, 21)imec, Kapeldreef 75, 3001 Leuven, Belgium2)Department of Electrical Engineering, KU Leuven, 3001 Leuven, Belgium

I. INTRODUCTION

The tunnel field-effect transistor (TFET) is a semicon-ductor device aimed at low-power logic applications thatemploys band-to-band tunneling (BTBT) as a carrier in-jection mechanism to obtain a subthermionic subthresh-old swing (SS). In particular, it relies on the energeticfiltering of the tail of the electron Fermi-Dirac distribu-tion to go below the fundamental 60 mV/dec SS limit atroom temperature of a metal-oxide-semiconductor FET(MOSFET). The goal is to combine a low leakage cur-rent with a low SS to allow the TFET to be more energyefficient than a MOSFET.

Research in TFET has been driven by the fundamen-tal power issues encountered by MOSFET as device scal-ing continues along the path of Moore’s law. This law,in its most common formulation today, states that thenumber of electronic components per chip resulting ina minimum component cost, doubles approximately ev-ery two years1,2. Also, the rise of mobile applicationsand the Internet of Things, which contain a plethora ofalways-on sensor nodes, has increased the demand fordevices with low supply voltage (VDD) and low-leakageoperation3,4. The TFET aims to fulfill this demand byexploiting the quantum mechanical phenomenon of tun-neling. Although it is a leakage mechanism for MOS-FET in today’s scaled architectures, tunneling enablesthe TFET to go beyond the inherent ON-current (ION)- OFF-current (IOFF) trade-off that hampers the low-power performance of the MOSFET. Several challengesstill remain, however, before TFET can be implementedas a low-power replacement for MOSFET.

Several excellent overview works exist which summa-rize the TFET state-of-the-art or go into more detail onspecific TFET topics5–8. This article aims to give a broadoverview of the TFET field, with a distinct focus on de-vice physics and architecture options. For more details,the reader is invited to consult the references which areincluded in each section. The article is structured as fol-lows. First, the power issue of the MOSFET, which theTFET seeks to solve, is outlined in Section II. Next, thebasic operation of the TFET is explained in Section III,

a)devin.verreck@imec.beThis is the peer reviewed version of the following article: Verreck,D., Groeseneken, G. and Verhulst, A., The Tunnel Field-EffectTransistor, Wiley Encyclopedia of Electrical and ElectronicsEngineering, 1-24, 2016., which has been published in final form athttp://onlinelibrary.wiley.com/doi/10.1002/047134608X.W8333.This article may be used for non-commercial purposes in accor-dance with Wiley Terms and Conditions for Self-Archiving.

along with the two main types of tunneling in Section IV.This is followed by an overview of different approachesto model the TFET operation in Section V. The mainperformance challenges for TFET are then presented inSection VI. In Section VII, different material optionsfor TFET are considered. The subsequent sections aredevoted to various implementation options that are be-ing researched to improve the TFET performance, suchas dopant pockets (Section VIII), specific gate configura-tions (Section IX) and strain (Section X). Section XI dis-cusses attention points upon using the TFET in a circuit.Finally, Section XII gives a brief update on experimentalwork in literature. Section XIII concludes the article andprovides a future outlook.

II. MOSFET POWER ISSUE

The inherent trade-off between ION and IOFF for de-creasing VDD lies at the heart of the power density is-sue of MOSFET-based logic. This can be understoodby looking at the total dissipated power of a circuit ofMOSFET-based logic gates, which consists of a staticand a dynamic component9:

Ptot = Pstatic+Pdynamic = NgIOFFVDD+αCtotV2DDf (1)

with Ng the amount of gates, α the fraction of activegates, Ctot the total load capacitance of all gates and fthe switching frequency. Based on Eq. (1), a key elementin the so-called Dennard scaling of MOSFET, proposedin 197410, is the reduction of VDD as the physical tran-sistor dimensions are decreased with every new genera-tion in order to maintain a constant power density (notethat although Ctot decreases, the VDD reduction also re-sults in an increase of f). The threshold voltage (Vth) isdecreased accordingly to maintain sufficient ION, whichis proportional to (VDD - Vth)x. The Dennard scalingparadigm has enabled the continuation of Moore’s lawuntil the end of the 20th century. However, Dennardscaling eventually leads to an untenable increase in thestatic power component, as the OFF-state leakage is ex-ponentially dependent on Vth

5:

IOFF ∼ e−VthnkT/q (2)

where kT/q is the thermal voltage with k the Boltz-mann constant, T the temperature and q the elemen-tary charge, and where n is the body factor, equal to(

1 + Cd

Cox

)with Cd and Cox respectively the depletion

and oxide capacitance of a planar MOSFET. Aroundthe year 2002, the path of Dennard scaling was there-fore abandoned, with the scaling of VDD slowing down

2

with respect to the scaling of the physical transistor di-mensions. As a result, power density has been increasingas more and more transistors are included on a chip, witheach transistor consuming roughly the same power as theprevious generation. Notably, a significant portion of thispower is consumed in the OFF-state. The rising powerdensity leads to issues with cooling and reliability.

The origin of the exponential dependence in Eq. (2)is the Fermi-Dirac distribution of the charge carriers inthe source region. In the subthreshold regime, also calledweak inversion, a potential energy barrier in the MOS-FET channel region prevents low energy carriers in thesource from flowing to the drain contact. However, thehigh energy carriers in the exponential tail of the distri-bution can still diffuse over the barrier in a process calledthermionic emission. This leads to an exponential depen-dence of the drain-source current IDS on the gate-sourcevoltage VGS

11:

IDS ≈ ID0eVGS−VthnkT/q for VGS < Vth (3)

with ID0 the current at VGS = Vth.The inverse of the slope of Eq. (3) determines the

trade-off between ION and IOFF. It is called the sub-threshold swing (SS) and is used as a metric for theswitching steepness of the device. SS is defined as theincrease in VGS that is required to increase IDS with oneorder of magnitude5,10, and can be expressed as:

SS =VGS

log10IDS≈(

1 +CdCox

)kT

qln(10). (4)

At room temperature (T = 300 K), the SS of a MOSFETis therefore theoretically limited to about 60 mV/dec. Inactual implementations, non-idealities result in SS val-ues which can be significantly higher. Fig. 1 illustratesgraphically that the value of the SS determines the inter-section with the VGS = 0 V axis, which corresponds toIOFF. IOFF increases exponentially as Vth is decreasedand the curve shifts leftwards. As IOFF becomes unac-ceptably high, it prevents further concurrent scaling ofVDD and Vth and hence leads to aforementioned powerdensity issues in highly scaled technologies. The under-limit on the SS makes this a fundamental trade-off.

Several new transistor concepts have been proposed tobreak the ION-IOFF trade-off by having a SS lower thanthe MOSFET limit. Examples include concepts whichuse negative capacitance12, impact-ionization13 and me-chanical switches14. However, these concepts give rise tohysteretic behavior and typically require a high operatingvoltage (> 1 V) at one of the transistor contacts.

The TFET is a new transistor concept, compatiblewith CMOS technology, that has been proposed for beingcapable of having a SS lower than the MOSFET limit.This is possible because the TFET relies on quantummechanical BTBT instead of thermionic emission as thecarrier injection mechanism. The basic TFET structurewas first proposed in 1978 as a ’surface channel tunnel

50mV/dec

60mV/dec

IOFF

Vth

log(I D

S)

VGS (V)

FIG. 1. Schematic transfer characteristics of a MOSFET withan ideal SS and a steep slope device with a sub-60 mV/decSS, illustrating that the SS determines IOFF. Scaling of thethreshold voltage Vth increases the OFF-current IOFF expo-nentially.

junction’, aimed at investigating subband splitting andmany-body effects in quasi-2D systems15. However, itwas not until 1987 that BTBT was suggested as the work-ing principle of a transistor in a DRAM trench transistorcell16. Major research efforts started after 2004, whena carbon nanotube TFET was demonstrated with a sub-60 mV/dec SS at room temperature17 and the use of het-erostructures was conceptually introduced18. Since then,significant research efforts have been invested worldwidein improving the TFET performance by optimization ofthe device architecture and material system.

III. TFET BASICS

A. Basic structure and operating principle

The basic TFET structure is similar to that of a MOS-FET: it contains two contact regions and an intrinsic orlowly doped channel region, covered by a gate dielec-tric and a gate contact (see Fig. 2(a)). In contrast to aMOSFET, however, the TFET contact regions have anopposite doping polarity, resulting in a p-i-n profile. Inan nTFET, the p-type region acts as the source region,while in a pTFET, the n-type region acts as the source.Many variations on the basic configuration are possible,with different gate overlaps or doping profiles. Thesewill be discussed in Sections VIII to X. First, the work-ing principle will be explained for a basic p-i-n nTFET ina semiclassical picture. In this discussion, it is assumedthat the doping is such that the Fermi-level in the sourceis aligned with the valence band edge.

The TFET operates by enabling and preventing BTBTbetween the source and the channel region by modula-tion of the electrostatic potential in these regions with

3

-20 0 20 40 60 80

-1.5-1.0-0.50.00.51.0

ξn

VDS = 0.5V

qVDSEFnE

(eV)

x (nm)

EFp

Ec

Ev

VGS=0.7V

VGS=0.2VOFF

ON

DrainSource

Gate

p i n

(a)

(b)

(c)1.2-0.5

eV

0.5V

0.7V

0V

FIG. 2. (a) Basic p-i-n TFET configuration. (b) 2D electro-static profile of a p-i-n In0.53Ga0.47As TFET in the ON-state.(c) Energy band diagram along the cutline in (a) in the OFF(dark lines) and ON-state (light lines). The black arrows il-lustrate the shortening of the available tunnel paths. Thequasi-Fermi level for the holes in the source (EFp) coincideswith the valence band edge, while at the drain side, there isa degeneracy ξn.

the gate contact (see Figs. 2(b) and (c)). The sourceand drain contacts are biased such that the p-i-n diode isin reverse bias. In the OFF-state, the only current thatflows is the reverse leakage current of the p-i-n diode.This leakage current is typically caused by minority car-rier diffusion currents and by defect-assisted processes,such as Shockley-Read-Hall (SRH) generation and trap-assisted-tunneling (TAT) (see Section VI C). As VGS isincreased, the source is depleted and the electric field atthe tunnel junction rises. This corresponds to an increas-ing band bending at the source-channel junction. At agiven VGS, called the onset voltage (Vonset), the conduc-tion band in the channel crosses over with the valenceband in the source, such that tunneling transitions be-tween these two bands become available. These transi-tions can be direct, between the maximum of the valenceband and the minimum of the conduction band at the Γ-point, or indirect, between the maximum of the valenceband and the minimum of one of the conduction bandvalleys. In the indirect case, the transition is assistedby a phonon. The tunneling transitions, whether director indirect, form the current generating process of the

-0.5 0.0 0.5 1.010-12

10-10

10-8

10-6

10-4 VDS = 0.5V

60m

V/de

c

subthresholdI (A/

m)

VGS (V)

ambipolar

ON-state

Vonset

FIG. 3. Semiclassical (SC) simulated transfer characteris-tics of an In0.53Ga0.47As p-i-n TFET as shown in Fig. 2(a).The TFET body thickness is 20 nm with a source doping of5x1019cm−3 and an EOT of 0.6 nm.

-20 0 20 40

-1.0

-0.5

0.0

0.5

1.0

-20 0 20 40 -20 0 20 40(c)(b)(a)

Ev

EcE(eV

)

x (nm)

EFpp p

1x1020cm-35x1019cm-31x1019cm-3

VDS=0.5V, VGS=0.7V

Ev

Ec

x (nm)

EFp

fD fD

Ev

Ec

x (nm)

EFp

6nm

4nm

fD

FIG. 4. Energy band diagram of the p-i-n In0.53Ga0.47AsTFET of Fig. 2 with different degrees of source doping de-generacy ξp, ranging from (a) no degeneracy to (b) mediumdegeneracy to (c) high source degeneracy. As the source de-generacy increases, less of the exponential tail of the Fermi-Dirac distribution fD is filtered by the source bandgap. Forthe ease of extraction, a cross-section parallel to the gate hasbeen used.

TFET.

B. Transfer characteristics

Fig. 3 plots an example of typical TFET transfer char-acteristics, IDS as a function of VGS, showing the differentoperating regimes. The tunneling current rises as VGS

is increased above Vonset, since the length of the avail-able tunnel paths decreases and the electron tunnelingprobability is exponentially dependent on the tunnelingdistance. At VGS equal to VDD, the transistor is in theON-state, and IDS at this point is ION. The transition

4

from the OFF to the ON-state is, in analogy to the MOS-FET, called the subthreshold swing (SS), although thereis no fixed-swing subthreshold regime as in a MOSFET(see Section VI B), and hence also no Vth. The I-V curvein Fig. 3 shows a SS lower than the 60 mV/dec MOSFETlimit.

The low SS of the TFET originates from the energeticfiltering effect of BTBT carrier injection. Fig. 4(a) illus-trates how the bandgap of the source material cuts off asignificant part of the exponential tail of the Fermi-Diracdistribution. This band-pass filter action effectively coolsthe carrier distribution. The origin of the SS-limit in aMOSFET, which was discussed in Section II, is thus re-moved. The TFET is therefore able to obtain a SS lowerthan 60 mV/dec at room temperature. When the Fermi-level in the source is no longer aligned with the valenceband in the case of a highly doped source, the SS can bedegraded if the source degeneracy is too large. Figs. 4(b)and (c) show that a part of the exponential tail is then nolonger filtered. If this part of the tail results in observ-able current, it deteriorates the SS. On the other hand,Figs. 4(b) and (c) also show that a higher source dopingincreases the electric field at the tunnel junction, whichleads to a higher ION. This SS-ION trade-off, along withother parameters influencing SS, is discussed further inSection VI B.

The TFET is an ambipolar device, meaning that annTFET operates as a pTFET when a negative VGS isapplied. In this case, the depletion occurs in the n-typedrain region as the electric field rises at the channel-drainjunction. After cross-over of the valence band in thechannel with the conduction band in the drain, a holetunneling current is injected into the channel and thecurrent increases with decreasing VGS (see Fig. 3). Theambipolar behavior can be both an advantage and a dis-advantage, and will be further discussed in Section XI A.

C. Output characteristics

The source doping, drain doping and VDS deter-mine the energetic window available for tunneling (seeFig. 2(b)). VDS fixes the hole quasi-Fermi level EFp inthe source relative to the electron quasi-Fermi level inthe drain EFn. The total tunneling window, the ener-getic distance between the valence band in the sourceand the conduction band in the drain, is then the sumof (EFp-EFn) and any doping degeneracies in source ξpand drain ξn (see Fig. 4). For a constant VGS and start-ing at a VDS of 0 V, an increase in VDS enlarges thetunneling window and increases IDS (see Fig. 5). Theincrease of IDS with VDS continues until the conductionband edge in the drain falls below the conduction bandedge in the channel. Beyond this VDS, called VDS,SAT,IDS saturates, since an increase in VDS no longer has animpact on the tunneling window. Since the conductionband edge in the channel is determined by VGS, VDS,SAT

increases with increasing VGS, just like in a MOSFET.

0.0 0.5 1.0 1.5

1.6V1.7V

1.8V

1.9V

VGS= 2V1.4

1.2

0.8

0.4

I (A/

m)

VDS (V)

x10-8

0.0 1.5V

FIG. 5. SC simulated output characteristics of a Si p-i-nTFET as shown in Fig. 2(a) for varying VGS. The TFETbody thickness is 20 nm with a source doping of 5x1019cm−3

and an EOT of 0.6 nm.

Fig. 5 also shows that in contrast to the MOSFET,the onset of the TFET output characteristics can be su-perlinear. This occurs when the BTBT is inefficient forsmall VDS, e.g. as a result of a large tunnel path causedby a large effective oxide thickness (EOT), a low sourcedoping or as a result of very low carrier density availablefor BTBT19–21 (see also Section VI A). In the superlinearregime, the output current is small. This is unwanted,since it increases the settling time of a TFET inverter.Further circuit implications of this superlinear onset willbe discussed in Section XI D.

IV. POINT VERSUS LINE TUNNELING

After introducing the basic operating principle in theprevious section, a first major distinction in tunnelingtypes can now be made. Based on the alignment of theelectric field induced by the gate with the dominant tun-nel paths, two types of tunneling can be defined in aTFET: point tunneling (Section IV A) and line tunnel-ing (Section IV B), which can both be present in the samedevice (Section IV C).

A. Point tunneling

Point tunneling is the dominant type in a standard p-i-n/n-i-p TFET as depicted in Fig. 2(a) or Fig. 6(a), withthe gate predominantly covering the channel. This con-figuration is also called a pointTFET. The term ’pointtunneling’ originates from the assumption that the tun-nel paths curve around a central point at the interfacebetween gate metal and gate dielectric, right above thetunnel junction. In this approximate semiclassical view,the tunnel paths are assumed to lie on circles formed

5

by the electric field lines between source and gate, start-ing at the tunnel junction and ending at the interfacebetween gate-dielectric and channel20. Note that the cir-cular form of the field lines is based on the assumption ofinfinitely high source doping. At onset, only the longesttunnel paths are available, which then gradually shortenas VGS is increased toward the ON-state. In Fig. 2(a),these circular lines have been replaced with a straight lineindicating the shortest allowed tunnel path, with roughlysame start and end point as the circular lines.

The pointTFET performance is influenced by field-induced quantum confinement (FIQC), which is presentin the triangular well formed by the conduction bandedge in the channel and the dielectric barrier22 (seeFig. 7, although for a lineTFET, the shape of the wellis similar). In this well, subbands are formed. The on-set of BTBT is thereby shifted to a higher VGS, sincethe band edge determining the allowed tunnel path in-side the well is defined by the first subband level, whichis higher in energy than the bulk value of the band edge.As VGS is increased and the triangular well deepens, thefirst subband level shifts down at a slower pace than thebulk band edge. Hence, the tunneling window increasesmore slowly than it would in the absence of FIQC. Thishas a stretching effect on the transfer characteristics, andhence negatively impacts SS. The degree of this confine-ment is determined by the effective mass of the bandstructure valley to which the tunneling transition is tak-ing place and therefore depends on the material choice forthe channel. The impact of FIQC can be alleviated withthe introduction of a doping pocket at the source-channelinterface, which forces the tunnel paths more parallel tothe gate (see Section VIII A).

B. Line tunneling

Line tunneling can be induced with a large overlap ofthe gate over the source (see Fig. 6(b)). Such a configu-ration is also called a lineTFET. In contrast to point tun-neling, the tunnel paths are equally long parallel straightlines perpendicular to the gate dielectric in the ideal caseof no parasitic paths. For an increasing VGS, the energybands bend toward the gate dielectric until cross-overoccurs between the conduction band edge at the gatedielectric and the valence band edge in the bulk, suchthat BTBT becomes possible (see Fig. 7). In the ideal-ized case of a uniform field underneath the gate dielec-tric, implying that also the drain voltage impact on thesource region is completely neglected, the onset is moreabrupt than for point tunneling. All tunnel paths un-derneath the gate-source overlap become available at thesame amount of band bending, after which they shortenuniformly for increasing VGS. The tunneling is also lo-cated closer to the gate than in a pointTFET, while theelectric field is in line with the tunnel paths. This meansa smaller increase in VGS is required to achieve a givenamount of band bending. Additionally, in the ON-state,

S

Gate

p i

Gate

p iS

(a) (b)

FIG. 6. Source-channel region of a (a) point tunneling and (b)line tunneling TFET configuration. The arrows schematicallyindicate the tunneling paths.

the band bending is stronger, resulting in shorter tunnelpaths. Important to note is that ION is proportional tothe gate-source overlap.

The lineTFET’s performance is more heavily impactedby FIQC than the pointTFET, since the triangular wellunderneath the gate is more pronounced. The stretchingeffect due to the slower increase in the tunneling window,also seen in the pointTFET, can therefore have a nega-tive impact on the SS. Additionally, due to the strongFIQC, several distinct subband energy ladders can ap-pear in the well, since the degree of confinement dependson the effective masses of the different band structurevalleys. E.g. in a Si nTFET, those conduction band val-leys which have a heavy longitudinal effective mass in thedirection of confinement, are shifted in energy less thanthose for which the lower transverse mass determines theconfinement. This leads to two ladders of quantized en-ergy levels, as shown in Fig. 7(b). As a consequence, thetunneling currents to the different valleys see a relativeshift, which is visible in the transfer characteristics asa kink in the SS23. This relative shift also affects thepTFET, in which the light hole band is shifted more bythe confinement than the heavy hole band. Tunnelingbetween conduction band and heavy hole band is not asefficient as to the light hole band: because of symme-try reasons, there is no direct coupling, so any tunnel-ing transition must be assisted by a phonon. In the ab-sence of confinement, this inefficient tunneling current ismasked by the higher light hole-conduction band current.In the presence of FIQC, however, the relative shift re-sults in the heavy hole-conduction band current formingan undesired tail to the transfer characteristics24.

C. Point and line tunneling combined

Point and line tunneling current components can bepresent together in the same configuration. This is cer-tainly true if the gate overlaps both the source and thechannel region, but can also be induced by the fring-ing field of the gate, even if no gate-channel overlap ispresent. Because the line tunneling is more impacted byFIQC, Vonset for the point tunneling component is lower,meaning the gradual onset of the point tunneling candegrade the abrupt line tunneling onset. On the otherhand, however, a gate-channel overlap removes the po-tential barrier between the source and the ungated chan-nel, which can impede carriers from flowing to the drain

6

10 15 20-1.0

-0.5

0.0

0.5

1.0

1.5

10 15 20

2V

In0.53Ga0.47As (b)(a)

Ev

Ec

E (e

V)

z (nm)

EFp

1.5V

VDS=0.5V

1.7V

Si

Ev

Ec

z (nm)

EFp

VGS=1.2V

FIG. 7. Energy band diagrams of a lineTFET in the OFF(dark lines) and ON-state (light lines) along a vertical cutlinethrough the center of the gate in the [100] crystal direction.(a) An In0.53Ga0.47As configuration for a VGS of 1.2 V and1.7 V and (b) a Si configuration for a VGS of 1.5 V and 2 V.Indicated schematically in brown and red are estimations ofthe first three quantized energy levels for the highest VGS,corresponding to different valley effective masses inside thepotential well. The dashed line represents the quasi Fermilevel for the holes in the source (EFp).

and hence can decrease ION25. This introduces a trade-

off between SS and ION and makes the alignment of thegate to the source-channel junction an important poten-tial source for device variability in a lineTFET. However,the unwanted lateral tunneling component and the asso-ciated variability can be removed with the introductionof a counterdoped pocket, as discussed in Section VIII B.

V. MODELING

To acquire more physical insight into TFET operationand assess different architecture options, several mod-els have been established. Since tunneling is a quantummechanical phenomenon, all of these models rely on thesolution of some form of the Schrodinger equation. Evenso, the different solution approaches can be categorizedas either semiclassical (Section V A) or fully quantummechanical (Section V B). In semiclassical models, theSchrodinger equation is not solved directly. Rather, thetunneling probability is calculated based on the integralof a position dependent imaginary wave vector along awell-defined tunnel path. This implies the classical as-sumption that wave vector and position of the electronare known at the same time, violating the Heisenberguncertainty principle. In fully quantum mechanical ap-proaches, on the other hand, the electron is describedentirely by its wave function, which is obtained from asolution of the Schrodinger equation projected on a cho-

sen basis. Tunneling then arises as a consequence of thewave-like character of the electron. Here, the most com-mon examples of both approaches are discussed, withoutbeing exhaustive.

A. Semiclassical

A common semiclassical approach to the solution of thetime-independent Schrodinger equation is the Wentzel-Kramers-Brillouin (WKB) approximation. The reason-ing behind WKB starts from the one-electron wave func-tion ψ in zero electric field, which corresponds to a con-stant potential energy. Assuming the electric field to bezero in the tunneling direction x, and disregarding theother directions for now, ψ takes the form of a planewave26:

ψ(x) = Aexp (±ikxx) (5)

with i the imaginary number, x the tunneling direction,kx the wave number and A the amplitude. The plus(minus) sign corresponds to a right (left) moving wave.The approximation then lies in assuming that the wavefunction in the presence of a small and smoothly varyingnon-zero field, can be described by introducing a positiondependence for kx. It can be shown that the phase φ(x)of the wave function can be obtained from the integral ofkx(x) over the given domain26:

ψ(x) ≡ A(x)exp(iφ(x)) ≈ C√|kx(x)|

exp

(±i

∫kx(x)dx

)(6)

with C a real constant. In a forbidden energy region,like the bandgap, kx is imaginary (kx = iκx), which re-sults in an exponential decay of the wave function. Thiscorresponds to a tunneling process. By comparing theprobability density at each side of the tunneling barrier,an expression for the transmission probability can be de-rived. This expression typically ignores the prefactors ofthe exponentials and therefore solely consists of a con-tour integral of the imaginary kx along the tunnel paththrough the forbidden region:

TWKB = exp

(2

∫ x2

x1

κx(x)dx

)(7)

with x1 and x2 respectively the start and end pointof the tunnel path, also known as the classical turningpoints26–28. The tunnel path starts at the valence bandedge and ends at the conduction band edge for a particu-lar set of perpendicular wave numbers ky and kz. For zeroperpendicular momentum (ky = kz = 0 and κx = κx0),the application of Eq. (7) is illustrated in Fig. 8. Fornon-zero ky and kz, the effective tunnel gap increases,making transmission less probable. This effect can be

7

Ec

Ev

E

E

x

κx0x1 x2

κx0

(a) (b)

FIG. 8. (a) Real and imaginary 2-band k·p band structure ofbulk InAs for zero perpendicular momentum (ky = kz = 0).Indicated are the conduction (co) and light hole (lh) bands.(b) Energy band diagram, superimposed with the imaginaryband structure at a given energy E. The WKB transmissionprobability is calculated from an integral of this imaginarydispersion.

made explicit by rewriting Eq. (7) as:

TWKB(ky, kz) = exp

(2

∫ x2

x1

κx0(x)dx

)× exp

(−|k2

y + k2z |∫ x2

x1

dx

κx0(x)

)(8)

where the assumption has been made that k2y + k2z <<

k2tot28. It is now clear that the second exponential factor

of Eq. (8) reduces the transmission for non-zero perpen-dicular momentum27,28. In the case of direct BTBT, κx0can be extracted from the complex band structure of thematerial under study (see Fig. 8(a) and Fig. 9 for exam-ple band structures). Although the WKB method candescribe quantum phenomena like tunneling, it is stilla semiclassical approach, because Eq. (8) requires thatboth position and momentum (expressed by the wavevector) are known at the same time. This is possible in aclassical approach, but violates the quantum mechanicalHeisenberg uncertainty principle. From the WKB trans-mission probability in Eq. (7), the BTBT current can becalculated. This is discussed later in this section.

Another commonly used semiclassical model to cal-culate the transmission probability is Kane’s model29.Originally, the Kane formula for BTBT probability wasderived for a uniform electric field in a perturbative ap-proach, using Fermi’s golden rule and assuming a 2-bandk·p-model. An equivalent result can be obtained bystarting from the WKB method and assuming the electricfield F to be constant over the tunnel path length, whiletaking a two band k·p model to describe the complexwave vector dispersion. The transmission probability in

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$

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''

('

)&

*

+

,$-./

01,2

3

/

!

$"#

3$!

4

5! 5

6.,2

3

/

!"#$

*

)

FIG. 9. Real and imaginary 30-band k·p band structure ofbulk In0.53Ga0.47As. Indicated are the conduction (co), lighthole (lh), heavy hole (hh) and split-off (so) bands.

a direct bandgap material can then be written as:

TKane(ky, kz) = exp

(−πE

3/2G m

1/2R

2qhF

)exp

(−2

E⊥

E

)(9)

where EG is the effective bandgap at the tunnel junctionand mR is the reduced effective mass, defined as mR =memlh

me+mlh, with me and mlh the effective masses of respec-

tively the conduction band and the light hole band. Inthe second exponential factor, E⊥ = h2(k2y + k2z)/(2mR)

and E = 2qhF/(π(mR)1/2E

1/2G

). A factor π2

9 , present in

the original Kane derivation, was shown later to be incor-rect and has been removed30. Because of the assumptionof a constant electric field, the Kane model can deviatesignificantly from the WKB approach in cases where thefield is strongly non-uniform30,31.

From the transmission probabilities in Eq. (7) andEq. (9), the BTBT current can be calculated in two ways.The first is based on the ballistic Landauer formalismand entails a direct integration of the transmission prob-abilities, weighted with the distribution functions in thecontacts. This is called the Tsu-Esaki formula32, whichgives the BTBT current density as:

JDS =2q

h

∫kx,ky,kz

T (ky, kz)(fS(E)−fD(E))dkx2π

dky2π

dkz2π

(10)where T is the transmission probability and fS(E) andfD(E) are the Fermi-Dirac distributions in the source anddrain contacts respectively. The energy E is a function ofkx, ky and kz. Eq. (10) illustrates that the BTBT currentis determined by both the transmission probability andthe occupation probabilities at both sides of the tunneljunction.

A second way with stronger simplifications is to calcu-late the BTBT current is to determine a generation rate

8

per unit volume, which is then integrated over the full de-vice volume. In this approach, device simulators searchfor tunnel paths which connect points of sufficient poten-tial difference to allow for tunneling. Carriers are gener-ated by the BTBT process at the endpoints of the tun-nel paths. An expression for the generation rate can bederived from Eq. (10) by assuming the distribution func-tions for the carriers to be step functions, correspondingto a temperature of 0 K. This effectively decouples thecarrier distribution functions from the transition rates.For the Kane model, the following generation rate for-mula is commonly used:

GKane = A

(F

F0

)Dexp

(−B

F

)(11)

where F is the electric field, F0 is 1 V/cm, D is a param-eter that is taken 2 for direct bandgap materials and Aand B are parameters defined as:

Adirect =gm

1/2R (qF0)2

πh2(EG)1/2(12)

Bdirect =π2m

1/2R (EG)3/2

qh(13)

where g is a factor for the spin and valley degeneracies.Corrections that reintroduce the non-zero temperaturedistribution functions afterwards have been developed33.Extensions of Kane’s model have been made to describeindirect phonon-assisted transitions as well27. For indi-rect BTBT, D in Eq. (11) is 2.5 and A and B are modifiedto25:

Aindirect =g(mcmv)

3/2(1 + 2NPH)D2PH(qF0)5/2

221/4h5/2m5/4R ρεPHE

7/4G

(14)

Bindirect =27/2πm

1/2R E

3/2G

3qh(15)

where mv (mc) is the valence (conduction) band den-sity of states effective mass, NPH = 1/ [exp(εPH/kT)− 1],DPH and εPH are respectively the occupation number,the deformation potential and the energy of the relevantphonons and ρ is the mass density. To obtain the BTBTcurrent, the generation rate of Eq. (11) is integrated overthe device volume:

IDS = q

∫GdV (16)

with dV an elementary volume. The same approach canbe followed for the WKB approximation33.

The disadvantage of semiclassical methods is that theyneglect certain quantum phenomena which result fromthe wave-like character of the electron, since they do notdirectly solve the Schrodinger equation in the full de-vice region. Important examples for TFET include fieldor size-induced confinement effects, which can effectivelyincrease the bandgap, and resonances and reflections inregions of high field, which respectively increase or de-crease the transmission probability34,35.

B. Quantum mechanical

A fully quantum mechanical simulation approach en-tails the solution of the Schrodinger equation in someform. In TFET modeling, the most commonly used isthe time independent one-electron form:

Hψ(r) =

[−h2

2me∇2 + Ve(r) + Vc(r)

]ψ(r) = Eψ(r) (17)

with me the free electron mass, E the total energy,Ve(r) the external applied potential energy and Vc(r) thecrystal potential energy of the lattice. The solution ofEq. (17) generally occurs in two steps. First, the wavefunction is decomposed onto a reduced basis. This is be-cause the complicated nature of Vc(r) prevents the directsolution of Eq. (17) for ψ. The choice of basis corre-sponds to a particular band structure model. For TFET,the most commonly used models are the k·p-based enve-lope function method and the orbital-based tight-bindingmethod. Once the Hamiltonian has been written in thechosen basis, the second step is to construct a linear sys-tem or an eigenvalue problem, the solutions of which canbe used to extract desired quantities like currents andcarrier densities. The two main approaches for this stepare the wave function method and the non-equilibriumGreen’s function (NEGF) method.

A first band structure model is the envelope functionmethod, which expands the wave function on the solu-tions of the Schrodinger equation in bulk36:

ψ(r) =∑n

Fn(r)Un(r), (18)

where the Un(r) form a complete set of orthonormal ba-sis functions with the periodicity of the lattice and Fn(r)are slowly varying envelope functions, which contain onlyFourier components in the first Brillouin zone. The indexn runs over all bands considered in the description. In-serting the expansion of Eq. (18) into Eq. (17) and usingthe properties of the set Un(r), namely orthonormalityand completeness, the following system of equations re-sults (a detailed derivation can be found in the work ofBurt36 and Van de Put et al.34):

−h2

2me∇2Fn(r)− ih

me

∑m

pnm · ∇Fm(r) +∑m

Hnm(r)Fm(r)

+Ve(r)Fn(r) = EFn(r)(19)

where the external potential Ve is assumed to vary slowlyon the scale of a unit cell, like the envelope functions.The pnm are known bulk k·p interband momentum ma-trix elements. They describe the coupling strength, andhence BTBT, between bands n and m. Hnm are thebulk Hamiltonian matrix elements, which correspond toknown bulk band edge energies. The main advantage ofEq. (19), compared to Eq. (17) is therefore that the crys-tal potential Vc(r) has been replaced with known materialparameters.

9

An alternative band structure description, called thetight-binding method, consists of expanding the wavefunction on Bloch sums of localized atomic orbital-likefunctions, instead of on extended bulk solutions37–39:

ψ(r) = N−12

∑n

Cn∑i

exp(ik ·Ri)φn(r−Ri)

= N−12

∑n,i

Cn,iφn(r −Ri) (20)

where φn is a Lowdin orbital with quantum number n,located on the atom at position Ri. N is the num-ber of primitive unit cells in the crystal and serves asa normalization constant. Cn,i = Cnexp(ik · Ri) arethe expansion coefficients, which serve a similar pur-pose as the envelope functions Fn of Eq. (18). Insertingthe expansion of Eq. (20) into the Schrodinger equationEq. (17), multiplying from the left with the Bloch sum∑j exp(−ik ·Rj)φ

∗m(r−Rj) and integrating over the full

crystal, the following system of equations is obtained:∑i,j

Cn,i−j

∫φ∗m(r−Rj)Hφn(r−Ri)dr =

∑i,j

Cn,i−jE

(21)with Cn,i−j = Cn exp(ik · (Rj − Ri)). The integrals inEq. (21) can be replaced by parameters available in liter-ature, similar to the pnm elements in the envelope func-tion approach.

For both the envelope function method and the tight-binding method, the inclusion of more basis functionsresults in a more accurate band structure that can cap-ture a larger part of the first Brillouin zone. If enoughbands are included such that the full first Brillouin zoneis captured, the model is called a full-zone model. For theenvelope function method, this corresponds to a 30-bandbasis40,41, for the tight binding method to the sp3d5s∗

basis set42. With more basis functions, also the couplingbetween the different bands is captured more accurately(compare e.g. Fig. 8 with Fig. 9).

To solve Eq. (19) or Eq. (21) for an actual devicein which current enters and leaves through the sourceand drain contacts, open boundary conditions are re-quired. For TFET simulations, the quantum transmit-ting boundary method (QTBM) is often used43. QTBMimposes that the electric field is zero in the contacts inthe transport direction. The wave function is then knownto take the form of a plane wave in that direction. It isthis form which is imposed as a boundary condition onthe system.

With the appropriate boundary conditions, Eqs. (19)and (21) can be discretized and solved for the enve-lope functions and tight binding coefficients respectively.This direct solution approach is called the wave functionmethod. Available numerical techniques include finitedifference methods44, finite element methods45, spectralmethods46 and others. The envelope functions and thetight binding coefficients can be used to calculate im-portant device characteristics such as carrier densities,

transmission probabilities and currents. Similar to thesemiclassical case, the current can be calculated from thetransmission probabilities directly with Eq. (10), or moreapproximated by first converting to a generation rate andusing Eq. (16). To include the effect of the carrier con-centration on the potential energy profile, the calculatedcarrier densities can be used to calculate a new potentialenergy profile with the Poisson equation, which in itsturn can be used to calculate a new carrier density. Thisloop is then repeated until self-consistency is reached.

Instead of solving Eqs. (19) and (21) directly as inthe wave function method, an alternative is to calculatethe non-equilibrium Green’s function (NEGF)38,47. In anNEGF approach, Eq. (17) is rewritten as:

(EI − H − ΣS/D)G = I (22)

with G the Green’s function, H the Hamiltonian in thechosen basis and ΣS/D the self-energies of the source anddrain contacts. The self-energy terms are added to in-clude the open boundary conditions. Just like the wavefunction, G contains all relevant device information. Theadvantage of the NEGF approach is that other interac-tions can be included in a rather straightforward mannerby adding the corresponding self-energy term. E.g. forelectron-phonon interactions:

(EI − H − ΣS/D − Σel−ph)G = I (23)

with Σel−ph the self-energy for the electron-phononinteraction38. In this way, rethermalization, phonon-assisted tunneling and other scattering processes can bedescribed. To avoid having to calculate the inverse of alarge matrix (EI − H − ΣS/D − Σel−ph), methods havebeen developed that calculate only the relevant entries inthe Green’s function matrix, such as the contact block re-duction (CBR) method48 and the recursive Green’s func-tion (RGF) method38.

A separate quantum-mechanical framework based onwave functions has also been established for phonon-assisted tunneling23. It was shown that the current canbe determined from solving Eq. (19) for each band sep-arately. Two distinct sets of wave functions are thenobtained for the conduction band and the valence band.The transmission probability is calculated based on theoverlap of the wave functions of the two bands, combinedwith the interaction probability with a phonon of the ap-propriate momentum.

C. Semiclassical versus quantum mechanical

Compared to semiclassical approaches, quantum me-chanical models are typically computationally more ex-pensive, but include the effects of the wave-like nature ofthe electron, such as confinement and reflections in re-gions of high field or at a heterojunction. Quantum sim-ulations should therefore be preferred in cases where con-finement is expected to be strong, e.g. for TFETs with

10

0 1 2 310-9

10-7

10-5

10-3

0 1 2 3VGS(V)

(b)

SC QM

I (A/

m)

VGS(V)

(a)

VDS = 0.6V

FIG. 10. Transfer characteristics of a Si lineTFET simu-lated with a semiclassical (SC) approach based on the WKBmethod and a quantum mechanical (QM) approach based onwave function overlap. (a) Unshifted and (b) shifted char-acteristics such that the VGS at which IOFF is 1x10−9A/µmcoincides.

a body thickness below the Bohr radius of the material,or when the tunneling is oriented toward the quantumwell underneath the gate dielectric. Other cases includeTFETs with a heterojunction49 or configurations thatrely on resonant tunneling50.

To illustrate the differences that can exist be-tween semiclassical and quantum mechanical approaches,Fig. 10 compares the simulated transfer characteristics ofa Si lineTFET, whereby the last described quantum me-chanical approach for phonon-assisted tunneling is used.Since the tunneling is oriented towards the gate, a strongimpact of FIQC is expected. The effect of FIQC is visiblefor the quantum simulation as a shift in Vonset comparedto the semiclassical prediction and a kink due to differentsubband ladders (see also Section IV B).

VI. CHALLENGES

Having a basic understanding of TFET and methodsto model the tunneling current, the main challenges forTFET implementation are now discussed in more detail.Although the operating principle of the TFET is promis-ing for low power applications, several important chal-lenges remain. They can be summarized as reaching ahigh ION (Section VI A), combined with a low SS overseveral decades of current (Section VI B), while main-taining a low IOFF (Section VI C). These three devicecharacteristics are discussed with the appropriate metricsand the parameters which have an influence on them.

A. ION

The TFET ION is typically lower than that of a MOS-FET. This is due to the tunneling barrier, which allcharge carriers have to overcome before they can driftand diffuse toward the drain. This barrier is presenteven in the ON-state of the device. In contrast, in aMOSFET, the carriers with an energy higher than thesource-channel barrier can drift and diffuse from sourceto drain unimpeded. The lack of sufficient drive currentnegatively impacts the intrinsic delay of a TFET inverterconfiguration, expressed as:

τd =CoxVDD

ION(24)

From Eq. (24), it is clear that to keep the delay small inlow-VDD operation, ION should be sufficiently high. Inorder to compete with MOSFET, it is generally acceptedthat ION should be in the range of several hundreds ofµA/µm for VDD smaller than 0.5 V4.

To identify the parameters that increase ION, the Kanemodel can be used, although it is strictly speaking onlyvalid for uniform fields. The exponential factors inEqs. (11)-(15) show that the BTBT generation rate, andhence ION, is largest for a high electric field at the tunneljunction, a small bandgap and a small reduced effectivemass. A high F and small EG correspond physically toshort tunnel paths, while the low mR signifies a smallattenuation along the path, as it is correlated with theimaginary dispersion in the bandgap. A short tunnelpath and a small attenuation result in a high probabil-ity for the charge carriers to tunnel into the channel andcontribute to the current. A high F can be obtainedwith sharp doping profiles and a large doping level at thetunnel junction, by increasing the source doping and/orwith the introduction of a counterdoped pocket (see Sec-tion VIII). Additionally, F can be improved by enhanc-ing control of the gate over the tunnel junction, e.g. bythinning the device body, by adding gates to obtain amulti-gate (MuG) configuration or by modifying the de-vice structure to a line tunneling set-up (see Sections IVand IX). The small EG and reduced mR, on the otherhand, are the result of a proper material choice, withIII-V materials proving promising candidates, either ina homostructure (one material) or in a heterostructure(multiple materials) configuration (see Section VII).

B. SS

In addition to a high ION, a TFET should obtain a low,sub-60 mV/dec SS over a large current range of interest.The SS of a TFET at a specific VGS can be approximatedas:

SS =dVGS

dlog10IDS= ln(10)

[1

VR

dVR

dVGS+

F + B

F2

dF

dVGS

]−1(25)

11

TABLE I. Examples of recent experimental values for I60 inliterature, rounded to order of magnitude. Target value forI60 is 10 µA/µm or larger.

nTFET I60 [µA/µm] pTFET I60 [µA/µm]

Tomioka et al.53 10−3 Mayer et al.54 10−6

Dewey et al.55 10−3 Morita et al.56 10−5

Sarkar et al.57 10−4

Huang et al.58 <10−6

Kim et al.59 <10−6

which is derived from an approximation of the tunneljunction as a degenerately doped p-n junction with aconstant electric field51. VR is then the reverse biasof the tunnel junction (EFp-EFn) and B is the exponen-tial parameter of the Kane formalism (see Eq. (13) andEq. (15)). Comparing Eq. (25) to Eq. (4) shows that incontrast to the MOSFET, the SS of a TFET is indeednot limited by kT

q ln(10). However, Eq. (25) also shows

that the TFET SS is not constant with VGS. It is there-fore possible that the sub-60 mV/dec SS regime is onlylimited to very small levels of IDS. In this case, reducingthe supply voltage is still not feasible, as the majority ofthe SS is above the thermionic limit. The minimum valueof the SS as described in Eq. (25) at a particular VGS-point, also called the minimum point-SS, is therefore nota good metric to assess TFET performance. More rele-vant is to look at the average SS over the full operatingvoltage range, as shown in Fig. 11:

SSavg =VDD − VOFF

log(

ION

IOFF

) (26)

where VOFF is the VGS corresponding to the definedIOFF. SSavg still depends, however, on the choice of IOFF

and VDD, which can vary depending on the targeted ap-plication. Therefore, another metric called I60 has beenproposed52. I60 is defined as the point on the IDS-VGS

curve where the SS transitions from sub-60 mV/dec tosuper-60 mV/dec (also indicated in Fig. 11). Hence,it is the largest current for which the correspondingTFET outperforms a theoretically optimal MOSFET.I60 is independent of the choice of IOFF, VDD or thegate workfunction, so it can be used to compare vari-ous TFET configurations presented in literature. To becompetitive with MOSFET, I60 should be at least above10 µA/µm4,52. As an example, Table I lists some experi-mental values obtained in literature. See also Section XIIfor more experimental results. These examples show thatthere is still a large gap with the SS goal.

From Eqs. (25) and (26), it is clear that SS can be mini-mized by increasing dVR

dVGSand dFmax

dVGS, which represent the

gate control over the tunnel junction, and by increas-ing the ratio ION/IOFF. Physically, these requirementscorrespond to the capability of the gate to induce anabrupt transition from an OFF-state with a low tunnel-ing probability to an ON-state with a very high tunneling

0.0 0.510-12

10-10

10-8

10-6

10-4

VOFF VDD

SSavg

ION

IOFF

I (A/

m)

VGS (V)

I60

FIG. 11. SC simulated transfer characteristics of anIn0.53Ga0.47As p-i-n TFET as shown in Fig. 3, illustratingvarious metrics used to characterize TFET performance.

probability. This means the optimization of SS and ION

are intertwined, with one generally benefiting from theimprovement of the other. This is not true, however,for very high source doping levels. A large source dop-ing improves ION, but can degrade the SS if the sourcedegeneracy becomes too high, as was mentioned in Sec-tion III. For a given doping level, the source degeneracyis determined by the density of states (DOS) in the va-lence band (for an nTFET) or the conduction band (for apTFET) of the source material. A large DOS allows for ahigh source doping while keeping the source degeneracy,and hence the SS degradation, small. As the conductionband for most common bulk materials has a lower DOSthan the valence band, the pTFET has a more limitingtrade-off between ION and SS. This puts the pTFET atan inherent disadvantage compared to the nTFET. Thisimbalance can be alleviated using dopant pockets, dis-cussed in Section VIII.

The SS can be negatively impacted by parasitic currentmechanisms which occur in addition to the desired BTBTprocess, such as trap-assisted tunneling (TAT)60–62. TATis a process in which trap levels in the bandgap are usedby the charge carriers as stepping stones between con-duction and valence band (see Fig. 12(a)). These lev-els are localized energy states resulting from defects inthe material, such as vacancies, impurities and danglingbonds in the bulk or at interfaces. The TAT transitionitself consists of at least one ballistic tunneling step and aphonon-assisted thermal step to and from the trap level.This means TAT has both a field and a temperature de-pendence. TAT degrades the SS, as it can turn on atlower VGS and add a thermal tail to the transfer charac-teristics. The impact of TAT can be reduced by improv-ing the material quality, such that the trap density is low,or by enhancing the desired BTBT current, such that itbetter masks the current component caused by TAT. Theamount of TAT present in the transfer characteristics can

12

be characterized by VTAT@IOFF, the increase in Vonset at300 K at the specified IOFF compared to the Vonset valueat 77 K63.

C. IOFF

To obtain a low leakage power, IOFF should be suffi-ciently small. IOFF is composed of the reverse leakagecurrent of a p-i-n diode, consisting mainly of SRH pro-cesses, minority carrier diffusion, and possibly some TATif the other two mechanisms are sufficiently small. Addi-tionally, parasitic TFET mechanisms such as ambipolarcurrent and direct source-drain tunneling can increaseIOFF. For low-power applications, the ITRS roadmapsets the target for IOFF at 10 pA/µm, with ION

IOFF> 105.

SRH, similar to TAT, is a trap-assisted process inwhich carriers are generated via localized trap levelsthrough phonon-assisted thermal steps when the electronand hole densities are out of equilibrium (see Fig. 12(b)).In contrast to TAT, SRH has a weak field dependenceand so does not impact the SS. However, if the trap den-sity is sufficiently high, it can increase IOFF. Similar toTAT, the remedy is to decrease the trap density.

The ambipolar current is determined by the efficiencyof BTBT at the channel-drain junction. This means itcan be reduced by taking opposite measures as those sug-gested in Section VI A to increase ION, viz. a reductionof F and EG and an increase in mR at the channel-draintunnel junction. F can be reduced by lowering the draindoping, at the expense of increasing the resistance. EGand mR depend on the material choice and cannot bevaried independently from the source in a homostruc-ture, but they can be in a heterostructure (see SectionVII C). Another option is to introduce a gate-drain un-derlap region, which decreases the influence of the gateon the channel-drain junction64 (see Section IX B). Usinga combination of these techniques, the ambipolar currentcan be kept to acceptable levels.

Direct source-drain tunneling occurs when charge car-riers can tunnel from source to drain, even when the de-vice is in the OFF-state. This occurs when the tunnelpaths in the OFF-state are too short or provide insuffi-cient attenuation to suppress the carrier tunneling proba-bility. Direct tunneling is particularly important in mate-rials with a small EG and mR and in configurations witha short channel. In vertical architectures, increasing thechannel length is a straightforward way to reduce thesource-drain tunneling. In planar configurations, how-ever, a longer channel length also increases the devicefootprint.

VII. MATERIAL CHOICE

To overcome the challenges outlined in the previoussection, different material options are being consideredfor TFET. Of particular interest are materials from group

-20 0 20 40 60 80-1.0

-0.5

0.0

0.5

1.0

(b)

Etrap

EFn

E (e

V)

x (nm)

EFp

0

Etrap

(a)

Ev

Ec

FIG. 12. Energy band diagrams of the tunnel junction ofan In0.53Ga0.47As TFET showing (a) TAT and (b) SRH pro-cesses, which contribute to the TFET IOFF. The green linesrepresent localized trap energy levels, the red wavy lines arethermal steps and the black solid line corresponds to a tun-neling step.

IV (Section VII A) and compounds from group III and Vof the periodic system of elements (Section VII B). Multi-ple of these materials can be combined in a heterostruc-ture (Section VII C). 2D materials are a new class ofmaterials, which is also gaining interest for TFET appli-cations (Section VII D).

A. Group IV materials

Silicon is the most prevalent material in today’s MOS-FETs for logic applications, and has therefore also beenextensively studied for TFET. Si has the distinct advan-tage of being a well-known, abundant material that canbe obtained with a very low density of defects in the bulkof the material as well as at the gate dielectric interface.Established fabrication infrastructure and processes ex-ist in industry for a wide variety of process steps. Thisincludes high quality oxide growth and high concentra-tion doping. Si is also interesting for TFET because ofits large conduction band DOS, which limits the sourcedoping degeneracy in pTFETs (the importance of whichis discussed in Section VI B).

However, Si is a relatively poor material for BTBTand consequently, Si TFETs typically have a small ION.A first cause is the relatively large EG of 1.12 eV, whichresults in a low tunneling probability (see Section VI A).Although beneficial for IOFF, the low tunneling rate isdetrimental for ION. Secondly, Si is an indirect bandgapmaterial, which reduces the overall efficiency of BTBT.The smallest EG is measured between the valence bandmaximum at the Γ-point and the conduction band val-ley minimum along the ∆-direction40. These two pointsin the E-k diagram are not at the same k-value, whichmeans they correspond to a different crystal momentumhk. A tunneling transition between these two points re-quires a phonon to provide the necessary crystal momen-

13

tum. This makes it less probable for a given energeticseparation than a direct transition, in which the startand end points of the tunneling process are at the samek-value, therefore requiring no phonon. In Si, the indi-rect transitions are dominant, since the bandgap at theΓ-point is much larger at 3.4 eV, making direct transi-tions very improbable25.

As an alternative to Si in group IV of the periodicsystem of elements, Ge is more suited for BTBT. It hasa smaller indirect bandgap than Si of 0.66 eV. Unlike Si,the direct bandgap at the Γ-point is only slightly larger at0.8 eV. Consequently, once the band bending is such thatdirect transitions are allowed, they will dominate over theindirect transitions and improve ION

25,65. However, asdiscussed in Section VI C, a smaller bandgap facilitatesambipolar tunneling at the channel-drain junction, whichis an important leakage mechanism in TFET. IOFF willtherefore generally be larger than for Si implementations,but it is expected that acceptable levels of IOFF can bereached.

Since it belongs to the same group as Si, Ge can alsobe used in an alloy with Si, forming SixGe1−x, with xthe Si mole fraction. x determines the band structure,including the bandgap and the relative importance of theindirect and direct processes. A rather abrupt transitionoccurs from Ge-like to Si-like behavior above x=0.225.The control over the band structure through x can beused to find a compromise between improving ION, andreducing IOFF.

B. Group III-V materials

Beyond group IV, a host of materials suited for TFETcan be found in the group of III-V materials, which arecompounds of elements from group III and group V.They are actively researched as future channel materi-als for MOSFET, because they can exhibit high elec-tron mobilities compared to Si66. III-V materials show awide variety of band structures, with bandgaps varyingfrom 0.17 eV for InSb up to 3.28 eV for GaN67. Thesame variety can be found in the effective masses. Thepossibility of a small bandgap and small effective mass,combined with the direct nature of most III-V materi-als, makes them interesting candidates for improving theTFET ION. Important examples which have been studiedfor TFET applications are binary compounds like InAs,GaSb, InP and ternary compounds like InxGa1−xAs andGaAsxSb1−x

7.Nevertheless, III-V materials also present significant

challenges. Firstly, they are much less known than Si,so it is challenging to obtain high-quality materials andgate dielectrics with a low defect density66. Secondly,the material properties that allow for a high ION alsoraise IOFF undesirably. A small bandgap combined witha low effective mass facilitates both ambipolar and di-rect source-drain tunneling. This issue can be alleviatedwith the use of a heterostructure as discussed in Sec-

Ec1

Ev1

Ec2

Ev2

Staggered

Ec1

Ev1Ec2

Ev2

Broken

Ec1

Ev1

Ec2

Ev2

Straddled

FIG. 13. Types of band edge alignments at a heterostructuretunnel junction. In a straddled alignment, Ec1 > Ec2 and Ev1

< Ev2. In a staggered alignment, Ec1 > Ec2 and Ev1 > Ev2.In a broken alignment, Ev1 > Ec2. The green arrows indicatethe effective bandgap at the tunnel junction. For the brokenconfiguration, the effective bandgap is negative.

tion VII C. Thirdly, a low electron effective mass meansa low DOS in the conduction band compared to Si. Thisexacerbates the ION-SS trade-off for pTFET for increas-ing source doping, discussed in Section VI B. Solutionsexist in the form of dopant pockets, as discussed in Sec-tion VIII.

C. Heterostructures

The material options discussed so far assume that theactive region of the device consists of only one material.For such a configuration, an important issue in the ma-terial choice is the link between ION and IOFF, with thedesired improvement of the former also inducing an un-wanted increase in the latter. A way to decouple the twois to combine two materials in a heterostructure, suchthat the material in the source is different from the ma-terial in the channel and the drain.

A heterostructure configuration has an extra degree offreedom: the band edge alignment at the tunnel junction.The alignment is determined to a first approximation bythe electron affinity of the two constituent materials, andis classified as straddled, staggered or broken, as shownin Fig. 13. The effective bandgap which determines thetunnel path lengths at the tunnel junction is determinedby the alignment and not by the bandgaps of the individ-ual materials. A hetero-TFET can therefore combine avery small effective bandgap at the source-channel junc-tion, enabling a high ION, with a large bandgap at thechannel-drain junction, maintaining a low IOFF. Fig. 14illustrates the performance improvement for a staggeredheterojunction compared to a homojunction. The mate-rial of the source can also be chosen to have a large DOS,associated with a large bandgap, to limit the source dop-ing degeneracy. This can be done without increasing theeffective bandgap at the tunnel junction, so long as theband alignment remains favorable68.

In the special case of a broken band alignment, thereis no forbidden region through which the carrier has totunnel. This enables a high transmission probability andis hence beneficial for ION. It is still unclear, however,

14

0.6 0.910-11

10-9

10-7

10-5

10-3

0.6 0.9

VDS = 0.3V

VGS(V)

(b)

Homo Hetero

I (A/

m)

VGS(V)

(a)

60m

V/de

c

60m

V/de

c

FIG. 14. QM simulated transfer characteristics for aIn0.53Ga0.47As (bandgap of 0.73 eV) homostructure TFETand a GaAs0.5Sb0.5/In0.53Ga0.47As heterostructure TFET.The heterostructure is lattice matched and has a staggeredband alignment with an effective bandgap of 0.29 eV. TheTFET is a double gate configuration with an EOT of 0.6 nm,a body thickness of 10 nm and a source doping of 5x1019cm−3.(a) Unshifted and (b) shifted characteristics such that the VGS

at which IOFF is 1x10−11A/µm coincides. This shift can beaccomplished by a proper choice of gate workfunction.

whether a broken gap alignment will allow for a suffi-ciently low IOFF, since phonon-assisted leakage paths ex-ist in the OFF-state69,70. This is indicated in Fig. 15:after transitioning from source to channel, a rethermal-ization step can enable the electron to pass over the po-tential barrier in the channel, resulting in an increasedIOFF. The importance of this leakage current is influ-enced by the quantization in the triangular wells at thejunction and the interaction strength with the availablephonons.

Depending on the choice of materials, heterostructurescan be either lattice-matched or lattice-mismatched.In the first case, both materials have the same lat-tice constant. The materials can be grown epitax-ially without any stress at the heterojunction. No-table examples include In0.53Ga0.47As/InP (straddled)and GaAs0.5Sb0.5/In0.53Ga0.47As (staggered). In the sec-ond case, the mismatch of lattice constants results in anon-uniform stress profile arond the tunnel junction, asin the case of GaSb/InAs (broken). The stress has animpact on the local band structure (see Section X). Thebuild-up of stress can also result in interfacial defects atthe junction if relaxation sets in71.

D. 2D materials

2D materials are an alternative to the bulk semi-conductors described in the previous sections, andare being investigated for both MOSFET and TFETapplications72. 2D materials are atomically thin, en-

0 20 40

0.0

0.5

-0.5V

VGS= -1V

EFnE (e

V)

x (nm)

EFp

Ev

Ec

FIG. 15. Energy band diagram at the tunnel junction of aGaSb/InAs heterostructure TFET with a broken band align-ment in the OFF (dark lines) and ON-state (light lines). VGS

is -1 V and -0.5 V respectively. Indicated is a leakage path inthe OFF-state. The red wavy line represents a thermal step.The dashed line represents the quasi Fermi level for the holesin the source (EFp). The source doping is 5x1019cm−3.

abling excellent gate control. In addition, it is expectedthat low defect densities can be obtained with no dan-gling bonds or roughness at the surface.

The most studied 2D-material is graphene, but since itis a semi-metal, it does not have a bandgap and is there-fore not suited for TFET as such. However, a bandgapcan be introduced by symmetry-breaking operations suchas patterning the graphene into nanoribbons, or by stack-ing two layers and applying an electric field73. This al-lows the bandgap to be tuned, either by controlling thesize of the ribbon or the strength of the electric field.

Transition metal dichalcogenides (TMD) form an al-ternative to graphene in 2D TFET applications. TMDsare a class of 2D materials with chemical formula MX2,with M a transition metal and X a chalcogenide. In con-trast to graphene, TMDs do exhibit a variety of relativelylarge bandgaps. They can be used as the channel mate-rial of an atomically thin TFET74–76 (see Fig. 16(a)), orlayers of different TMDs can be stacked as a heterostruc-ture, bonded by Van der Waals interactions. Tunnelingthen occurs in the overlap region of the layers, perpen-dicular to the gate (see Fig. 16(b)). Such 2D heterostruc-ture TFETs are predicted to combine high ION and lowIOFF in the same way as bulk heterostructures77. TMDscan also be combined with a bulk semiconductor, suchas MoS2 on Ge57 (see Fig. 16(c)). Challenges that re-main for 2D materials are the development of large areadefect-free production, good ohmic contacts and tech-niques to obtain high doping levels72,78. As a result ofthese challenges, only few experimental 2D TFETs withsub-60 mV/dec SS have been realized (see Fig. 30).

15

Bottom gate

Top gate

SourceDrainTMD1

TMD2

Bottom gate

Top gate

Source DrainTMD

(a)

(b)

Gate

Source

DrainTMD

(c)

Bulk

FIG. 16. TMD TFET configurations. (a) homojunction TMDTFET74–76, (b) 2D heterojunction TMD TFET, also calleda Thin-TFET77 and (c) 3D-2D heterojunction bilayer TMDTFET, also called ATLAS-TFET57. The arrows indicate thedirection of the tunneling paths.

VIII. DOPANT POCKETS

To improve SS and/or ION, another design option is touse dopant pockets. A dopant pocket is a localized regionof doping, which locally modifies the device electrostat-ics. In a TFET, they can be used both in point tunneling(Section VIII A) and line tunneling (Section VIII B) con-figurations.

A. Pocketed pointTFET

In a pocketed pointTFET, a counterdoped pocket isadded at the interface between source and channel toimprove both ION and SS (see Fig. 17(a)). This forms a p-n-i-n doping profile in an nTFET, and a n-p-i-p profile fora pTFET. Compared to a p-i junction, the built-in fieldat a p-n junction is larger, corresponding to a strongerbuilt-in band bending and hence an onset at lower VGS

and the potential for a higher ION79–82. As shown in the

band diagrams of Fig. 18, for a properly designed pocket,the enhanced band bending induces an abrupt transitionfrom long to very short tunnel paths at tunneling onset,compared to more gradual shortening seen in a standardp-i-n/n-i-p configuration. In the transfer characteristicsthis results in an improvement of SS, as shown in Fig. 19.

An additional effect of the pocket is that it reduces theimpact of FIQC on the pointTFET performance. Thestrong built-in electric field at the tunnel junction forcesthe tunnel paths in a direction more parallel to the gateand induces tunneling before a strong band bending to-wards the gate, causing FIQC, is induced. The result is a

S

Gate

p i

(a) (b) Gate

p iS

n

n

Tpo

Tpo

FIG. 17. Source-channel region of a pocketed (a) point tun-neling and (b) line tunneling TFET configuration.

shift of the BTBT onset to lower VGS and a reduction ofthe stretching effect on the SS, discussed in Section IV A.

An optimum exists for the pocket thickness (Tpo, seeFig. 17(a)). The strength of the built-in field, and conse-quently the improvement in ION, increases with Tpo (seeFig. 20(a)). However, if the pocket is so thick that theconcentration of free carriers in the pocket becomes large(close to the doping level in the source) and is larger thanthe concentration in the channel at the onset of tunneling,the abrupt onset is deteriorated by a potential barrier inthe channel82 (see Fig. 20(b)). At the first moment ofcross-over between valence and conduction band, a dipis present in the energy bands at the tunnel junction,followed by a bump in the channel. For such a config-uration, a further increase in VGS only marginally goestoward increasing the band bending at the tunnel junc-tion, but is consumed largely by a further increase of thecarrier concentration in the pocket. The structure is theneffectively a p-n diode in series with an n-i-n MOSFET. Agood estimate for the optimal Tpo is the depletion widthat the tunnel junction79,82. Note that for configurationswith a large body thickness, a thick pocket can cause anuncontrolled tunneling current through the body of thedevice.

A pocket can also be used to mitigate the deteriorat-ing effects of a large source doping degeneracy on the SS.The doping in the source is kept low, except for a pocketat the source side of the source-channel junction. Thispocket retains the built-in electric field, while the lowerdoping in the rest of the source reduces the degeneracy83.SS is consequently improved, while ION is maintained.The source pocket can be combined with a counterdopedpocket at the channel side, resulting in a p−p+n+in con-figuration. This approach is particularly useful for III-VpTFET in which the source consists of a material with alow conduction band DOS, as discussed in Section VI B.

B. Pocketed lineTFET

In a pocketed lineTFET, a pocket is introduced to mit-igate the impact of FIQC and to reduce the sensitiv-ity to the gate-channel overlap (see Section IV B). Thepocket is located in the source region, underneath thegate-source overlap and adjacent to the source-channeljunction (see Fig. 17(b)). Similar to the pocketed pointTFET, the doping type of the pocket is opposite to that

16

-20 0 20 40

-1.0

-0.5

0.0

0.5

1.0

-20 0 20 40

VDS=0.5V

(b)(a)

Ev

Ec

E (e

V)

x (nm)

EFp

No pocket Pocket

Ev

Ec

x (nm)

EFp0.8V

VGS=0.3V

0.8V

0.3V

FIG. 18. Energy band diagrams of a In0.53Ga0.47As TFETin the OFF (dark lines) and ON-state (light lines). VGS isrespectively 0.3 V and 0.8 V. (a) A no-pocket configurationand (b) a configuration with a 4 nm thick pocket at the source-channel junction as in Fig. 17(a). The source and pocketdoping is 5x1019cm−3. The EOT is 0.6 nm, with a bodythickness of 20 nm. The dashed line represents the quasiFermi level for the holes in the source (EFp).

0.6 0.910-11

10-9

10-7

10-5

10-3

0.6 0.9

VDS = 0.3V

VGS(V)

(b)

Homo Hetero Homo pocket Hetero pocket

I (A/

m)

VGS(V)

(a)

60m

V/de

c

60m

V/de

c

FIG. 19. QM simulated transfer characteristics of Fig. 14compared to the transfer characteristics of the same config-urations with a counterdoped pocket of 3 nm. The TFETis a double gate configuration with an EOT of 0.6 nm, abody thickness of 10 nm and a source and pocket dopingof 5x1019cm−3. (a) Unshifted and (b) shifted characteristicssuch that the VGS at which IOFF is 1x10−11A/µm coincides.This shift can be accomplished by a proper choice of gateworkfunction.

of the source.The effect on the FIQC underneath the gate dielectric

is shown by the energy bands of Fig. 21: the triangu-lar well is rounded off and becomes wider for increasingTpo. The rounding reduces the FIQC, such that the sub-band quantization levels decrease in energy. The onset ofvertical BTBT, determined by the first quantized level,

-20 0 20 40-1.0

-0.5

0.0

0.5

1.0

-20 0 20 40

VDS=0.5V

Tpo=6nm

4nm

Tpo

(b)(a)

Ev

Ec

E (e

V)

x (nm)

EFp

0.3V0.5V

VGS=0.5V

Ev

Ec

x (nm)

EFp

FIG. 20. Energy band diagrams of an In0.53Ga0.47As TFETaround onset of BTBT. The source and pocket doping is5x1019cm−3. The EOT is 0.6 nm, with a body thickness of20 nm. (a) Impact of increasing Tpo (0 nm, 2 nm and 4 nm)for a constant VGS of 0.5 V, showing an increasing electricfield at the tunnel junction. (b) Comparison of an optimalTpo of 4 nm to a larger Tpo of 6 nm at onset, with the lattershowing a potential bump in the channel. VGS is respectively0.5 V and 0.3 V. The dashed line represents the quasi Fermilevel for the holes in the source (EFp).

10 15 20-1.0

-0.5

0.0

0.5

1.0

10 15 20No pocket Pocket

VDS=0.5V

VGS=1.4V

0.9V

(b)(a)

Ev

Ec

E(eV

)

z (nm)

EFp

0V

0.5V

Ev

Ec

z (nm)

EFp

FIG. 21. Energy band diagrams of a In0.53Ga0.47As lineTFETin the OFF (dark lines) and ON-state (light lines) along avertical cutline through the center of the gate. The sourceand pocket doping is 5x1019cm−3. The EOT is 0.6 nm, witha body thickness of 20 nm. (a) A no-pocket configuration fora VGS of 0.9 V and 1.4 V and (b) a configuration with a 4 nmthick pocket underneath the gate as in Fig. 17(b) for a VGS

of 0 V and 0.5 V. Indicated in brown are estimations of thefirst three quantized energy levels inside the potential well forthe highest VGS. The dashed line represents the quasi Fermilevel for the holes in the source (EFp).

17

therefore shifts to a lower VGS. The resulting onset volt-age Vonset can be calculated analytically as84:

V onset =WF − χe + Esub

q− q(Npo +Ns)Tpo

Cox+

1

Cox...

×

√2qεsNs

[Eg + Esub

q+q(Npo + 2Ns)T 2

po

2εs

]− q2N2

s T2po

(27)

provided the pocket is fully depleted, with WF the workfunction of the gate, χe the semiconductor electron affin-ity, Npo and Ns respectively the doping level of the pocketand the source and Esub the energy level of the first sub-band in the potential well underneath the gate, whichcan be solved from a 1D Schrodinger equation. Eq. (27)shows that by adjusting the thickness and doping of thepocket for a given WF of the gate, the FIQC-inducedshift in Vonset seen in the no-pocket case can be re-moved. Note that for materials which are more proneto FIQC, i.e. those with a small effective mass and hencea large Esub, the required Tpo or Npo to compensate forthe FIQC shift are larger.

In materials like Si, which have two distinct subbandladders in the well underneath the gate, the decreasedFIQC has the added benefit of reducing the relative shiftbetween the subband levels. The corresponding kink inthe SS which was discussed in Section IV B is therebyalso reduced, as shown in Fig. 22, where two pocketedlineTFETs are compared to a pocketed pointTFET con-figuration. For a thicker pocket, Vonset is reduced, whilethe relative shift of the two current components is de-creased. The kink is not present in a III-V configura-tion with an isotropic conduction band effective mass, asshown in Fig. 23.

The presence of the counterdoped pocket also re-duces the unwanted lateral point tunneling componentby blocking the shortest lateral tunneling paths closest tothe gate, since the source-channel p-i junction is locallyreplaced by a n-i junction. Combined with the earlieronset of vertical BTBT, the overall impact of the lateralcomponent on the transfer characteristics is thus dimin-ished, removing also the variability to the gate alignment.

The comparison of transfer characteristics in Fig. 22and Fig. 23 shows that although the pocketed lineT-FET outperforms the pocketed pointTFET in a Si con-figuration in terms of ION and SS, the difference be-comes smaller for materials with a smaller bandgap, likeIn0.53Ga0.47As82,85.

IX. GATE STACK CONFIGURATION

As discussed in Section VI, the gate control is an essen-tial factor in the BTBT efficiency. Gate control is char-acterized by two aspects. The first aspect is the portionof the gate voltage observable in the semiconductor, afterthe voltage drop over the oxide. This is directly related to

0.0 0.810-11

10-9

10-7

0.0 0.8

VDS = 0.5V

VGS(V)

(b)

Line 3nm Line 2nm Point

I (A/

m)

VGS(V)

(a)

60m

V/de

c

60m

V/de

c

FIG. 22. QM simulated transfer characteristics of a Si pock-eted pointTFET with a Tpo of 4 nm and pocketed lineTFETwith two different Tpo. The TFETs are double gate config-urations with an EOT of 0.6 nm, a body thickness of 20 nmand a source doping of 1x1020cm−3. (a) Unshifted and (b)shifted characteristics such that the VGS at which IOFF is1x10−11A/µm coincides. This shift can be accomplished by aproper choice of gate workfunction.

0.4 0.810-9

10-7

10-5

10-3

0.4 0.8

VDS = 0.3V

VGS(V)

(b)

Line Point

I (A/

m)

VGS(V)

(a)

60m

V/de

c

60m

V/de

c

FIG. 23. QM simulated transfer characteristics of anIn0.53Ga0.47As pocketed pointTFET with a Tpo of 3 nm anda pocketed lineTFET with a Tpo of 6 nm. The TFETs aredouble gate configurations with an EOT of 0.6 nm, a bodythickness of 10 nm for the pointTFET and 40 nm for thelineTFET and a source and pocket doping of 5x1019cm−3.(a) Unshifted and (b) shifted characteristics such that theVGS at which IOFF is 1x10−11A/µm coincides. This shift canbe accomplished by a proper choice of gate workfunction.

the EOT. A second aspect is the degree in which a givenvariation in gate voltage moves the equipotential lines inthe device closer together and hence increases the electricfield locally. By tuning both aspects, the gate control ata tunnel junction can be enhanced or decreased.

To improve TFET performance for conventional logicapplications, it is advantageous to enhance the gate con-

18

Source

DrainSource

Gate

p i n

DrainSource

Gate

p i n

Gate

p i n Drain

Gate

(a)

(b)

(c)

FIG. 24. (a) Single gate, (b) double gate and (c) gate-all-around TFET configuration.

trol at the source-channel tunnel junction (Section IX A),and to decrease it at the channel-drain junction (Sec-tion IX B). The former improves the TFET SS and ION,while the latter reduces the ambipolar current and CGD.In this section, gate configurations addressing both re-quirements are discussed.

A. Improving source-channel BTBT

A first way to improve the gate control at the source-channel junction is to decrease the EOT, which increasesthe electrostatic potential drop in the semiconductor.Like a MOSFET, the TFET performance therefore bene-fits from the introduction of high-k materials as the gatedielectric86–88.

A second way to improve the gate control at thesource-channel junction is to go from a single-gate (SG)to a multi-gate (MuG) to a gate-all-around (GAA)configuration89,90 (see Fig. 24), an approach which is alsoapplied to MOSFET. This requires a transition from aplanar to a protruding structure. A multi-gate configu-ration can be implemented as a finFET, where the gatecovers three sides of the device body. Going further, theTFET body can be realized as a horizontal or verticalnanowire (NW), with the gate wrapped around.

The tighter gate control can be seen when comparingthe electrostatic profile of a single gate to that of a dou-ble gate configuration89 (see Fig. 25). When a secondgate is added, the equipotential lines are curved morestrongly. A consequence is that the electric field close tothe source region is enhanced and hence the tunnel pathlengths are reduced, improving ION. The electric field isnow increasing towards the source region. Therefore, agiven increase in VGS results in a larger increase in elec-tric field than in the single-gate configuration, because

the electric field now increases both due to a larger totalvoltage drop between source and gate, and because thetunneling moves closer to the source where the equipoten-tial lines are more closely spaced, and the electric field ishigher. The result is a beneficial impact on the SS. Thiseffect is enhanced further for a MuG or GAA structureas illustrated in Fig. 26(a).

Further scaling of the body thickness has an additionalbeneficial impact on the gate control. As the gates movecloser together, the curvature of the equipotential linesbecomes more pronounced, and the electric field henceincreases. As explained in the previous paragraph, thisbenefits the SS of a pointTFET as illustrated in Fig. 27for a pocketed point TFET. For a double gate lineTFET,the body scaling does not benefit performance above acertain minimum body thickness, as the gate depletes thesource locally underneath the gate and tunneling startsfrom close to the undepleted source region (see Fig. 21),which is at source voltage. Hence, the two depletedsource regions underneath the two gates are disconnectedin the lineTFET.

Although body scaling can improve performance, size-induced quantum confinement (SIQC) effects becomemore important as the body thickness is scaled to di-mensions comparable to the exciton Bohr radius of thematerial91,92. SIQC results in a global increase of thematerial bandgap, and hence an increase in tunnel pathlengths. As discussed in Section VI, this can be detri-mental for ION and can consequently undo some of theadvantage that comes with improved gate control. Inparticular, a GAA structure is more affected by SIQCthan a MuG or SG configuration as it is confined in twodirections. Fig. 26(a) shows this can even result in asmaller ION for the GAA configuration than for the DGconfiguration. Similar to the case of FIQC, materialswith small effective masses are more affected by SIQC.

Specific care must be taken when scaling the bodythickness of lineTFET or pointTFET configurations, toprevent excessive depletion of the source region82,93. Un-derneath the gate-source overlap, a depletion region ex-tends into the source, with a maximal extent in the ON-state (as explained in Section III A). If the body of thedevice is too thin, the depletion regions of different gatestouch even before the device reaches the ON-state, result-ing in depletion of the source over the full body thickness.For a lineTFET, this means no more tunnel paths per-pendicular to the gate are available. Only much longernon-orthogonal tunnel paths are available and the cur-rent drops accordingly (see Fig. 27). Since the lineTFEToperation depends on the gate-source overlap, the bodythickness can therefore not be scaled below a certain crit-ical thickness. This thickness is determined by the sumof the depletion lengths underneath the gate-source over-laps in the ON-state. The depletion lengths themselvesare determined by the doping level of the source and ofthe pockets, if present. In a pointTFET, depletion overthe full body thickness increases the tunnel path lengths,resulting in a drop in current for high VGS. In this case,

19

20

0

10

z (n

m)

(a) (b)0.85 V

-0.5 V

FIG. 25. Electrostatic potential profiles at the source-channel junction for a (a) single gate and (b) double gateIn0.53Ga0.47As p-i-n TFET at a VGS of 1 V and a VDS of0.5 V. Six contour lines have been highlighted in each config-uration.

FIG. 26. (a) QM simulated transfer characteristics at VDS

= 0.2 V of InAs (line with triangles) SG ultra thin body(UTB), (dashed line) DG UTB, and (gray line) GAA NW de-vices. Body thickness or diameter is 6 nm. The NW currentis normalized with its diameter. The OFF-to-ON gate volt-age swing ∆-VGS is indicated. (b) CB and VB edges alongthe transport direction x of the 6 nm p-i-n SG UTB deviceat the onset gate voltage. Λ indicates the tunneling barrierwidth, ψS is the electrostatic potential in the middle of thegate, and Efl and Efr denote the source and drain Fermilevels, respectively. (c) Same as (b) for the 6 nm DG UTBdevice. (d) Same as (b) and (c) for the 6 nm GAA NW de-vice. Current leakage paths are indicated by dashed arrowsin (b), (c), and (d) c©2009 IEEE. Reprinted, with permission,from IEEE Elec. Dev. Lett. vol. 30, no. 6, pp. 602604, 2009.

full depletion of the source can be avoided by reducingor removing the gate-source overlap for thin body thick-nesses.

-1.0 -0.5 0.0 0.510-11

10-9

10-7

VDS = 0.5V

I (A/

m)

VGS (V)

point: line: 30nm 30nm 20nm 20nm 15nm 15nm 10nm 10nm

Tbody

FIG. 27. QM simulated transfer characteristics of Si pocketedpoint and lineTFETs for varying body thickness. The con-figurations are as shown in Fig. 17, but have a double gate.The gate-source overlap for the 10 nm body pointTFET con-figuration is removed. For the lineTFET, the length of thegate-source overlap and the pocket are 20 nm. The EOT is0.6 nm. Source and pocket doping are 1x1020cm−3.

B. Reducing channel-drain BTBT and CGD

The ambipolar current can be reduced by introduc-ing a gate-drain underlap64 (see Fig. 28(a)). The un-derlap decreases the gate control on the channel-drainjunction. Since the desired BTBT takes place locallyat the source-channel junction, the gate does not haveto cover the full channel as in a MOSFET to enforce aparticular band bending and hence tunnel path lengthat the source-channel junction. The underlap increasesthe distance between the gate and the channel drain-junction and consequently reduces the BTBT efficiencyat the drain. The short gate has the added benefit of re-ducing CGD, which is responsible for the Miller effect (seeSection XI C). Shortening of the gate can proceed downto the length at which it loses control over the source-channel junction (typically lengths of 10 nm and below).Care has to be taken as well that the resistance in theungated channel region does not surpass the resistanceof the tunnel barrier, to avoid an observable reduction inthe desired TFET current.

Instead of removing part of the gate, an alternative isto make the gate heterogeneous, for instance by intro-ducing two different metals, each with a different workfunction94 (see Fig. 28(b)). This is also called a dual ma-terial gate TFET. Although both metals are biased atthe same VGS, the work function at each of the tunneljunctions (source-channel and channel-drain) determinesthe amount of local band bending and hence the localtunnel barrier. The two work functions can be optimizedseparately: at the source-channel junction for a minimaltunnel barrier in the ON-state and at the channel-drain

20

DS p i n

DS p i n

Gate

(b)

(c)

DS p i n

Gate(a)

WF 1 WF 2

FIG. 28. Gate stack configurations for a p-i-n TFET aimed atreducing ambipolar behavior. (a) Short gate, (b) dual metalwork functions and (c) dual EOT dielectric.

junction for a maximal tunnel barrier in the OFF-state.

The same can be achieved by reducing the EOT only atthe source-channel junction, while retaining a large EOTat the channel-drain interface95 (see Fig. 28(c)). This canbe implemented with different physical oxide thicknesses,or with a high-k dielectric at the source side and a low-kdielectric at the drain.

X. STRAIN

Similar to a MOSFET, mechanical strain impactsTFET performance. This is a result of the effectstrain has on the band structure (Section X A), an ef-fect which can be incorporated in TFET models (Sec-tion X B). Strain can be externally applied as a per-formance booster, and is also intrinsically present at alattice-mismatched heterojunction (Section X C).

A. Impact of strain on the band structure

Mechanical strain can have an important effect onthe band structure of a semiconductor, since it altersthe bond lengths and changes the crystal symmetry96.Firstly, strain warps the curvature of the energy bands,and hence influences the effective masses. This effect isexploited in MOSFETs to increase carrier mobility, bychoosing a strain configuration such that the effectivemasses in the transport direction are decreased97. Sec-ondly, strain shifts the relative positions of valley edges,such that the bandgap changes. Thirdly, as a result ofbroken symmetries, strain lifts certain energy band de-generacies, which modifies the DOS. Most notably, straincan lift the degeneracy between the heavy and light holevalence band.

B. Strain modeling

A common approximate model to study the effect ofstrain on the band structure is the deformation potentialmodel98. The strain due to the deformation is assumedto be small and gradually varying, such that the effect onthe energy band edges can be treated as if it were a smallapplied electrostatic potential. The shift in the bandedges then varies linearly with the strain components:

∆En =∑ij

Ξijεij (28)

with En the band edge of band n, εij the elements of thestrain tensor and Ξij the so-called deformation potentialconstants, available in literature. The deformation po-tential model can be directly applied in semiclassical ef-fective mass-based simulators as a correction on the bandedges.

Strain can be introduced into more complex bandstructure models as well. In the k·p-model, strain canbe incorporated by the addition of a strain interactionterm as proposed by Pikus and Bir99, which includes thedeformation potential constants of Eq. (28). In the tight-binding approach, the integrals of Eq. (21) are adjustedbased on the strain-induced change in bond lengths andangles100. The introduction of strain in these models ac-counts for both the shift in band edge energies and thechange in effective masses. Strained band structure mod-els can be used in fully quantum mechanical simulations,but are also useful to extract band edge energies andeffective masses, which serve as inputs to semiclassicalmodels101.

C. Strain in TFET

Since TFET operation depends heavily on the bandstructure, strain affects the TFET performance. Straincan be induced intentionally like in a MOSFET, e.g.by external stressors, to improve ION by reducing EG

and mR102 (see Section VI A). Similarly, the shifting

of the band edges due to strain can induce a more fa-vorable band alignment at a heterojunction103 (see Sec-tion VII C). Specifically in indirect materials, the relativeshift of conduction band valleys can render the materialdirect104. This is of particular interest in Ge, where thedifference between the indirect and direct bandgaps issmall.

Under uniaxial or biaxial strain conditions, however,the valence band DOS is reduced due to the splitting ofheavy and light hole bands. This is a result of a reduc-tion of crystal symmetry. The smaller valence band DOSincreases the source doping degeneracy and can hence re-sult in an SS degradation (see Section VI B). The degra-dation can be prevented with a lowly doped source regionin combination with a highly doped pocket at the tunneljunction, as discussed in Section VIII A. Fig. 29 illus-trates using k·p-based quantum mechanical simulations

21

0.6 0.910

-11

10-9

10-7

10-5

10-3

0.6 0.9

VDS

= 0.3V

VDS

= 0.3V

VGS

(V)

(b)

Hetero p-n-i-n

Hetero p-p-n-i-n strainedI

(A/

m)

VGS

(V)

(a)

60m

V/d

ec

DS

G

G

n i n

DS

G

G

p n i n

p- p+

FIG. 29. QM simulated transfer characteristics of the un-strained pocketed GaAs0.5Sb0.5/In0.53Ga0.47As pointTFETof Fig. 19 compared with a p−p+n+in version of this TFET(inset). The latter TFET is under a uniform tensile biaxialstrain of 500 MPa and has a p-type pocket of 4 nm and andan n-type pocket of 3 nm, both with a doping of 5x1019cm−3.The source doping is 5x1018cm−3. The TFET is a double gateconfiguration with an EOT of 0.6 nm and a body thicknessof 10 nm. The strain was included in the quantum mechan-ical simulations using a k·p-based model. (a) Unshifted and(b) shifted characteristics such that the VGS at which IOFF is1x10−11A/µm coincides. This shift can be accomplished by aproper choice of gate workfunction.

that with this approach uniform strain can be used tofurther improve performance103.

Strain can also be inherently present in a TFET, e.g.at the heterojunction of two lattice mismatched materi-als. The strain profile in this case is very non-uniform,making it difficult to predict the exact impact on theTFET performance.

XI. CIRCUIT CONSIDERATIONS

Certain TFET features require additional care whendesigning circuits. The most important are the am-bipolar effect (Section XI A), the asymmetrical structure(Section XI B), the Miller capacitance (Section XI C) andthe superlinear onset in the output characteristics (Sec-tion XI D).

A. Ambipolar effect

The TFET ambipolarity can result in an increasedswitching leakage in a TFET inverter, but can just aswell be used to design more compact digital and ana-log circuits if the positive and negative switching ofthe gate voltage to turn on the tunneling current isexploited105,106. For good ambipolar behavior in these

applications, both the source-channel and channel-drainjunction have to be optimized to obtain similar ION andSS. This stands in contrast to conventional logic applica-tions, in which the channel-drain tunneling is suppressed(Section IX B). In digital circuits, the ambipolarity canbe used to create more complex logic gates with fewercomponents105. These ambipolar gates have control in-puts that determine the bias point, and hence the polar-ity of the devices. In analog applications, an ambipolaramplifier for example, exhibits both positive and nega-tive small-signal gain, depending on the bias point106.This allows it to function as both a common-source andcommon-drain amplifier, without changing the physicalimplementation.

B. Asymmetrical structure

Unlike a MOSFET, the TFET has an asymmetricalsource and drain doping and therefore behaves signifi-cantly different for a positive or negative VDS polarity107.As the p-i-n diode is reverse biased in normal TFET oper-ation, the sign of VDS is fixed to positive for nTFET andnegative for pTFET. When properly designed, the dom-inant current is BTBT-based with leakage mechanismsas described in Section VI C. Reversing the sign of VDS

brings the p-i-n diode in forward bias. At small forwardbias, the current is typically negligible compared to thecurrent at similar reverse bias, except for designs withsufficiently high source doping such that (Esaki-) tunnel-ing becomes significant108. Even then, a drop in currentis typically present upon increasing VDS as the tunnelingdecreases, before the forward bias diode diffusion currentreaches sufficiently high values to become dominant.

The asymmetrical TFET conduction can be a concernfor Static Random Access Memory (SRAM) circuits. Instandard 6-transistor (6T) SRAM cells, the two accesstransistors are required to conduct current in two direc-tions. The asymmetrical conduction leads to unaccept-able read and write static noise margins and hence in-stability of the SRAM cell109. Alternative SRAM celldesigns with increased number of transistors have beenproposed to circumvent this issue109,110.

Weak conduction in one direction also prevents the dis-charging of transient noise signals that appear on a circuitnode through capacitive coupling111. These signals canat times become very large and significantly surpass VDD

and therefore be detrimental to device reliability. Alsothe circuit timing suffers from these excessive noise sig-nals. To alleviate this issue, the forward Esaki tunnelingcurrent present at low VDS can be used to evacuate theexcess charge. This requires a sufficiently high degener-acy in the source.

Several other logic circuits, like the basic inverter, aremostly unaffected by the asymmetry. It is even possiblefor specific basic circuits to exploit the unidirectional-ity to redesign the circuit with fewer transistors than inconventional CMOS, e.g. the pass-gate multiplexor111.

22

C. Miller capacitance

A high CGD creates an enhanced Miller effect, whichresults in over-and undershoots in the transient behaviorof an inverter. The peak voltages VP of the over- andundershoots can be expressed as112:

VP =CM

CM + CLVDD (29)

with CL the load capacitance of the inverter and with CM

comprising the CGD of both nTFET and pTFET of theinverter. It is possible to decrease VP by increasing CL,but this has the downside of also increasing the inverterfall time delay. Care must therefore be taken in the devicedesign to keep CGD low in the first place.

The gate capacitance division in gate-source capaci-tance CGS and gate-drain capacitance CGD is differentfrom the MOSFET-case, because charge injection fromthe source requires a tunneling event, while charge in-jection from the drain is via thermal injection, similarto the MOSFET-case. Therefore, when the tunneling ef-ficiency at the source side is comparatively low, and inthe absence of a strong SRH process, the carriers in thechannel are supplied by the drain and the full channeldetermines CGD. CGS is then determined by the deple-tion of the highly-doped source region, hence resulting ina decreasing capacitance with increasing VGS (nTFET).The channel charge is determined by the position of thedrain Fermi level and the conduction band in the chan-nel (nTFET). A channel material with a lower DOS inthe conduction band (nTFET) hence results in a smallercharge build-up in the channel and the correspondingCGD is also smaller112. Despite the fact that Cg ≈ CGD

if the tunneling efficiency at the source is low, the CGD

can hence be limited if the TFET is properly designed.Also a gate-drain underlap can help to reduce the Millereffect113.

In cases where the tunneling efficiency is high and thedevice is fully in the ON-state, a significant amount ofcharge in the channel is supplied by the source. Like aMOSFET, the TFET then exhibits a linear region, inwhich charge is contributed equally by source and drain,and a saturation (pinch-off) regime, in which charge isuniquely supplied by the source. The gate capacitance

is divided accordingly between the contacts. Improvingthe source tunneling efficiency is therefore also beneficialin reducing the Miller effect.

D. Superlinear onset

As discussed in Section III C, the TFET output char-acteristics can have a superlinear onset19–21. The smallcurrent at low VDS delays the last part of the charging ordischarging of the load capacitance in a TFET inverter.This increases the inverter rise and fall times and henceincreases the total circuit delay. Additionally, recoveryfrom transient noise signals is less efficient when the out-put characteristics are superlinear114. As suggested inSection III C, the superlinear onset can be reduced byimproving the BTBT efficiency at small VDS.

XII. EXPERIMENTAL STATUS

After describing the device physics and architectureoptions in previous sections, this section is intended togive an overview of experimental realizations. The cur-rent status of experimental TFET transfer characteris-tics is summarized in Fig. 3017,53,55–58,81,115–129. Thecurves have been selected to have a point-SS lower than70 mV/dec, which means they are either close to or belowthe ideal MOSFET limit of 60 mV/dec for a given volt-age range. A variety of experimental techniques is usedto fabricate these structures8. Some configurations canbe seen to obtain a sub-60 mV/dec SS, demonstratingthe steep switching potential of TFET. None of the dis-played curves, however, attains all requirements for SS,ION, IOFF and I60 as specified in Section VI, and whichare required to be a viable replacement for MOSFET.The comparison between nTFET and pTFET shows thatfewer experimental realizations of pTFET exist, with aperformance generally inferior to nTFET. The reasonsbehind this discrepancy are discussed in Section VI B. Itis clear from Fig. 30 that a gap still needs to be closedbetween the promising theoretical predictions and actualexperiment. Note, however, that some configurationswhich are promising in simulations, confined III-V het-erostructure NW, are challenging to fabricate, and havenot yet been experimentally realized.

XIII. CONCLUSIONS AND OUTLOOK

In this article, the TFET was discussed from the per-spective of device physics. The basic operating princi-ple based on BTBT enables the TFET to obtain a sub-60 mV/dec SS at room temperature. This makes it a

promising candidate to circumvent the increasing powerissues in scaled MOSFET technologies. The main chal-lenges for TFET are to obtain a low average SS, a highION and low IOFF, or stated differently: a high I60, andthis for both nTFET and pTFET. Accurate predictivemodels are required to meet these challenges, with quan-

23

0.0 0.2 0.4 0.6-0.6 -0.4 -0.2 0.0

10-6

10-4

10-2

100

102

In0.7Ga0.3As SG | 0.2V [127] Si | 0.6V [58] CNT MuG | -0.5V [17] InP/GaAs NW | -0.75V [128] Si NW GAA | 0.1V [117] Si SG | 0.05V [81]

VGS(V)nTFET

Si/InAs NW | 1V [53] In0.53Ga0.47As/In0.7Ga0.3As

line SG | 0.05V [55] MoS2/Ge | 0.1V [57] Si/Ge SG | 0.5V [121] CNT MuG | -0.01V [120] sGe DG | 1V [119]

60mV/

dec

I (A/

m)

I60

60mV/dec

pTFET Si SG | -1V [126] Si NW GAA | -0.5V [116] Si line MuG | -0.05V [56] sSiGe SG | -0.1V [125] Si MuG | -0.1V [124]

FIG. 30. Experimental transfer characteristics in literature of nTFET and pTFET. Only curves with an SS lower than70 mV/dec have been included. The legend includes the material system (s-prefix stands for strained), gate configuration andVDS. The legend entries are ordered according to the intersection of the corresponding curves at a VGS of -0.2 V and 0.2 V.Also indicated is the target value for I60 mentioned in Section VI B. This figure is an updated version of Fig. 2 of Lu et al7.

tum mechanical simulators complementing more andmore the semiclassical models typically used for MOS-FET. These models can help in choosing the optimal ma-terial system, with alternative group IV materials, III-Vmaterials and 2D materials proving interesting alterna-tives for Si. Combining materials in a heterostructureprovides an additional degree of freedom in the devicedesign. Other performance improvements can be gainedfrom dopant pockets or from an optimization of the gatestack configuration. The presence of strain can have abeneficial effect on the device performance. Finally, sev-eral specific characteristics of the TFET operation at adevice level also have consequences for its use in circuits,suggesting the need for co-optimization of device and cir-cuit. The gap between theoretical predictions and exper-imental realizations today shows that many challengesare still to be overcome, before the TFET’s appearancein low-power products.

XIV. LIST OF ABBREVIATIONS

BGN: BandGap NarrowingBTBT: Band-To-Band-TunnelingCMOS: Complementary Metal-Oxide-Semicon-

ductorDG: Double GateDOS: Density Of StatesEF: Envelope FunctionEOT: Effective Oxide ThicknessFIQC: Field-Induced Quantum ConfinementGAA: Gate-All-AroundMOSFET: Metal-Oxide-Semiconductor Field-Effect

TransistorMuG: Multi-GateNEGF: Non-Equilibrium Green’s FunctionNW: NanoWireQM: Quantum MechanicalQTBM: Quantum Transmitting Boundary MethodSS: SemiClassicalSIQC: Size-Induced Quantum Confinement

24

SG: Single GateSRAM: Static Random Access MemorySRH: Shockley-Read-HallSS: Subthreshold SwingTAT: Trap-Assisted TunnelingTFET: Tunnel Field-Effect TransistorTMD: Transition Metal DichalcogenideWF: Work FunctionWKB: Wentzel-Kramers-Brillouin

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