the physical and electrical effects of metal-fill ... · index terms— chemical-mechanical...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 3, MARCH 1998 665

The Physical and Electrical Effects ofMetal-Fill Patterning Practices for OxideChemical-Mechanical Polishing Processes

Brian E. Stine, Duane S. Boning,Member, IEEE, James E. Chung, Lawrence Camilletti,Frank Kruppa, Edward R. Equi, William Loh, Sharad Prasad, Moorthy Muthukrishnan,

Daniel Towery, Michael Berman, and Ashook Kapoor

Abstract—In oxide chemical-mechanical polishing (CMP) pro-cesses, layout pattern dependent variation in the interlevel di-electric (ILD) thickness can reduce yield and impact circuitperformance. Metal-fill patterning practices have emerged as atechnique for substantially reducing layout pattern dependentILD thickness variation. We present a generalizable methodologyfor selecting an optimal metal-fill patterning practice with thegoal of satisfying a given dielectric thickness variation spec-ification while minimizing the added interconnect capacitanceassociated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement inuniformity in one case and a 60% improvement in the othercase, and illustrate that pattern density is the key mechanisminvolved. The pros and cons of two different metal-fill patterningpractices—grounded versus floating metal—are explored. Crite-ria for minimizing the effect of floating or grounded metal-fillpatterns on delay or crosstalk parameters are also developedbased on canonical metal-fill structures. Finally, this methodologyis illustrated using a case study which demonstrates an 82%reduction in ILD thickness variation.

Index Terms—Chemical-mechanical polishing (CMP), designfor manufacturing, metal-fill, within-die variation.

I. INTRODUCTION

I N recent years, chemical-mechanical polishing (CMP) hasemerged as the primary technique for planarizing interlayer

dielectrics [1], [2]. Although CMP is very effective at reducingthe as-deposited step height and achieves a measure of globalplanarization not possible with either spin-on or resist etchback

Manuscript received February 28, 1997; revised September 10, 1997. Thereview of this paper was arranged by Editor Y. Nishi. This work was supportedby ARPA Contract N00174-93-C-0035, AASERT Grant DAAHA04-95-1-0459, and an Intel Foundation graduate fellowship.

B. E. Stine, D. S. Boning, and J. E. Chung are with MicrosystemsTechnology Laboratories, Department of Electrical Engineering and ComputerScience, Massachusetts Institute of Technology, Cambridge MA 02139 USA.

L. Camilletti was with the Digital Equipment Corporation, Hudson, MA01749 USA. He is now with Rockwell Semiconductor Systems, NewportBeach, CA 92660 USA.

F. Kruppa and E. R. Equi are with the Digital Equipment Corporation,Hudson, MA 01749 USA.

W. Loh, S. Prasad, M. Muthukrishnan, and D. Towery are with LSI Logic,Inc., Milpitas, CA 95035 USA.

M. Berman was with LSI Logic, Inc., Milpitas, CA 95035 USA. He is nowwith LSI Logic, Gresham, OR 97006 USA.

A. Kapoor was with LSI Logic, Inc., Milpitas, CA 95035 USA. He is nowwith National Semiconductor, Santa Clara, CA 95052 USA.

Publisher Item Identifier S 0018-9383(98)01669-4.

techniques [1], CMP processes are hampered by layout patternsensitivities which cause certain regions on a chip to havethicker dielectric layers than other regions due to differencesin the underlying topography [2]–[4]. This interlevel dielectric(ILD) variation must be kept in control due to aggressivelithographic depth-of-field focus budget requirements and thepotential impact of dielectric thickness variation on circuitperformance. This problem has become especially acute asperformance requirements have increased, dimensions havescaled, and larger die sizes have appeared (see Fig. 1). Also,CMP has found wider application in VLSI technology devel-opment and production serving as an enabling tool for shallowtrench isolation [5]–[7], damescene metallization technologies[8], and other novel process techniques.

Attempts to control CMP intralevel dielectric thicknessvariation include an exhaustive search for and experimentationwith different consumable and process choices (especiallypads), but no consumable choice currently available appearsto reduce appreciably pattern-dependent dielectric thicknessvariation [9]; thus, the only viable choice available for reduc-ing layout pattern dependent dielectric thickness variation is tochange the layout pattern itself via the introduction of metal-fill patterning. Metal-fill patterning is the process of filling thelarge open areas on each metal layer with a metal pattern,which is either grounded or left floating, to compensate forpattern-driven variations.

Note that metal-fill patterning practices are anintrinsicintegration issue, i.e., the problem cannot be solved either atthe unit process step or as a circuit design issue alone; there isa need to integrate process and design concerns and deal withthe problem as a whole. Improvements in uniformity at theprocess/CMP module level resulting from metal-fill patterningpractices must be carefully checked against design/electricalconcerns of any added interconnect capacitance resulting frommetal-fill.

Because of the confidential nature of metal-fill pattern-ing practices and design rules in general, relatively littleinformation about metal-fill patterning practices has beenpublicly reported. Ichikawaet al. [10] describe a metal-fill patterning practice for planarizing a five-level spin-on-glass (SOG) interconnect CMOS process. A procedure forautomatically generating metal-fill patterns is presented andsome consideration is given toward optimizing the metal-fill

0018–9383/98$10.00 1998 IEEE

666 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 3, MARCH 1998

Fig. 1. Range of ILD thickness variation versus die size. As the die size has increased, the range of ILD thickness variation has also increased. This can beattributed to the size of the chip approaching and then surpassing the finite planarization length of the CMP process. The data shown was simulated usingthe model in [14]. The same layout was used for each data point and scaled appropriately. Although this would seem to indicate that scaling should help theproblem, in reality, scaling forces are checked by ever increasing demands for higher transistor counts leading to larger and larger die sizes.

design-rule to meet a given planarity target and to reducethe effect of added interconnect capacitance associated withthe metal-fill; however, this methodology was developed forSOG processes, the consideration of capacitance effects isnot described completely, and simulation/modeling aspectsrelated to capacitance effects are not rigorously explored orstated. Camilletti [12] described and explored a metal-fillpatterning practice in a CMP process, and reported significantimprovements in uniformity. Stineet al. [13] also explored theeffects of metal-fill patterning practices on dielectric thicknessuniformity and presented a mechanism for the beneficialincreases in uniformity via pattern density modeling. In boththese papers, however, interconnect capacitance and designrule optimization concerns were not addressed.

This paper presents a unified methodology for designingand optimizing metal-fill design rules and procedures whichis suitable for inclusion in automated CAD tools and whichdeals with both CMP process/uniformity concerns at themodule level and capacitance/electrical concerns at the designlevel. While we are concerned with methods to help supportautomatic generation of metal-fill, we are not concerned withthe actual layout generation algorithms. Also, although thebeneficial effects of metal-fill patterning practices will bereviewed and the mechanisms for this improvement describedfully, we are particularly interested in developing a linkbetween specific metal-fill design rules and the resultant im-provements in ILD thickness uniformity. Finally, we areespecially interested in the key integration issues associatedwith optimizing metal-fill design rules to minimize the ac-companying increase in interconnect capacitance. Although

we only consider metal-fill patterning practices for traditionalback-end-of-line interconnect processes, the generic methodspresented here can potentially be adapted to shallow-trench,damascene, and other inlaid polishing processes.

This paper is organized in six major sections. Section IIdeals with the beneficial effects of metal-fill on dielectricthickness uniformity while Section III describes the mech-anisms responsible for the uniformity improvements due tometal-fill patterning practices. Section IV analyzes metal-fillinterconnect capacitance concerns and presents capacitanceevaluation methods. Section V presents a case study whichillustrates the methods developed in Sections III and IV whichallow the optimization of a metal-fill patterning practice givencertain technology parameters and design constraints. Finally,a summary and recommendation for future work are offeredin Section VI.

II. THE EFFECTS OFMETAL-FILL ON

DIELECTRIC THICKNESS UNIFORMITY

In this section, we demonstrate via two industrial-basedexperiments the beneficial effects of metal-fill patterning prac-tices on dielectric thickness uniformity. The first experimentwas conducted on existing test vehicles as an initial feasibil-ity and proof-of-concept study. The second experiment wasconducted on an actual product and used a more aggressivepatterning practice in an effort to explore more fully the gainspossible using metal-fill patterning practices.

In the first experiment, we used a standard test vehiclecontaining SRAM, defect density test structures, and devicearrays. Two versions of this mask set were produced. The

STINE et al.: PHYSICAL AND ELECTRICAL EFFECTS OF METAL-FILL PATTERNING PRACTICES 667

(a) (c)

(b) (d)

Fig. 2. Dielectric thickness distributions between metal-1 and metal-2 [(a) and (b)] and between metal-2 and metal-3 [(c) and (d)]. Reticle “A” did nothave metal-fill added while reticle “B” had metal-fill patterning.

first mask set, reticle “A,” did not contain any metal-fillstructures while the second mask set, reticle “B” containedmetal-fill structures. The fill pattern used in this experimentwas used as a buffer to fill these large open areas greaterthan m m between adjacent test structuresand circuitry. Also, no metal-fill pattern was placed lessthan 40 m away from any active circuitry. The metal-fill implementation on reticle “B” also needed structuresto accommodate yield inspection, electromigration testing,capacitance considerations, and device characterization needs.Thus, only a portion of the total eligible area for reticle“B” received metal-fill with the metal-2 level incorporatingslightly more pattern fill compared to the metal-1 level. A0.35- m CMOS technology was used to fabricate the teststructures. The ILD thickness was measured optically on ninedie (approximately 17 sites per die) on each wafer for severallots to yield approximately 30 000 measurements. The sitelocations on each die were selected from populations near thethickest regions and near the thinnest regions.

Fig. 2 shows the ILD thickness distributions (all thicknesseshave been normalized) for one die for structures patterned with

reticle “A” [Fig. 2(a) and (b)] and reticle “B” [Fig. 2(c) and(d)] at the ILD 1 and ILD 2 level. The standard deviation anduniformity for reticle “B” with pattern fill has improved byapproximately 20–25% and by 15% at the ILD 1 and ILD 2levels, respectively, compared with reticle “A” with no patternfill. The results for ILD 2 are not as pronounced as for ILD1 because the density of underlying topography in ILD 2before metal-fill was more uniform to begin with comparedto the underlying topography in ILD 1 before metal-fill. Asthe ANOVA table for the ILD 1 level in Table I shows, thedifference in standard deviation between reticles (i.e., withmetal-fill and without metal-fill) was the only statisticallysignificant difference observed (as opposed to wafer-to-waferor die-to-die type variation). Similar results were observed atthe ILD 2 level.

In the second experiment, the same experimental method-ology and process technology was used: two versions of areticle were generated, one without metal-fill (Reticle “A”)and one with metal-fill (Reticle “B”). In this case, however, amuch more aggressive metal-fill patterning strategy was imple-mented and actual product layout at the metal-2 layer was used


Fig. 3. Dielectric thickness versus pattern density (extracted from [11]). The interaction distance was 3.5 mm. The effect of restricting pattern densityto half of full scale is also schematically illustrated.

TABLE ITHE ANOVA TABLE FOR THE ILD 1 LEVEL FOR THE FIRST EXPERIMENT

DISCUSSED IN SECTION II. THE STANDARD DEVIATION IS MODELED

AS A FUNCTION OF THE WAFER, THE DIE, AND THE RETICLE USED.ONLY THE RETICLE EFFECT (METAL-FILL PATTERNING VERSUS NO

METAL-FILL PATTERNING) WAS FOUND TO BE STATISTICALLY SIGNIFICANT

in the experiment instead of that for a test vehicle. The ILDthickness was measured optically. For intradie measurementsfour sites/die (selected to achieve the largest range of variation)were measured on three dies per wafer across three wafers foreach split. For within-wafer and wafer-to-wafer measurementsone site on 21 dies per wafer was measured across all sixwafers in each split. Substantial improvement was observedat the intradie level (60% reduction) as well as within-wafer(35–40% reduction) and wafer-to-wafer (35–40% reduction).intradie variation for some products can be as high as 0.6mtotal range and 0.15m within-wafer [11].

In addition to the improvements in dielectric thicknessuniformity, other benefits including improved etch and lithog-raphy process uniformity are often observed. Also, metal-fillpatterning of test vehicles, such as in the first experiment, hasthe additional benefit of allowing the test vehicle to mimic

more closely the behavior of real-life products and reduceproduct learning cycles [12].

III. M ECHANISMS FORMETAL-FILL PATTERNING BENEFITS

The improvements in dielectric thickness uniformity ob-served in metal-fill experiments can ultimately be attributed tolayout pattern-density. The strong correlation between layoutpattern density and dielectric thickness is well recognized forCMP processes [11], [13]–[16], and it has also been demon-strated that layout pattern-density is the primary variablecontrolling CMP-induced intradie dielectric thickness variation[11], [14]. Pattern density can be defined as the ratio of raisedoxide area in a given square window to the area of the window.We assume that the window is square; thus, its size can berepresented by the length of one side of the window, whichwe term the interaction distance. Typical interaction distancesare in the range of 3–4 mm. For a more thorough definitionand discussion of pattern density, see [11] and [14]. By addingmetal-fill, the underlying topography is restricted to a confinedrange of pattern density. The restricted latitude of pattern-density yields a minimized spread in ILD thickness variationwhich is significantly smaller compared to the variation whichwould be encountered if the density were allowed to varyfull-scale (Fig. 3).

Stine et al. [14] have recently reported a universal closedform model for dielectric thickness variation in CMP pro-cesses. According to this model, dielectric thickness variationcan be related to pattern density (assuming sufficient polishingtime) via

(1)


Fig. 4. A contour plot of the achievable pattern density inside of an empty1 mm � 1 mm area versus the metal-fill design rule. The metal-fillpatterning scheme is shown in the inset. The buffer distance for this example has been fixed at 25�m: A minimum linewidth of 0.35 �m and aminimum linespace of 0.45�m has been assumed.

where is the dielectric thickness at a position on the die,is the initial dielectric film thickness before planarization,is the as-deposited film thickness, is the bulk polish rate ofblanket wafers, is time, and is pattern density as a functionof position on the die. According to (1), if a layout has a fullscale range of pattern density before metal-fill and sufficientmetal-fill is added to reduce the range in pattern density by50% then the resulting dielectric thickness variation shouldbe reduced by half. Furthermore, for a given CMP processadding metal-fill tends to increase the mean layout patterndensity (and dielectric thickness) across the chip resulting inthicker oxide films and correspondingly lower layer-to-layercapacitance values than would be seen in a non metal-filllayout1

Design decisions about the size and extent of metal-fillpatterning can be made based on models similar to (1). Thesedecisions can be made by assuming a worst case scenario (suchas a square open region free of metalmm mm in size)and examining the effect of adding metal-fill. For example,if one considers a metal-fill patterning scheme of verticallyoriented lines (see Fig. 4 inset) with a buffer distance defined

1Although increasing the dielectric thickness has the effect of reducinglayer-to-layer capacitance, coupling or line-to-line capacitance may actuallyincrease with increasing dielectric thickness due to decreased shielding effects.

as the distance between the nearest active circuit region and ametal-fill line of 25 m, a design chart can be generated (e.g.,Fig. 4) showing the pattern density that can be achieved insidethis mm mm square region for a given linewidth andlinespace of the metal-fill design. If it is desired to reducethe dielectric thickness variation in half, then a linewidthand linespace for the metal-fill design rule should be chosenwhich would give a pattern density inside themmmm square box of at least 50%. As Fig. 4 shows, there aremany possible design rules along the 50% contour which canmeet this requirement. Choosing a value along this contour aswell as other design rule issues (e.g., the choice of the bufferdistance and whether to use lines or square blocks) are dictatedby electrical/capacitance considerations and are dealt with inthe next section.

Although the above method of selecting a metal-fill designrule to meet a uniformity criterion guarantees that all blankareas greater than mm mm in size will have theminimal allowable density (50% in this example), it does notabsolutely guarantee that the entire layout will have this valueof minimum pattern density. Consider this artificial example:a layout consisting entirely of 1-m lines and 10-m spaces.Since there is no blank area greater than 50m (which is twotimes the buffer distance in the above example), no regions


of this chip qualify for metal-fill; but, the minimum patterndensity on chip is only 10%. Also, if one corner of a layouthas a large high density block and the other corner has alarge low density block, the best possible range in dielectricthickness variation is ultimately dictated by the difference inthe densities of these two regions. These issues are especiallyacute in test structures where high density defect structures(typically snakes and combs) are placed in one area and lowerdensity circuit blocks or devices arrays are placed in anothercorner resulting in a severely compromised layout in the senseof only allowing marginal improvement in uniformity throughmetal-fill patterning. However, this situation is quite artificialand most regions of modern ASIC and logic design layout arefilled with dense circuit regions requiring metal-fill only for thelarger open areas. Significant improvements in uniformity arethus feasible for these designs as the case study in Section Villustrates.

IV. I MPACT OF METAL-FILL ON INTERCONNECTCAPACITANCE

In addition to meeting a uniformity constraint, a welldesigned metal-fill patterning practice should also minimizethe added interconnect capacitance associated with the metal-fill. In many ASIC designs, there are large open areas orsparse regions near or around routing channels which areprime candidates for metal-fill. Especially for regions nearrouting channels, blindly adding metal-fill without consideringthe impact on capacitance is disastrous resulting in increaseddelay or coupling.

The issues associated with capacitance and metal-fill arecomplex. Key issues are the best choice of the buffer distance(the distance between metal-fill and the nearest active metal-line), grounded versus floating metal-fill lines, and the shapeof the metal-fill patterns (e.g., lines versus blocks). For denselogic designs where the amount of metal-fill needed is lowand where the number of products on which a designer isfocused is also low, the placement and choice of metal-fillmight ultimately be left as a decision by the circuit designer.For ASIC design, however, there are far too many designswith rapid design schedules and considerable areas which needmetal-fill: automated metal-fill placement is often essential. Inthis section, we will discuss the tradeoffs between groundedand floating metal-fill and present a methodology for devel-oping a metal-fill design rule suitable for automated metal-fillplacement with an interconnect capacitance constraint.

A. Grounded versus Floating Metal-Fill

One of the most important decisions regarding metal-fillconcerns floating metal-fill, i.e., leaving all metal-fill regionsunconnected, versus grounded metal-fill, or connecting allmetal-fill regions to the nearest ground connection. In termsof interconnect capacitance, grounded metal-fill tends to affectdelay attributes in a layout while floating metal-fill tends toincrease coupling/crosstalk attributes.

For grounded metal-fill, the primary advantage is that allmetal-fill regions are at a known potential; thus, traditionallayout-parasitic extraction tools can be used to re-verify andsimulate a layout after the metal-fill has been placed. The

(a) (b)

Fig. 5. An illustration of (a) vertical line filling, which is recommended forgounded metal-fill and (b) block filling, which is recommended for floatingmetal-fill. Note the bridging bars in (a) and that in a floating metal-fillconfiguration regions A and B cannot couple very easily in (b) but couldin (a) if the fill were floating. Because the fill in (a) is grounded, the metal-filllines do not permit coupling between regions A and B, although there maybe an overall increase in capacitance and delay.

drawbacks are that each metal-fill region needs to be connectedto ground, preferably to a close-by terminal. This is often noteasy and places an additional strain on already overburdeneddesign tools. For this reason, it is better to use long lines asthe metal-fill pattern and to place small metal bridges betweenthese lines to allow ease of ground connection [see Fig. 5(a)].

For floating metal-fill, the advantage is that no connec-tions need to be made to ground; thus, floating metal-fillcan be generated automatically during tape-out. The primarydrawback is that floating metal-fill regions can now serveas additional coupling paths. To minimize extended rangecoupling effects, small unconnected square blocks should beused. Fig. 5(b) illustrates this point. If vertical lines were used[as in Fig. 5(a)], regions A and B, although many micronsapart, could couple to each other. As Fig. 5(b) shows, however,small square unconnected blocks minimize this behavior.

B. Minimizing the Effect of Metal-Fillon Interconnect Capacitance

In order to minimize the interconnect capacitance addedresulting from metal-fill, the total amount of metal-fill tobe added should be small, the linewidth of the fill patternshould be as small as possible, the spacing between fill “lines”should be maximum, and the buffer distance should be keptas large as possible. Unfortunately while this capacitanceminimization criterion is useful as a guideline, it has twoprimary flaws: 1) steps restricting the amount of metal-filland increasing the buffer distance have the unwanted effect oflimiting the possible improvements in uniformity using metal-fill and 2) this minimization is not a precise method and lacksquantitative criterion measures.

A more appropriate criterion can be formed by consideringthe canonical case of two lines spaced apart by twice thebuffer distance plus the linewidth or block width of one metal-


fill block or line. This spacing arrangement is the worst casescenario since spacing the active lines any further apart lessensany capacitance coupling/delay effects between each activelines and between any active line and any neighboring metal-fill regions. The buffer distance is initially chosen at somereasonable value (e.g., 25m The space between the twolines is then patterned with metal-fill of a particular linewidth

and linespace for the case of line filling [e.g., Fig. 5(a)]or a particular block width and block space for thecase of block filling [e.g., Fig. 5(b)]. A generic capacitancemetric is then computed which is suitable for the particulartype of metal-fill (grounded or floating). For the floating designstrategy shown in Fig. 6(a), a reasonable capacitance metric(all capacitances are per unit length) might be

(2)

where is the capacitance from an active line to a metal-fill block and is the capacitance from one active line tothe other active line for the case of floating metal-fill [seeFig. 6(a)]. For the grounded strategy shown in Fig. 6(b), areasonable capacitance metric might be

(3)

where is the capacitance from an active line to a groundedmetal-fill line, is the overlap capacitance between anactive line above and an underlying metal-fill region, and

is the capacitance from one active line to the otheractive line [see Fig. 6(b)]. Note that both metrics use theratio of the capacitance (either coupling capacitance or delaycapacitance) present in the metal-fill pattern to the capacitancepresent before metal-fill. The individual capacitance values(e.g., can either be computed using TCADsimulations or using closed-form approximations (see theAppendix). The value of is recorded and the ratio iscomputed again across a wide range of metal-fill spacing andwidth parameters.

The contour plot of (or 100 which represents thepercent change in capacitance) is then superimposed on top ofthe minimum pattern density contour plots versus line widthand line space. The desired minimum pattern density speci-fication is then coupled with the desired capacitance metricvalue specification to yield an optimized metal-fill design rule(see Fig. 7). The desired capacitance metric value is selectedto be as low or negative as possible, while still satisfyingthe desired uniformity criterion. If the capacitance metric issufficiently small or negative, a smaller buffer length valuecan be selected and a comparison plot can be generated for thenew buffer length value. A smaller buffer length is desirablefrom a uniformity perspective since smaller buffer lengthslead to denser fill and hence a higher probability of meetingthe minimum pattern density specification across the entirechip. An example of the entire metal-fill methodology fromuniformity criterion specification to capacitance evaluation anddesign rule specification is offered in the next section.

(a) (b)

Fig. 6. A stylized illustration depicted the definitions and capacitance typi-cally of interest in (a) floating metal-fill with block patterning and (b) groundedmetal-fill with vertical line patterning.

V. A M ETAL-FILL PATTERNING PRACTICE CASE STUDY

In this section, the methodology outlined in Sections III andIV will be exercised on the layout (see Fig. 8) of a bitbit 24-port memory register containing over 65 000 transistors[17]. Since completely automatic generation of metal-fill isdesired, a floating metal-fill design-rule is desired. First, for thecanonical structure the patterning scheme shown in Fig. 5(b)will be used. The goal will be to find design rules for the threecanonical parameters: the buffer distance , the blockwidth , and the block space Then, optimized metal-fillparameters will be selected and the impact of this optimizedmetal-fill on the case study (Fig. 8) will be evaluated.

In order to estimate the effect of the metal-fill pattern oninterconnect capacitance, a metric for the capacitance increasedue to metal-fill as discussed in Section IV-B needs to bedetermined. For this case study, we will use the canonicalstructure discussed in Section IV-B and (2) to evaluateNote that for this canonical structure, the metal-fill patternand surrounding active lines are isolated, i.e., no metal linesor features are shown above or below the structure and noground plane has been assumed. Although in reality featuresare seldom isolated from each other, this canonical form hasbeen assumed because it maximizes the coupling capacitancebetween lines (e.g., and If metal features wereplaced above or below, some shielding would occur and thecoupling capacitance between lines would be reduced by fringecapacitance from the line to the layer above or below. Asolution to the more general problem is not practical since inevery area of a layout the metal coverage above and below ametal-layer varies significantly. A statistical approach could be


Fig. 7. Contour plots of 100(C�� 1) is superimposed on contour plots of constant pattern-density to form a design chart for the coupling and optimizing

of pattern-density/uniformity specifications with interconnect capacitance specifications.

attempted in which the average and range of patterns aboveand below a given layer are extracted and used to form amodel database for capacitance evaluation, but this techniquewould complicate the formulation of a design rule since thecapacitance metric (c.f. above) becomes a distributionrather than one number.

The large number of calculations required (1000) tocompute the individual components of (e.g., and )and generate design-rule charts necessitate the use of simpleclosed form expressions instead of numerical simulations.More specifically, we will assume that and (see theAppendix) can be approximated by

(4)

(5)

where is the thickness of the metal and is the spacingbetween blocks, is the block width, and is the bufferlength [see Fig. 6(a)]. As Fig. 9(a) and (b) shows, the approxi-mations in (4) and the assumption of linewidth independence is

quite good except for small spaces where (4) overestimates thecapacitance. Also note that the proportionality constant in (4)is primarily dependent on metal thickness and not significantlyaffected by linespace. For the comparison in Fig. 9, the two-dimensional (2-D) capacitance solver RAPHAEL2 [18] wasused to evaluate the capacitance; the simulation structure isshown in Fig. 9(c).

In (5), the capacitance is composed of two terms. Thefirst term accounts for the coupling between the sidewalls ofthe active line on the left (line in Fig. 10) and one of themetal-fill blocks. The second term represents fringing fromthe sidewall of line to the perpendicular sidewall of ametal-fill block. A derivation for this second fringing termcan be found in the Appendix. In order to assess the validityof the assumptions and approximations in (5), several 3-Dsimulations were run using RAPHAEL [18] for the structureshown in Fig. 10. As Table II shows, the agreement betweensimulation and (5) is excellent. For the comparison shown inTable II, all lines except were grounded, and the capacitancebetween and every other metal region was simulated.

Fig. 11 shows a contour plot of versus block width andblock space superimposed on a contour plot of the minimumpattern density within a 1-mm block (see Section III) versusblock width and space. Contour plots are shown for buffer

2RAPHAEL is a registered trademark.


Fig. 8. The metal-1 layer of the layout described in [17] used in the metal-fill case study discussed in Section V. The layout is about7:9 mm � 9:2

mm and the minimum linewidth and space at metal-1 is 3�m:

TABLE IICOMPARISON OF THE CAPACITANCE APPROXIMATION IN (5) VERSUS SIMULATION

lengths of 10, 25, 50, and 100m If an entire layout werecomposed of features at the minimum feature width and spacefor metal-1, then the pattern density across the chip shouldaverage around 50%. Thus for our case study, we select theminimum pattern density criterion to be 50% since the majorityof features in the layout in Fig. 6 are placed at minimum widthand space.

Table III shows the block width and space combinationswhich achieve the 50% minimum pattern density criterion.These values were extracted from Fig. 11 using a minimumfeature width and space of 3 m as dictated by processconsiderations at the time Fig. 6 was designed. For TableIII, larger choices of line space invariably lead to highercapacitance metric numbers; thus, the minimum values werechosen (see Fig. 12). Although the capacitance metric min-

imizes for a buffer length closer to 50m, a buffer lengthof 25 m was chosen, because a 50-m buffer length wouldlimit the minimum space that could be filled by metal-fill toover 100 m (which would limit the permissible change inpattern density) and the relative gain in the capacitance metricnumbers would be marginally small. Note that if a differentminimum feature width and space is assumed, the numbers inTable III change, but the optimal buffer length is still in the25–50 m range.

Fig. 13 shows the simulated dielectric thickness betweenmetal-1 and metal-2 using the model in [14] for the layoutshown in Fig. 8. Fig. 13(a) and (b) shows the ILD thicknessvariation before metal-fill patterning and Fig. 13(c) and (d)shows the ILD thickness variation after optimized metal-fillpatterning using a buffer length of 25m, a block width


(a) (b)

(c)

Fig. 9. (a) Interconnect capacitance per unit length for two parallel lines 0.6�m thick. Note the relative independence of line width from capacitance.(b) The effect of interconnect capacitance for two parallel lines versus spacing and metal thickness with the metal width fixed at 2.5�m: Note therelatively good agreement(R2> 0:99) between the simulated capacitance values and the model shown and discussed in Section V. (c) The simulationstructure used in the comparison shown in (a) and (b).

TABLE IIIBUFFER LENGTH, BLOCK WIDTH, BLOCK SPACE VALUES WHICH MINIMIZE THE EFFECT OF THEADDED METAL-FILL PATTERN

ON INTERCONNECT CAPACITANCE AND ACHIEVE A MINIMUM PATTERN DENSITY VALUE OF 50% (EXTRACTED FROM FIG. 11)

of 9 m, and a block space of 3 m The range in ILDthickness variation has been reduced from 0.22m to justunder 0.04 m, a reduction of 82%. In addition to removingalmost completely the impact of dielectric thickness variationon circuit performance, substantial gains have been madetoward the manufacturability of this product (e.g., dielectric

thickness variation has been factored out of depth-of-focuserror budgets).

In this case study, two main assumptions were used: 1)the amount of overlap crosstalk (i.e., additional crosstalkintroduced between metal-3 and metal-1 due to placing metal-fill in metal-2) is relatively small, and 2) the optimal minimal


Fig. 10. The simulation structure used to evaluate the capacitance approxi-mation in (5). For the comparison, all lines exceptb1 where grounded, andthe capacitance betweenb1 and every other metal region was simulated usinga three-dimensional (3-D) capacitance solver.

Fig. 11. Design charts of minimum pattern density constraints superimposedon a relevant metric for evaluating the effect of a particular metal-fill designrule on interconnect capacitance. Design charts are shown for buffer lengthsof 10, 25, 50, and 100�m: These charts allow one to contrast uniformityconstraints with capacitance requirements. In reality, many of the negativecapacitance numbers shown are slightly larger due to neglected fringingelements.

pattern density criterion is roughly determined by the mini-mum feature width and space (50% density). Fig. 14 showsthe estimated range of ILD thickness variation versus minimalpattern density. Clearly, 50% is close to the optimum value.

Fig. 15(a) shows the simulation structure used to gaugethe impact of the metal-fill patterning practice used in thiscase study on overlap crosstalk. A m m metal

Fig. 12. Detailed view of the metal-fill design chart for a buffer length of25 �m: For the case study discussed in Section V, the optimal choice of 9�mand 3 �m for linewidth and linespace is highlighted. This value achievesa minimum pattern density of 50% and minimizes any added capacitanceassociated with the metal-fill. Linewidths and spaces below 3�m were notconsidered manufacturable.

plate was placed on metal-1 and metal-3 while metal-2 wasfilled with floating blocks. The structure was simulated usingFastCap [19] for different block widths and spaces. The resultsof the simulation are shown in Fig. 15(b) as percent increasein overlap capacitance versus the local density of the metal-fill pattern. A 50% pattern leads to an increase in overlapcapacitance of 20%. This simulation, however, is a worst casescenario and does not consider

1) the probability of having a large metal-1 and metal-3overlap where there is very little metal-2 is relativelysmall;

2) signal statistics;3) overlap capacitance is a net-by-net occurrence;4) and placing a large metal plate on metal-1 and metal-3

maximizes the overlap capacitance and tends to greatlyreduce the lateral sidewall capacitance due to shielding.

A less aggressive metal-fill patterning practice can be used(e.g., block width m and block space m fora minimal pattern density specification of 30%) to limit theincrease in overlap capacitance. At these values, the percentchange in lateral capacitance (approximately15%) is offsetby the increase in overlap capacitance, and the amount of ILDthickness variation is reduced by 50% (as opposed to 84%).

VI. CONCLUSION

In this paper, a methodology has been demonstrated for de-veloping design rules for metal-fill patterning practices whichtake into account dielectric thickness uniformity constraints aswell as the effect of metal-fill patterning on interconnect ca-pacitance. The methodology presented in this paper represents


(a) (b)

(c) (d)

Fig. 13. The simulated ILD thickness variation based on the model presented in [14] for the metal-1 layer of the layout shown in Fig. 7 for without metal-fill[(a) and (b)] and for with metal-fill [(c) and (d)] with a buffer-length of 15�m, a block width of 9�m, and a block spacing of 3�m:

Fig. 14. The estimated ILD thickness variation versus minimal pattern density criterion. The optimal value is near 50% as expected.

an important tool for reducing dielectric thickness variationin CMP processes. The procedure outlined in this paper is ofparticular interest to the ASIC community where the numberof products manufactured and the variety of layouts anddesigns encountered are both large necessitating an automatedprocedure for mitigating dielectric thickness variation.

Several extensions of this work can be identified. Mostnotably, the methodology presented in this paper can beextended to shallow trench isolation processes and inlaid metaltechniques such as copper damascene. Also, the methodologymight also be adapted to spin-on-glass (SOG) or to othernovel dielectrics processes. Finally, novel metal-fill patterning


(a)

(b)

Fig. 15. (a) The simulation structures used to evaluate the worst-case impact of metal-fill on overlap capacitance. (b) There is a strong relationshipbetweenthe density of the fill pattern and the amount of increase in overlap capacitance.

procedures can be developed. Key novel procedures include1) attaching all metal-fill patterns to ground gated throughtransistors so that the amount of grounding or floating canbe modulated as a function of switching activity or circuitcell function and 2) activity dependent metal-fill patterningin which metal-fill is used aggressively near noncritical slowtransitioning circuit blocks while conservative patterning isused near critical paths and rapid switching circuit blocks.

APPENDIX

Consider the illustrative drawing shown in Fig. 16. If weassume a parallel plate capacitance formula similar to (4) holdsthen the capacitance (per unit length) for the case shown inFig. 16 can be written as

(6)Fig. 16. An illustrative diagram used in the calculation of the fringingcapacitance formula discussed in the Appendix.

where is a proportionality constant. In (6), we are alsoassuming that For the examples considered in


this paper, this is a valid assumption. The capacitance per untillength in (6) can then be integrated across the entire span of

from 0 to

(7)

Integrating (7), we obtain

(8)

for the fringing component, , shown in Fig. 16. For thecoplanar capacitance, , the formula shown in (4) can beused. Summing , to account for fringing from both edges,and gives the approximation of (5).

ACKNOWLEDGMENT

Several people have contributed to this work, including D.Maung, E. Chang, R. Divecha, D. Ouma, T. Park, and V.Mehrotra at Massachussetts Institute of Technology; D. Het-herington at Sandia National Laboratories; and D. Ciplickas atPDF Solutions. The authors would also like to thank the staffof Digital Equipment Corporations Fab-6 fabrication facilityin Hudson, MA, for providing fabrication and measurementof data used here.

REFERENCES

[1] I. Ali, S. Roy, and G. Shinn, “Chemical mechanical polishing ofinterlayer dielectric: A review,”Solid State Technol., vol. 37, no. 10,pp. 63–70, Oct. 1994.

[2] M. Fury, “Emerging developments in CMP for semiconductor planariza-tion,” Solid State Technol., vol. 38, no. 5, pp. 47–54, Apr. 1995.

[3] P. Burke, “Semi-empirical modeling of SiO2 chemical mechanicalpolishing planarization,” inVLSI Multilevel Interconnect Conf., June1991, pp. 379–384.

[4] S. Sivaram, H. Bath, R. Leggett, A. Maury, K. Monnig, and R. Tolles,“Planarizing interlevel dielectrics by chemical-mechanical polishing,”Solid State Technol., vol. 35, no. 5, May 1992.

[5] J. Pierce, P. Renteln, W. Burger, and S. Ahn, “Oxide-filled trenchisolation planarized using chemical/mechanical polishing,” inProc.3rd Int. Symp. ULSI Sci. Tech. Electrochem. Soc., 1991, vol 91-11, p.650–656.

[6] A. Perera, J. Lui, Y. Ku, M. Arzak, B. Taylor, J. Hayden, M. Thompson,and M. Blackwell, “Trench Isolation for 0.45-�m active pitch andbelow,” in IEDM Tech. Dig., Dec. 1995, pp. 679–682.

[7] A. Bryant, W. Hansch, and T. Mii, “Characteristics of CMOS deviceisolation for the ULSI age,” inIEDM Tech. Dig., Dec. 1994, pp.671–674.

[8] C. Kaanta, S. Bombardier, W. Cote, W. Hill, G. Kerszykowski, H.Landis, D. Poindexter, C. Pollard, G. Ross, J. Ryan, S. Wolff, and J.Cronin, inVLSI Multilevel Interconnect Conf., June 1991, pp. 144–152.

[9] D. Ouma, B. Stine, R. Divecha, D. Boning, J. Chung, I. Ali, andM. Islamraja, “Using variation decomposition analysis to determinethe effects of process on wafer and die-level uniformities in CMP,”presented at1st Int. Symp. Chemical Mechanical Planarization (CMP)in IC Device Manufact., 190th Electrochem. Soc. Meeting, San Antonio,TX, Oct. 1996.

[10] M. Ichikawa, K. Inoue, K. Izumi, S. Sato, S. Mitarai, M. Kai, and K.Watanabe, “Multilevel interconnect system for 0.35-�m CMOS LSI’swith metal dummy planarization process and thin tungsten wirings,” inVLSI Multilevel Interconnect Conf., June 1995, pp. 254–260.

[11] B. Stine, D. Ouma, R. Divecha, D. S. Boning, J. Chung, D. Hetherington,C. R. Harwood, O. S. Nakagawa, and S.-Y. Oh, “Rapid characterizationand modeling of pattern dependent variation in chemical-mechanicalpolishing,” IEEE Trans. Semiconduct. Manufact., vol. 11, pp. 129–140,Feb. 1998.

[12] L. Camilletti, “Implementation of CMP-based design rules and pattern-ing practices,” inProc. IEEE/SEMI Adv. Semiconduct. Manufact. Conf.,Oct. 1995, pp. 2–4.

[13] B. Stine, D. Boning, J. Chung, L. Camilletti, E. Equi, S. Prasad, W. Loh,and A. Kapoor, “The role of dummy fill patterning practices on intradieILD thickness variation in CMP processes,” inProc. VLSI MultilevelInterconnect Conf., June 1996, pp. 421–423.

[14] B. Stine, D. Ouma, R. Divecha, D. Boning, J. Chung, D. Hetherington,I. Ali, G. Shinn, J. Clark, O. S. Nakagawa, and S.-Y. Oh, “A closed-form analytic model for ILD thickness variation in CMP processes,” inProc. CMP-MIC Conf., Santa Clara, CA, Feb. 1997, pp. 266–273.

[15] E. Chang, B. Stine, T. Maung, R. Divecha, D. Boning, J.Chung, K.Chang, G. Ray, D. Bradbury, O. S. Nakagawa, S. Oh, and D. Bartelink,“Using a statistical metrology framework to identify systematic andrandom sources of die- and wafer-level ILD thickness variation in CMPprocesses,” inIEDM Tech. Dig., Dec. 1995, pp. 499–502.

[16] R. Divecha, B. Stine, E. Chang, D. Ouma, D. Boning, J. Chung, O.Nakagawa, S. Oh, S. Prasad, W. Loh, and A. Kapoor, “Assessing andcharacterizing inter- and intradie variation using a statistical metrol-ogy framework: A CMP case study,” presented at1st Int. WorkshopStatistical Metrology, Honolulu, HI, June 1996.

[17] W. Maly, M. Patyra, A. Primatic, V. Raghavan, T. Storey, and A. Wolfe,“Memory chip for 24-port global register file,” inProc. IEEE CustomIntegrated Circuit Conf., May 1991, pp. 15.5.1–15.5.4.

[18] Raphael User’s Manual, Technology Modeling Associates, Sunnyvale,CA, ver. 3.2, 1995.

[19] K. Nabors and J. White, “FastCap: A multipole accelerated 3-D capac-itance extraction program,”IEEE Trans. Computer-Aided Design, vol.10, pp. 1447–1459, Nov. 1991.

Brian E. Stine received the B.S. degree (summa cum laude) and theM.S. degree in electrical engineering from the University of Pennsylvania,Philadelphia, and the Ph.D. degree in electrical engineering and computerscience from the Massachusetts Institute of Technology, Cambridge, in1997. His dissertation dealt with assessing and modeling spatial variation insemiconductor processes and with estimating the impact of spatial variationon circuit performance and product manufacturability. Most of this work wasfocused on chemical mechanical polishing (CMP) processes.

He is currently a Consultant with PDF Solutions, Inc., San Jose, CA.Dr. Stine is a member of Tau Beta Pi, Sigma Xi, and Eta Kappa Nu.

Duane S. Boning (S’83–M’89) received the B.S. degrees in electricalengineering and in computer science in 1984, and the M.S. and Ph.D.degrees in 1986 and 1991, respectively, all from Massachusetts Institute ofTechnology (MIT), Cambridge.

From 1991 to 1993, he was a Member of the Technical Staff at the TexasInstruments Semiconductor Process and Device Center, Dallas, TX, where heworked on process/device simulation tool integration, semiconductor processrepresentation, and statistical modeling and optimization. Currently, he isan Associate Professor in the Electrical Engineering and Computer ScienceDepartment at MIT. His research focuses on variation modeling and controlin semiconductor processes, with special emphasis on chemical-mechanicalpolishing and plasma etch. Additional interests include tools and frameworksfor process and device design, network technology for distributed design andfabrication, and computer integrated manufacturing.

Dr. Boning is an Associate Editor for the IEEE TRANSACTIONS ON

SEMICONDUCTOR MANUFACTURING, and a member of Eta Kappa Nu, TauBeta Pi, Sigma Xi, and the Association of Computing Machinery. He was anNSF Fellow from 1984 to 1989, and an Intel Graduate Fellow in 1990.


James E. Chungreceived the B.S. degree in electrical engineering from theUniversity of Illinois, Urbana, in 1984, and the M.S. and Ph.D. degrees inelectrical engineering from the University of California, Berkeley, in 1988and 1990, respectively.

He spent the fall of 1990 as a Visiting Researcher at the Motorola AdvancedProducts Research and Development Laboratory, Austin, TX. From 1991 to1994, he held the Analog Devices Career Development Chair. Since 1991,he has been a faculty member of the Massachussetts Institute of Technology,Cambridge, where he is currently an Associate Professor in the Departmentof Electrical Engineering and Computer Science and a member of the MITMicrosystems Technology Laboratories. His research interests are in theareas of MOSFET device physics, VLSI technology and manufacturing, SOImaterials and devices, and hot-electron and thin-dielectric reliability

Lawrence Camilletti, photograph and biography not available at the time ofpublication.

Frank Kruppa , photograph and biography not available at the time ofpublication.

Edward R. Equi, photograph and biography not available at the time ofpublication.

William Loh , photograph and biography not available at the time of publi-cation.

Sharad Prasad, photograph and biography not available at the time ofpublication.

Moorthy Muthukrishnan , photograph and biography not available at thetime of publication.

Daniel Towery, photograph and biography not available at the time ofpublication.

Michael Berman, photograph and biography not available at the time ofpublication.

Ashook Kapoor, photograph and biography not available at the time ofpublication.

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