Linear Technology Magazine • June 1991 7

A substantial percentage of DCregulator requirements involve reduc-tion or step down of a primary voltage.Linear regulators do this, but theydon’t achieve the efficiency of switch-ers. The theory supporting step downor “buck” switching regulation is wellestablished, and has been exploitedfor some time. However, convenientlyapplied ICs allowing practical imple-

mentations haven’t been available. Anew power IC device, the LT1074,permits broad application of step downregulators with minimal complexityand low cost. Further, more complexstep down regulator functions arepossible with it also.

The LT1074 is a 5A bipolar switch-ing regulator requiring minimal exter-nal parts for operation. While the block

diagram of Figure 1. reveals a complexdevice, basic operation is still fairlystraightforward. A description of themain circuit elements and their pinfunctions is as follows.

The LT1074 uses a special con-trolled saturation Darlington NPNoutput switch, with the emitter out-

The LT1074 Family of Step DownSwitching Regulators by Jim Williams

Figure 1. LT1074/LT1076 Block Diagram

continued on page 8

6V REGULATOR

AND BIAS

+

–

-POWER SHUTDOWNµ

10 Aµ 320 Aµ

+

–

2.35V

0.3V

CURRENT LIMIT

SHUTDOWN

4.5V 10k

S

+

–

CURRENT LIMIT COMP

C2

15400+

–

C1

+

–

SYNC

FREQ*

2.4V

R/S LATCH

COMOUT*

R

R

Q

X

Y

Z+

–

A1 ERROR

AMP

FB V

100kHz OSCILLATOR

ANALOG MULTIPLIER

XY Z

FREQ SHIFT

SYNC

SYNC FREQ BOOST

G1

PULSE WIDTH COMPARATOR

20V (EQUIVALENT)

2.21V

STATUS*

SWITCH OUTPUT (V )

0.035

250

100Ω

EXTLM*

INPUT SUPPLY

SHUTDOWN* I *

6V TO ALL CIRCUITRY

LIM

OUTPUT VOLTAGE MONITOR

Ω Ω

SW

Ω

VIN

C *AVAILABLE ONLY ON 11-PIN SIP PACKAGE

8 Linear Technology Magazine • June1991

When the LT1074 (internal) switchcloses, input voltage appears at theinductor, and current flowing throughthe inductor-capacitor combinationbuilds over time. When the switchopens, current flow ceases and themagnetic field around the inductorcollapses. Faraday teaches that thevoltage induced by the collapsing mag-netic field is opposite to the originallyapplied voltage. As such, the voltageat the inductor’s left end heads nega-tive, and is clamped by the diode. Thecharge accumulated on the capacitorhas no discharge path, leaving anoutput DC potential. This potential islower than the input, because theinductor limits current during theswitch on-time.

Ideally, there are no dissipativeelements in this voltage step downconversion. Although the output volt-age is lower than the input, there isno energy lost in this conversion. Inpractice, the circuit elements do havelosses, but step down efficiency isstill higher than with inherently dis-sipative (e.g. voltage divider) ap-proaches. In this circuit, feedback

controls the switch, to regulate out-put voltage. The switch on-time (e.g.inductor charge time) is varied tomaintain the output against changesin either input or loading.

With respect to a practical circuitusing the LT1074 regulator, some

put at pin VSW. This switch uses anisolated design, allowing voltageswings up to 40V below the groundpin. In addition, the switch also hasa continuous current monitor. Theoscillator of the LT1074 operates at100kHz, driving the switch through acontrol latch. Duty cycle controlcomes from a pulse width compara-tor, which in turn is driven by themain error amplifier through the ana-log multiplier. This multiplier allowsa loop gain independent of input volt-age, optimizing transient response.The error amp of the LT1074 com-pares a sample of the output pre-sented to the FB pin to an internal2.21V (±2.5%) reference. Loop com-pensation is accomplished by a simpleRC network at the amplifier output(VC pin), to ground.

While the above describes the ba-sic operational loop of the LT1074design, accessory internal functionsalso exist. These are ILIM, FREQ, STA-TUS, COMOUT, SHUTDOWN andEXTLIM pins (available only in the 11pin package). As alluded, there aremultiple power packagesused with the LT1074., a 4lead TO-3 (K), a 5 lead TO-220 (T), and the 11 lead SIPpackage (V), which permitsthe optional clock synchro-nization, micropower shut-down, current limit pro-gramming and other fea-tures. The LT1074 is avail-able in two basic voltagegrades, the LT1074 for45V(max) inputs, and theLT1074HV, usable to 64V.There is also a 2.5A rateddevice, the LT1076.

ApplicationsFigure 2 is a practical LT1074 volt-

age step down or “buck” circuit, us-ing minimum componentry. It closelyfollows a voltage step down concep-tual model, described as follows.

continued from page 7 additional new elements appear. TheRC components at the LT1074 VCpin provide frequency compensation,stabilizing the feedback loop. Outputsensing resistors R1/R2 are selectedto scale the output to the desiredvoltage VOUT, generally as noted inthe figure, with values shown in thiscase for 5V.

Performance wise, the circuit op-erates over an input range of 10-40V,and has a maximum output of 5A.Efficiency is about 80% at a currentof 1A, while output ripple is about25mV with the filtering as shown.With these and other switching regu-lators, power components are criticalto performance, and should be ratedfor switching use at the currentsanticipated.

Regulated negative outputs withthe LT1074 are easily obtained also,using a simple two terminal induc-tor. The basic positive to negativeconverter of Figure 3 demonstratesthis, essentially grounding the in-ductor, steering diode current to whatis now a negative output. This designaccomplishes the plus-to-minus DC

level shift by connecting theLT1074 GND pin direct tothe negative output, requir-ing an isolated heat sink.

Feedback is sensed fromthe grounded positive out-put terminal, and the regu-lator again forces its feed-back pin 2.21V above its GNDpin. Output voltage scalingis numerically as in Figure 2,with a negative sign. Circuitground is common to inputand output, making systemuse easy.

Overall performance is as noted,and is similar to the positive buckconverter of Figure 2, but with someunique distinctions. On the plus side,note that the input/output voltagesof this configuration are seen in se-

continued on page 9

+

R32k

R2**2.21k1%

C20.1 Fµ

MBR745R1 **2.8k1%

L150 Hµ

C3*100 Fµ

LT1074

VSW

FBVC

VIN

GND

V = 5V AT 5A

OUTV = 10V TO 40V

IN

+ C1500 Fµ

* OPTIONAL - USE IF CONVERTER IS MORE THAN 2" FROM RAW SUPPLY FILTER CAPACITOR PULSE ENGINEERING, INC. #PE-92114

+

A3 • F2

** V = + 1 * 2.21R1R2OUT ( )

Figure 2. LT1074 Step Down Regulator (5V output)

Linear Technology Magazine • June 1991 9

common. This option uses an op ampas a precision feedback level shifter.A1 facilitates loop closure, providinga scaled inversion of the negativeoutput to the LT1074 FB pin. Preci-sion resistors R1/R2 set negativeoutput voltage as noted (values shownfor a -5V output). The VC pin of theLT1074 is left open, and the RC net-work around A1 gives frequency com-pensation.

Advantages of this circuit com-pared to Fig. 3 is that the LT1074package can directly contact a

ries by the LT1074, as VIN. This hasthe effect of allowing a very low abso-lute level for the positive input, downto as low as 5V, making the circuit anefficient 5V to -5V power converter.On the down side, note in this in-stance the LT1074 control pins arefloating off ground, presenting somepotential problems with control in-terfacing (when necessary).

Figure 4, another variant, is usedwhen it is desirable to operate thecase (GND) pin of the regulator at

continued from page 8 grounded heat sink. Additionally, thiscircuit permits ground referred ad-dressing of the regulator’s controlpins. Disadvantages are that it re-quires a higher minimum input volt-age, plus an additional active device..

Higher Output Currentswith Tapped Inductors

Buck (step-down) convertors havea switch current at least as high asregulator output current. This limitsLT1074 output current to 5A in thesimple buck convertor topology. Aslightly modified version (shown onthe data sheet) can double availableoutput current to 10A when inputvoltage is a minimum of 20V. Themodified version uses a 3 to 1 tappedinductor which generates current gainin the inductor.

During switch “on” time currentflows through the entire inductor tothe output and can have a maximumvalue of 5A. When the switch turnsoff, the voltage at the tap flies nega-tive and current flows to the outputthrough just 1/4 of the inductor.Energy conservation requires thatthis current be four times the currentwhich was flowing in the entire in-ductor. Average current delivered tothe output is between 5A and 20A, asdetermined by operating switch dutycycle. For low input voltages, switchduty cycle is very high, and maxi-mum output current is only slightlyabove 5A. For input voltage above20V, duty cycle is low enough todeliver 10A output current.

The voltage on the LT1074 switchpin flies negative to about 17V duringswitch “off” time due to the trans-former action of the inductor. Leak-age inductance, however, wouldcause, at switch turn-off, the switchvoltage to briefly fly negative withoutlimit. Clamps are needed to protectthe LT1074.

Figure 4. Positive to Negative Converter with Op Amp Level Shift

1000µ

IN4148

L155 Hµ

LT1074

VSW

FBVC

VIN

L1 = PULSE ENGINEERING, INC. #PE-92116

A3 • F4* V = – 2.21R1

R2OUT ( )

LT1006

12V INPUT

4.7k0.33

R210k 1%

MBR745

V = –5VOUT

R1*22.6k1%

A1NC

12VINPUT +

+

–

*

GND

F

Fµ

Figure 3. Positive to Negative Converter

C3* 200

A3 • F3

Fµ

12V TO 40V

L1 22 Hµ

†

R1 2.80k

C1** 1000 Fµ

–5V 1.5A

††

R2 2.21kR3

*

**

†††

OPTIONAL – USE IF CONVERTER IS MORE THAN 2" FROM RAW SUPPLY FILTER CAPACITOR LOWER OUTPUT RIPPLE CAN BE OBTAINED BY PARALLELING SEVERAL LOWER VALUE CAPACITORS. AN OUTPUT FILTER OF 5µH, 100µF WILL GIVE 20:1 RIPPLE ATTENUATION WITH AN ESR OF 0.1Ω ON THE 100µF CAPACITOR PULSE ENGINEERING, INC. #PE-51590 MAXIMUM OUTPUT CURRENT IS 1.5A AT VIN = 5V 3A AT VIN = 15V AND 3.5A AT VIN = 30V

C2

D1 MBR745

GND FBC

VSW

V

VIN

+

+

LT1074

14 Linear Technology Magazine • June1991

Switching regulator post regula-tion, battery powered apparatus, andother applications often require lowVIN-VOUT, or dropout, linear regula-tors. For post regulators this is neededfor high efficiency. In battery circuitslifetime is significantly effected by regu-lator dropout. The LT1123, a new lowcost reference/control IC, is designedspecifically for cost-effective duty insuch applications. Used in conjunc-tion with a discrete PNP power tran-sistor, the 3 lead TO-92 unit allowsvery high performance positive legregulator designs. The IC contains a5V bandgap reference, error ampli-fier, NPN darlington driver, and cir-cuitry for current and thermal limit-ing.

A low dropout example is the simple5V circuit of Fig. 1, using the LT1123and an MJE1123 silicon PNP. In op-eration, the LT1123 sinks Q1 basecurrent through the DRIVE pin, toservo control the FB (feedback) pin to5V. R1 provides pull-up current toturn Q1 off, and R2 is a drive limiter.The 10µF output capacitor (Cout) pro-vides frequency compensation. TheLT1123 is designed to tolerate a widerange of capacitor ESR so that lowcost aluminum electrolytics can be beused for COUT. If the circuit is located

more than 6 inches from the inputsource, the optional 10µF input ca-pacitor (CIN) should be added.

Normally, such configurations re-quire external protection circuitry.Here, the MJE1123 has been coopera-tively designed by Motorola and LTCfor use with the LT1123. The device isspecified for saturation voltage forcurrents up to 4 amperes, with basedrive equal to the minimum LT1123drive current specification. In addi-tion, the MJE1123 is specified formin/max beta at high current. Be-cause of this factor and the definedLT1123 drive, simple current limitingis practical. In limit, excessive outputcurrent causes the LT1123 to drive Q1hard until the LT1123 current limits.Maximum circuit output current isthen a product the LT1123 currentand the beta of Q1. The foldback char-acteristic of the LT1123’s drive cur-rent combined with the MJE1123 betaand safe area characteristics providereliable short circuit limiting. Thermallimiting can also be accomplished, bymounting the active devices with goodthermal coupling.

Performance of the circuit is no-table, as it has lower dropout than anymonolithic regulator. Line and load

Figure 1. The LT1123 5V regulator features ultra-low dropout.

+

DRIVE

U1LT1123

FB

+

GND

C10 F

OUTµ

C10

INµ

R1600Ω

INPUT +5VOUT

* = OPTIONAL (SEE TEXT)MJE 1123 = MOTOROLA A8 • F1

Q1MJE1123

R220Ω

F

Figure 2. LT1123 regulator dropout voltagevs. output current

An LT1123 Ultra Low Dropout 5VRegulator Jim Williams and Dennis O'Neill

regulation are typically within 5 milli-volts, and initial accuracy is typicallyinside 1%. Additionally, the regulatoris fully short circuit protected, with ano load quiescent current of 1.3mA.

Figure 2 shows typical circuit drop-out characteristics, in comparison withother IC regulators. Even at 5A theLT1123/MJE1123 circuit dropout isless than 0.5V, decreasing to only50mV at 1A. Totally monolithic regu-lators cannot approach these figures,primarily because their power tran-sistors do not offer the MJE1123 com-bination of high beta and excellentsaturation. For example, dropout isten times lower than in 138 types, andsignificantly better than all the otherIC types. Because of Q1’s high beta,base drive loss is only 1-2% of outputcurrent even at high output currents.This maintains high efficiency underthe low VIN-VOUT conditions the circuitwill typically see. As an exercise, theMJE1123 was replaced with a 2N4276germanium device. This provided evenlower dropout performance, but limit-ing couldn't be production guaran-teed without screening.

OUTPUT CURRENT (A)

00

DROP

OUT

VOLT

AGE

(V)

0.5

1.0

1.5

2.0

2.5

3.0

1 2 5

A8 • F2

3 4

LT1123/MJE1123

LT1185

LT1084

LT138

LT1123/2N4276

Linear Technology Magazine • October 1991 17

DESIGN FEATURES

B = 5V/DIV

HORIZ = 100µs/DIVART ? • FIG 3

A = 500µV/DIV

10 SECONDS ART ? • FIG 2

50nV

+

–

100k

100kR1

R2Ω10

+

–

1k* 200*

450* 900*

+15

+15

–15

–15

0.02

A1 LTC1150

Q1, Q2 = 2x

2SK147 TOSHIBA

A2 LT1097

OPTIONAL OVER

COMPENSATION

OUTPUT

– INPUT

Q1

5

+ INPUT

* = 1% FILM RESISTOR750Ω*

10k

–15V

Q3 2N2907

Q2

Ultra-low Noise and Low DriftChopped-FET Amplifier

Figure 1’s circuit combines the ex-tremely low drift of a chopper-stabi-lized amplifier with a pair of low noiseFETs. The result is an amplifier with0.05µV/°C drift, offset within 5µV,100pA bias current and 50nV noise ina 0.1Hz–10Hz bandwidth. The noiseperformance is especially noteworthy;it is almost 35 times better than mono-lithic chopper-stabilized amplifiers.

FETs Q1 and Q2 differentially feedA2 to form a simple low-noise op amp.

Feedback, provided by R1 and R2, setsclosed-loop gain (in this case 10,000)in the usual fashion. Although Q1 andQ2 have extraordinarily low noise char-acteristics, their offset and drift areuncontrolled. A1, a chopper-stabilizedamplifier, corrects these deficiencies.It does this by measuring the differ-ence between the amplifier’s inputsand adjusting Q1’s channel currentvia Q3 to minimize the difference. Q1’sskewed drain values ensure that A1will be able to capture the offset. A1

and Q3 supply whatever current isrequired to force offset to within 5µVinto Q1’s channel. Additionally, A1’slow bias current does not appreciablyadd to the overall 100pA amplifier biascurrent. As shown, the amplifier is setup for a non-inverting gain of 10,000,although other gains and invertingoperation are possible. Figure 2 is aplot of the measured noise perfor-mance.

The FETs’ Vgs can vary over a 4:1range. Because of this, they must beselected for 10% Vgs matching. Thismatching allows A1 to capture theoffset without introducing any signifi-cant noise.

Figure 3 shows the response (traceB) to a 1mV input step (trace A). Theoutput is clean, with no overshoots oruncontrolled components. If A2 is re-placed with a faster device (e.g. LT1055)speed increases by an order of magni-tude with similar damping. A2’s op-tional overcompensation can be used(capacitor to ground) to optimize re-sponse for low closed loop gains.

by Jim Williams

Figure 1. Chopper Stabilized FET Pair Combines Low Bias, Offset and Drift with 45nV Noise

Figure 3. Step Response for the Low Noise +10,000Amplifier. A 10x Speed Increase is Obtainable by ReplacingA2 with a Faster Device

Figure 2. 45nV Noise Performance for Figure 1. A1’s Low Offset andDrift are Retained, but Noise is Almost 35 Times Better

DESIGN IDEAS

16 Linear Technology Magazine • October 1991

DESIGN FEATURES

+

–A3

LT1006

ART. ?, FIG. ?

+

–

A2 CFA

1/2 LT1228

100Ω

10kRF INPUT 0.6VRMS-1.3VRMS

25MHz

300Ω

–15V

+15V

+

–

A1 OTA

1/2 LT1228

470Ω

10Ω

0.01

10k

0.01

+15V

–15V

4pF

10k

100k

AMPLITUDE ADJUST

10k 4.7k–15V

LT1004 1.2V

10k

OUTPUT 2Vp-p

1N4148’s COUPLE THERMALLY

ISET

nents, including the inductor, are sur-face mount devices. The SHUTDOWNinput turns off the converter, reduc-ing quiescent current to 300µA when

Flash memory chips such as theIntel 28F020 2Megabit device requirea Vpp program supply of 12 volts at30mA. A DC–DC converter may beused to generate 12 volts from the 5volt logic supply. The converter mustbe physically small, available in sur-face-mount packaging, and have logic-controlled shutdown. Additionally, theconverter must have carefully con-trolled rise time and zero overshoot.Vpp excursions beyond 14 volts for20ns or longer will destroy the ETOX1-process based device.

Figure 1’s circuit is well suited forproviding Vpp power for a single flashmemory chip. All associated compo-

L1 47 H

ART ? • FIG 1

µ

+

GND

SWSENSE

LT1109CS8-12

10 Fµ

V 12V 50mA

OUT

MBRL120

INVIN+V 5V

SHUTDOWN PROGRAM

SHUTDOWN*

* 8-PIN PACKAGE ONLY L1 = ISI LCS2414 OR TDK NLC2220-470K

Figure 1. All Surface Mount Flash MemoryVpp Generator

The RF input is applied to A1, anLT1228 operational transconduc-tance amplifier. A1’s output feeds A2,the LT1228’s current-feedback am-

plifier. A2’s output, the output of thecircuit, is sampled by the A3-basedgain control configuration. This ar-rangement closes a gain-control loopback at A1. The 4pF capacitor com-pensates rectifier diode capacitance,enhancing output flatness vs fre-quency. A1’s ISET input current con-trols its gain, allowing overall outputlevel control. This approach to RFleveling is simple and inexpensive,and provides low output drift anddistortion.

by Jim Williams

by Steve Pietkiewicz

Leveling loops are often a require-ment for RF transmission systems.More often than not, low cost is moreimportant than absolute accuracy.Figure 1 shows such a circuit.

RF Leveling Loop

Figure 1. Simple RF Leveling Loop

LT1109 Generates Vpp for FlashMemory

DESIGN IDEAS

pulled to a logic 0. Vpp rises in acontrolled fashion, reaching 12 volts±5% in under 4ms. Output voltagegoes to Vcc minus a diode drop whenthe converter is in shutdown mode.This is an acceptable condition forIntel flash memories and does notharm the memory.

1ETOX is a trademark of Intel Corporation.

DESIGN FEATURES

Linear Technology Magazine • June 1992 3

Illumination Circuitryfor Liquid Crystal Displays

Current-generation portable com-puters and instruments employback-lit liquid crystal displays (LCDs).Cold-cathode fluorescent lamps(CCFLs) provide the highest availableefficiency for backlighting the display.These lamps operate on high-voltageAC and therefore require efficient high-voltage DC-AC converters. In additionto providing high efficiency, convert-ers used with CCFLs should deliverthe lamp drive in the form of a sinewave. This is desirable to minimize RFemissions, which can cause interfer-ence with other devices and degradeoverall operating efficiency. The cir-cuit should also permit lamp-inten-sity control from zero to full brightnesswith no hysteresis or “pop-on.”

The LCD also requires a bias supplyfor contrast control. The supply’s nega-tive output should be regulated andshould be variable over a considerablerange.

Because of their small size andbattery-powered operation, LCD-equipped devices require low compo-nent count and high efficiency. Sizeconstraints place severe limitationson circuit architecture, and long bat-tery life is usually a priority. Laptopand hand-held portable computersare excellent examples. In these appli-cations, the CCFL and its power sup-ply are responsible for almost 50% ofthe battery drain. Additionally, thesecomponents, including the PC boardand all hardware, must usually fitwithin the LCD enclosure, with a heightrestriction of 0.25".

CCFL Power SuppliesAny discussion of CCFL power

supplies must consider lamp charac-teristics. These lamps are difficult loadsto drive, particularly for a switchingregulator. They have a “negative re-sistance” characteristic; the startingvoltage is significantly higher than theoperating voltage. Typically, the start-ing voltage is about 600 volts, althoughhigher and lower voltage bulbs arecommon. Operating voltage is usually300–400 volts, although other bulbsmay require different potentials. Bulbsize or length does not necessarilycorrelate to break-down voltage. Thebulbs will operate from DC, but migra-tion effects within the bulb will quicklydamage it. Hence, the waveform mustbe AC with no DC content.

Bulb operating frequencies aretypically 20 to 100kHz, and asine-like waveform is preferred. Thesine-like drive has low harmoniccontent, which minimizes RF emis-sions that can cause interference andefficiency degradation.

Figure 1’s circuit meets CCFL-driverequirements. Efficiency can be ashigh as 78% with an input voltagerange of 4.5V–20V. 82% efficiency ispossible if the LT1172 is driven from alow voltage (3–5V) source. Addition-ally, lamp intensity is continuouslyand smoothly variable from zero to full

Figure 2. CCFL power supply waveformsFigure 1. Cold-cathode fluorescent lamp power supply

by Jim Williams

A = 20V/DIV

B = 0.4V/DIV

C = 20V/DIV

D = 20V/DIV

E = 1000V/DIV

F = 5V/DIV

A AND B HORIZ = 10µs/DIVC THRU F HORIZ = 20µs/DIV

TRIGGERS FULLY INDEPENDENT

+

+

D2 1N4148

Q2 MPS650

1N5818

D1 1N4148

+

50kΩ INTENSITY

ADJUST

562Ω

10kΩ

1kΩ

LAMPC2 15pF 3kV 9 7

43215

Q1 MPS650

10µF

C1 0.02µF

+VIN

+VIN 4.5V TO +20V

VIN

VSW

VFB

VCGND

E2

E1

LT1172

5

7

3

2µF

1

8

6

2

1µF

L2 300µH

L1

CCFL_1.epsC1 = MUST BE A LOW LOSS CAPACITOR. METALIZED POLYCARB WIMA FKP2 (GERMAN) RECOMMENDED.L1 = SUMIDA-6345-020 OR COILTRONICS-CTX110092-1. PIN NUMBERS SHOWN FOR COILTRONICS UNITL2 = COILTRONICS-CTX300-4

Q1, Q2 = AS SHOWN OR BCP 56 (PHILIPS SO PACKAGE) DO NOT SUBSTITUTE COMPONENTS

SUMIDA (708) 956-0666 COILTRONICS (305) 781-8900

4 Linear Technology Magazine • June 1992

DESIGN FEATURES

intensity. When power is applied, theLT1172 switching regulator’s feedbackpin is below the device’s internal 1.23Vreference, resulting in full duty-cyclemodulation at the VSW pin (trace A,Figure 2). L2 conducts current (traceB), which flows from L1’s center tap,through the transistors, into L2. L2’scurrent is deposited in switched fash-ion to ground by the regulator’s action.

L1 and the transistors comprise acurrent-driven, Royer-class converter,which oscillates at a frequency deter-mined primarily by L1’s characteris-tics (including its load) and the 0.02µFcapacitor. LT1172 driven L2 sets themagnitude of the Q1–Q2 tail current,and hence L1’s drive level. The 1N5818diode maintains L2’s current flow whenthe LT1172 is off. The LT1172’s 100kHzclock rate is asynchronous with re-spect to the push-pull converter’s(60kHz) rate, accounting for trace B’swaveform thickening.

The 0.02µF capacitor combines withL1’s characteristics to produce sinewave voltage drive at the Q1 and Q2collectors (traces C and D, respec-tively). L1 furnishes voltage step-up,and about 1400VP–P appears at itssecondary (trace E). Current flowsthrough the 15pF capacitor into the

lamp. On negative waveform cycles,the lamp’s current is steered to groundvia D1. Positive waveform cycles aredirected, via D2, to the ground referred562Ω–50kΩ potentiometer chain. Thepositive half-sine appearing acrossthese resistors (trace F) represents 1/2the lamp current. This signal is filteredby the 10kΩ-1µF pair and presented tothe LT1172’s feedback pin. This con-nection closes a control loop whichregulates lamp current. The 2µF ca-pacitor at the LT1172’s VC pin providesstable loop compensation. The loopforces the LT1172 to switch-modemodulate L2’s average current to what-ever value is required to maintain aconstant current in the lamp. Theconstant current’s value, and hencelamp intensity, can be varied with thepotentiometer. The constant currentdrive allows full 0–100% intensity con-trol with no lamp dead zones or “pop-on” at low intensities. Additionally,lamp life is enhanced because currentcannot increase as the lamp ages.

Several points should be kept inmind when observing this circuit’soperation. L1’s high-voltage second-ary can only be monitored with a wide-band, high voltage probe fully specifiedfor this type of measurement. The vast

A Related Circuit:Helium Neon Laser Driver

The high-voltage-compliancecurrent-loop approach of the CCFLpower supply is suitable for otherapplications as well. Current sens-ing permits precise, high-efficiencycontrol of a wide variety of difficultloads. A HeNe laser is such a load.Lasers are negative impedances op-erating at very high voltages. Typi-cally, they require from 6 to 10kV tostart, with an operating voltage inthe 1 to 3kV range. Simple high-voltage drive does not provide this.The circuit in Figure A1 adapts theCCFL circuitry to control a laser.Both tube-current stability and elec-trical efficiency are improvedover the more conventional voltage-mode drive.

Q1 and Q2 combine with L2 toform a self-oscillating DC-DC con-verter. No resonating capacitor isused in this design. The DC-DC con-verter operates in square-wave mode,although resonant operation couldbe used to minimize harmonics. Theconverter’s high-voltage output ismultiplied by the D1-D2 voltage dou-bler and applied to the laser via the50kΩ ballast resistor. This resistoris required to isolate the laser fromthe 0.1µF output capacitor. Lasercurrent flow is converted to a voltageby the 340Ω shunt and is fed back tothe LT1074 step-down switchingregulator. D3, L1, and C1 smooththe LT1074’s pulsed output to DCand drive the DC-DC converter. Thiscompletes a loop that controls thelaser current. The components atthe LT1074’s VC pin stabilize theloop. The frequency compensation isarranged so transients (e.g., turn-on) will not cause a brief lowering ofthe tube current. Such an event willcause laser impedance to rise dra-matically, extinguishing the laser.

L2 and the voltage doubler sup-ply a maximum of about 3.5kV, notenough to start laser conduction.A1, L3, and associated componentsprovide a high voltage start-up.

continued on page 7Figure A1. Laser-driver power supply

Q2 D45

0.17 8

32146

Q1 D45

VIN

VSW

FB

VCGND

LT1074

L2

LASER = HUGHES 3121

+ C1 470µF

5

0.1µF+28V

47Ω

–

+

–

+

C2 2µF 300V

Z1 250V

10M

61.9k

1k

10M

LT1004 1.2V

340Ω

50k 5W

L1 = PE92108 – PULSE ENG.L2 = PE6197 – PULSE ENG.L3 = TRIAD PL-11Z1 = MOTOROLA 1.5KE-250

D1,D2 = SEMTECH SH-100

+28V

D3 MUR415

L1 100µH +28V

10k 100k

1N914 1N914

1N914+28V

A1 LT1018

C106

IK = 6.5mA

2k

D2 0.1µF

D1

L3

START RING

CCFL_A1.eps

2k

0.01µF

LASER

Q1,Q2 = MOTOROLA D45H11 OR EQUIVALENT

PULSE ENGINEERING (619) 268-2400

NOTE: THE START RING IS A RING OF WIRE AROUND THE LASER TUBE

DESIGN FEATURES

Linear Technology Magazine • June 1992 5

majority of oscilloscope probes willbreak down and fail if used for thismeasurement.1 Tektronix type P-6009(acceptable) or types P6013A andP6015 (preferred) probes must be usedto read L1’s output.

Another consideration involves ob-serving waveforms. The LT1172’sswitching frequency is completelyasynchronous from the Q1–Q2 Royerconverter’s switching. As such, mostoscilloscopes cannot simultaneouslytrigger and display all the circuit’swaveforms. Figure 2 was obtained us-ing a dual-beam oscilloscope (Tektronix556). LT1172-related traces A and Bare triggered on one beam, while theremaining traces are triggered on theother beam. Single-beam instrumentswith alternate sweep and trigger switch-ing (e.g., Tektronix 547) can also beused, but are less versatile and arerestricted to four traces.

Obtaining and verifying high effi-ciency requires some diligence.2 Theoptimum efficiency values given forC1 and C2 are typical, and will varyfor specific types of lamps. C1 setsthe circuit’s resonance point, whichvaries to some extent with the lamp’scharacteristic. C2 ballasts the lamp,effectively buffering its negative-resis-tance characteristic. Small values ofC2 provide the most load isolation, butrequire relatively large transformer out-put voltage for loop closure. Large C2values minimize transformer outputvoltage, but degrade load buffering.Also, C1’s “best” value depends some-what on the type of lamp used. BothC1 and C2 must be selected for givenlamp types. Some interaction occurs,but general guidelines are possible.

Typical values for C1 are 0.01 to0.047µF. C2 usually ends up in the10pF–47pF range. C1 must be a low-loss capacitor; substitution for theWIMA device is not recommended. Apoor-quality dielectric for C1 can eas-ily degrade efficiency by 10%. C1 andC2 are selected by trying different val-ues for each and iterating towardsminimum supply input current. Dur-ing this procedure, ensure that loopclosure is maintained by monitoringthe LT1172’s feedback pin, whichshould be at 1.23 volts. Several trialsusually produce the optimum C1 andC2 values. Note that the highest effi-ciencies are not necessarily associatedwith the most aesthetically pleasingwaveshapes, particularly at Q1, Q2,and the output.

Other issues influencing efficiencyinclude bulb wire length and energyleakage from the bulb. The high-volt-age side of the bulb should have thesmallest practical lead length. Exces-sive length results in radiative losses,which can easily reach 3% for a three-inch wire. Similarly, no metal shouldcontact or be in close proximity tothe bulb. This prevents energy leak-age, which can exceed 10%. (Theseconsiderations should be made withknowledge of other LCD issues. SeeAppendix B of AN49, “MechanicalDesign Considerations for LiquidCrystal Displays.”)

Special attention should be givento the layout of the circuit board,since high voltage is generated atthe output. The output couplingcapacitor must becarefully located tominimize leakagepaths on the circuitboard. A slot in theboard will furtherminimize leakage.Such leakage can per-mit current flowoutside the feedbackloop, wasting power.In the worst case, longterm contaminationbuild-up can increaseleakage inside theloop, resulting instarved lamp drive or

destructive arcing. To minimize leak-age, it is good practice to break thesilk-screen line which outlines trans-former T1. This prevents leakage fromthe high voltage secondary to theprimary. Another technique for mini-mizing leakage is to evaluate andspecify the silk-screen ink for its abil-ity to withstand high voltages.

Once these procedures have beenfollowed, efficiency can be measured.Efficiency may be measured by de-termining bulb current and voltage.Measuring current involves measur-ing RMS voltage across the 562Ωresistor (short the potentiometer). Thebulb current is

IBULB = (E/R) x 2

Multiplication by two is necessarybecause the diode steering dumps thecurrent to ground on negative cycles.Bulb RMS voltage is measured at thebulb with a properly compensated high-voltage probe. Multiplying these tworesults gives power in watts, whichmay be compared to the DC-input-supply E x I product. In practice, thelamp’s current and voltage contain

+

D2 1N4148

Q2 MPS650

1N5818

D1 1N4148

INTENSITY

ADJUST 1M

3.3k

1M

330Ω

LAMP

15pF 3kV 9 7

43215

Q1 MPS650

10µF

C1 0.01µF

+VIN

+VIN 2V TO 6V

VIN

SW1

FB

GNDSW2

SET

AO

LT1173

NC

0.01µF

L2 82µH

L1

CCFL_4.eps

C1 = MUST BE A LOW LOSS CAPACITOR. METALIZED POLYCARB WIMA FKP2 (GERMAN) RECOMMENDED.L1 = SUMIDA-6345-020 OR COILTRONICS-CTX110092-1. PIN NUMBERS SHOWN FOR COILTRONICS UNIT L2 = TOKO 262LYF-0091K DO NOT SUBSTITUTE COMPONENTS

1N5818

NC

ILIM

47Ω

1N4148

SHUTDOWN

Figure 3. Separate ballast capacitors allowone transformer to drive two tubes

CCFL_3.eps

BALLAST CAPACITORS CCFLs

TO D1, D2 JUNCTION

COILTRONICS CTX110459-1

TO DRIVE CIRCUITRY

Figure 4. Low-current CCFL power supply

6 Linear Technology Magazine • June 1992

DESIGN FEATURES

+

3V 2 AA CELL

R1 100

OPERATE SHUTDOWN

* TOKO 262LYF-0092K

D4 1N4148 C3

22µF

R2 120k

R4 2.21M

C1 0.1µF

C2 4.7µF

D3 1N5818

D2 1N5818

OUTPUT –12V TO –24V

L1* 100 Hµ

CCFL_6.eps

U1 LT1173

ILIM VIN

SW1

FBSW2GND

×

D1 1N5818

R3 100k

+

AN49, “Achieving Meaningful Effi-ciency Measurements.”

Two-Tube DesignsSome displays require two tubes

instead of the more popular single-tube approach. These two-tube designsusually require more power. Accom-modating two tubes involves separateballast capacitors (see Figure 3), butcircuit operation is similar. Higherpower may require a different trans-former rating. Figure 1’s transformercan supply 7.5mA, although morecurrent is possible with appropriatetransformer types. For reference, an11mA-capability transformer appearsin Figure 3.

Low-Power CCFL SupplyFigure 4 represents the other ex-

treme. This design is optimized forsingle-tube operation at very low cur-rents. Figure 1’s circuit typically drives5mA maximum, but this design topsout at 1mA. This circuit maintainscontrol down to tube currents of 1µA,a very dim light. It is intended for ap-plications where the longest possiblebattery life is desired. Maintaininghigh efficiency at low tube currentsrequires modifying the basic design.

Achieving high efficiency at lowoperating currents requires loweringFigure 1’s quiescent power drain. Todo this, the LT1172, a pulse-width-modulator-based device, is replaced

with an LT1173. The LT1173 is aburst-mode-type regulator. When thisdevice’s feedback pin is too low, itdelivers a burst of output currentpulses, putting energy into the trans-former and restor-ing the feedbackpoint. The regulator maintains controlby appropriately modulating the burstduty cycle. The ground-referred diodeat the SW1 pin prevents substrateturn-on due to excessive L2 under-shoot. During the off periods, the regu-lator is essentially shut down. Thistype of operation limits available out-put power, but cuts quiescent currentlosses. In contrast, Figure 1’s LT1172pulse-width-modulator-type regulatormaintains “housekeeping” current be-tween cycles. This results in moreavailable output power but higher qui-escent currents. Figure 5 shows oper-ating waveforms for the circuit in Figure4. When the regulator comes on (traceA) it delivers bursts of output currentto the L1–Q1–Q2 high-voltage con-verter. The converter responds withbursts of ringing at its resonant fre-quency. The circuit’s loop operation issimilar to that of Figure 1.3

LCD Bias SuppliesLCDs also require a bias supply for

contrast control. The supply’s variablenegative output permits adjustmentof display contrast. Relatively littlepower is involved, easing RF radiationand efficiency requirements. The logicsections of display drivers operate fromsingle 5V supplies, but the actual driveroutputs swing between +5V and anegative bias potential. Varying thisbias varies the contrast of the display.

An LCD bias generator, developedby Steve Pietkiewicz of LTC, is shownin Figure 6. In this circuit U1 is anLT1173 micropower DC-DC converter.The 3V input is converted to +24V byU1’s switch, L1, D1, and C1. Theswitch pin (SW1) then drives a chargepump composed of C2, C3, D2, and D3to generate –24V. Line regulation isless than 0.2% from 3.3V to 2.0Vinputs. Although load regulation suf-fers somewhat because the –24V out-put is not directly regulated, it stillmeasures 2% from a 1mA to 7mA load.

Figure 5. Low-current CCFL power-supplywaveforms

Figure 6. LCD bias generator (3V to -12 to -24V)

small out-of-phase components, buttheir error contribution is negligible.

Both the current and voltage mea-surements require a wide-band true-RMS voltmeter. The meter must employa thermal-type RMS converter—themore common logarithmic-computingtype instruments are inappropriatebecause their bandwidths are too low.(See AN49 for a discussion of the op-erational theory and limitations of vari-ous AC voltmeters.)

The previously recommended highvoltage probes are designed to see a1MΩ, 15–22pF oscilloscope input. TheRMS voltmeters have a 10MΩ input.This difference necessitates an im-pedance matching network betweenthe probe and the voltmeter. Detailsof this and other efficiency measure-ment issues appear in Appendix C of

A = 5V/DIV

B = 5V/DIV

50µs/DIV

DESIGN FEATURES

Linear Technology Magazine • June 1992 7

L1 = SUMIDA CD75-470M C1, C2 = TANTALUM CCFL_7.eps

LT1172

VC

VIN

FB

GND

VSW

+D1 1N914

R3 15kΩ

C5 2µF

D2 1N5817

VIN = 5V

VBATT = 3V TO VOUT + 1V

R2 100kΩ

R1 200kΩ

+ C1 2µF

VOUT = –10V TO –30V

C2 4.7µF

D3 1N5817

C3 4.7nFC4

4.7nFQ1 VN2222LL

L1 47µH

OPTIONAL SHUTDOWN

+

The circuit will deliver 7mA from a2.0V input at 75% efficiency.

If greater output power is required,Figure 6’s circuit can be driven from a+5V source. R1 should be changed to47Ω and C3 to 47µF. With a 5V input,40mA is available at 75% efficiency.Shutdown is accomplished by bring-ing the anode of D4 to a logic high,forcing the feedback pin of U1 to goabove the internal 1.25V referencevoltage. Shutdown current is 110µAfrom the input source and 36µA fromthe shutdown signal.

Another interesting modification ofa boost converter that can providenegative bias from a 5V supply is shownin Figure 7. The converter, developedby Jon Dutra of LTC, is half switcherand half charge pump. The chargepump (C1, C2, D2, and D3) is driven bythe flying node at VSW. The output isvariable from –10 to –30V, providingcontrast control for the display.

On low-voltage supplies (6V or less)VIN and VBATT can be tied together.With higher battery voltages, high effi-ciency is obtained by running theLT1172 VIN pin from 5V. Shutting offthe 5V supply will automatically turnoff the LT1172. The maximum valuefor VBATT is equal to the negative out-put plus 1V. Also, the difference be-tween VBATT and VIN must not exceed16V. R1, R2, and R3 are made large tominimize battery drain in shutdown,since they are permanently connectedto the battery via L1 and D1. Efficiencyis about 80% at IOUT = 25mA.

When power is applied, laser currentis zero and A1’s output goes toground. The high-voltage convertersupplies full output ( 3.5kV), but thelaser does not start. Under theseconditions, the C106 SCR is off andC2 charges. A divided-down portionof C2’s voltage biases A1’s positiveinput. When C2 reaches about 200V,A1’s output goes high, triggering theSCR. This dumps C2’s chargethrough L3 to ground. L3’s output, avery-high-voltage spike, ionizes the

laser, driving it into conduction. La-ser impedance drops and the maincurrent control loop begins be-having as described above. Thepresence of voltage across the 340Ωshunt causes A1’s output to go low,preventing further SCR conduction.Zener clamp Z1 limits C2’s voltageunder these conditions. If the laserfails to start, the cycle will repeatuntil start-up occurs. Electrical effi-ciency for this circuit is about 75%for inputs from 22 to 35V.

Laser Driver, continued from page 4

3 The discontinuous energy delivery to the loopcauses substantial jitter in the burst-repetitionrate, although the high-voltage section maintainsresonance. Unfortunately, circuit operation is in the“chop” region of most oscilloscopes, precluding adetailed display. “Alternate” operation causes wave-form-phasing errors, also producing an inaccuratedisplay. Hence, waveform observation requires spe-cial techniques. Figure 5 was taken with a dual-beam instrument (Tektronix 556) with both beamsslaved to one time base. Single-sweep triggeringeliminated jitter artifacts. Most 'scopes, whetheranalog or digital, will have trouble reproducing thisdisplay.

1 Don’t say we didn’t warn you!

2 The term “efficiency” as used here refers to electri-cal efficiency. In fact, the ultimate concern centersaround the efficient conversion of power-supplyenergy into light. Unfortunately, lamp types showconsiderable variation in their current-to-light con-version efficiency. Similarly, the emitted light for agiven current varies over the life of any particularlamp. Hence, this article treats “efficiency” on anelectrical basis: as the ratio of power removed fromthe primary supply to the power delivered to thelamp. When a lamp has been selected, this ratio canbe measured with a photometer.

Figure 7. 5V LCD bias generator (5V to -10 to -30V)

This article was extracted from LTCApplication Note 49 available inAugust. For more details, andadditional information, please requestAN49 on the response card or call the800 number listed on the last page ofthis magazine.

Linear Technology Magazine • February 1993 17

DESIGN IDEAS

Some 1.5V powered systems, suchas two-way survival radios, remote,transducer-fed data-acquisition sys-tems, and the like, require much morepower than stand-alone IC regulatorscan provide. Figure 1’s design suppliesa 5V output with 200mA capacity.

The circuit is essentially a flybackregulator. The LT1170 switchingregulator’s low saturation losses andease of use permit high power opera-tion and design simplicity. Unfortu-nately this device has a 3V minimumsupply requirement. Bootstrapping itssupply pin from the 5V output is pos-sible, but requires some form of start-up mechanism. The 1.5V poweredLT1073 switching regulator forms astart-up loop. When power is applied,the LT1073 starts, causing its VSW pinto periodically pull current through L1.L1 responds with high-voltage flybackpulses. These pulses are rectified and

200mA Output, 1.5V-to-5V Converterby Jim Williams

stored in the 500µF capacitor, produc-ing the circuit’s DC output. The out-put-divider string is set up so theLT1073 turns off when the circuit’soutput crosses about 4.5V. Under theseconditions the LT1073 can no longerdrive L1, but the LT1170 can. Whenthe start-up circuit turns off, theLT1170 VIN pin has adequate supplyvoltage and it can operate. There issome overlap between start-up loopturn-off and LT1170 turn-on, but thishas no detrimental effect. The start-uploop must function over a wide range ofloads and battery voltages. Start-upcurrents are about 1 ampere, necessi-tating attention to the LT1073’s satu-ration and drive characteristics. Theworst case is a nearly depleted batteryand heavy output loading. Figure 2plots input/output characteristics forthe circuit. Note that the circuit willstart into all loads with VBATT = 1.2V.

Start-up is possible down to 1.0V atreduced loads. Once the circuit hasstarted, the plot shows it will drive full200mA loads down to VBATT = 0.6V (avery dead battery). Figure 3 graphsefficiency at two supply voltages over arange of output currents. Performanceis attractive, although at lower cur-rents circuit quiescent power degradesefficiency. Fixed junction saturationlosses are responsible for lower overallefficiency at the lower supply voltage.

References

1. Williams, Jim and Brian Huffman. “Some Thoughtson DC–DC converters”, pages 13–17, “1.5V to 5VConverters.” Linear Technology Corporation Appli-cation Note 29, October 1988.

OUTPUT CURRENT (mA)

00

EFFI

CIEN

CY (%

)

10

60

100

40 100 180

CELL_3.eps

20 60 80 120 140 200160

80

50

40

20

VIN = 1.2V

90

70

30

VIN = 1.5V

VOUT = 5.0V

OUTPUT CURRENT (mA)

00

MIN

IMU

M IN

PUT

VOLT

AGE

TO M

AIN

TAIN

VO

UT

= 5.

0V

0.2

1.0

1.4

40 100 180 220

CELL_2.eps

20 60 80 120 140 200160

1.2

0.8

0.6

0.4

START

RUN

VIN SW1

SW2

500µF

1N5823

LT1073

L1 = * =

COILTRONICS CTX20-5-52, COILTRONICS (305) 781-8900 1% METAL FILM RESISTOR

+

CELL_1.eps

22µF+

6.8µF

VC

VIN

GND

LT1170

+

GND

FB

1k

220µFL1 20µH

1.5VIN

5VOUT

3.74k*

FB

1k*

240Ω*

VSW

+

Figure 1. 200mA output, 1.5V-to-5V converterFigure 3. Efficiency versus operating pointfor Figure 1

Figure 2. Input/output data for Figure 1

Linear Technology Magazine • February 1993 13

DESIGN IDEAS

Helium-neon lasers, used for a vari-ety of tasks, are difficult loads for apower supply. They typically need al-most 10 kilovolts to start conduction,although they require about 1500 voltsto maintain conduction at their speci-fied operating currents. Powering alaser usually involves some form ofstart-up circuitry to generate the initialbreakdown voltage and a separate sup-ply for sustaining conduction. Figure1’s circuit considerably simplifies driv-ing the laser. The start-up and sus-taining functions have been combinedinto a single, closed-loop current sourcewith over 10 kilovolts of compliance.When power is applied, the laser doesnot conduct and the voltage across the190Ω resistor is zero. The LT1170switching regulator FB pin sees nofeedback voltage, and its switch pin

A Simple, Efficient Laser Power Supplyby Jim Williams

loop. The LT1170 adjusts its pulse-width drive to L2 to maintain the FB pinat 1.23 volts, regardless of changes inoperating conditions. Hence, the lasersees constant current drive, in thiscase 6.5mA. Other currents are obtain-able by varying the 190Ω value. TheIN4002 diode string clamps excessivevoltages when laser conduction firstbegins, protecting the LT1170. The 10µFcapacitor at the VC pin frequency com-pensates the loop and the MUR405maintains L1’s current flow when theLT1170 VSW pin is not conducting. Thecircuit will start and run the laser over a9–35 volt input range with an electricalefficiency of about 75%.

References

1. Williams, Jim. “Illumination Circuitry for LiquidCrystal Displays” Linear Technology ApplicationNote 49, August 1992.

(VSW) provides full duty cycle pulse-width modulation to L2. Current flowsfrom L1’s center tap through Q1 andQ2 into L2 and the LT1170. This cur-rent flow causes Q1 and Q2 to switch,alternately driving L1. The 0.47µF ca-pacitor resonates with L1, providing aboosted, sine-wave drive. L1 providessubstantial step-up, causing about3500 volts to appear at its secondary.The capacitors and diodes associatedwith L1’s secondary form a voltagetripler, producing over 10 kilovoltsacross the laser. The laser breaks downand current begins to flow through it.The 47kΩ resistor limits current andisolates the laser’s load characteristic.The current flow causes a voltage toappear across the 190Ω resistor. Afiltered version of this voltage appearsat the LT1170 FB pin, closing a control

LASER

190Ω 1%

1N4002 (ALL)

0.1µF

10k

VIN

10µF

VC

VIN FB

GND

2.2µF

VIN 9V TO 35V

150ΩMUR405 L2

150µH

LT1170

L1

5 4 1 32

811 HV DIODES

1800pF 10kV

0.01 5kV

1800pF 10kV

47k 5W

2.2µF

0.47µF

HV DIODES = 0.47µF = Q1, Q2 =

L1 = L2 =

LASER =

SEMTECH-FM-50 WIMA 3X 0.15µF TYPE MKP-20 ZETEX ZTX-849 COILTRONICS CTX02-11128 COILTRONICS CTX150-3-52, COILTRONICS (305) 781-8900 HUGHES 3121H-P

+

+

10k

Q1 Q2

LASER_1.eps

VSW

+

Figure 1. Laser power supply

20 Linear Technology Magazine • June 1993

DESIGN IDEAS

Noise Generators for Multiple UsesA BroadbandRandom Noise Generator

by Jim WilliamsFilter, audio, and RF-communica-

tions testing often require a randomnoise source. Figure 1’s circuit pro-vides an RMS-amplitude regulatednoise source with selectable band-width. RMS output is 300 millivolts,with a 1kHz to 5MHz bandwidth,selectable in decade ranges.

Noise source D1 is AC coupledto A2, which provides a broadbandgain of 100. A2’s output feeds a gain-control stage via a simple, selectablelowpass filter. The filter’s output isapplied to A3, an LT1228 operationaltransconductance amplifier. A1’soutput feeds LT1228 A4, a current-

A Diode Noise Generatorfor “Eye Diagram” Testing

by Richard MarkellThe circuit that Jim Williams de-

scribes evolved from my desire tobuild a circuit for testing communi-cations channels by means of “eyediagrams.” (See Linear Technology,Volume I, Number 2 for a shortexplanation of the eye diagram.) Iwanted to replace my pseudo-ran-dom code generator circuit, whichused a PROM, with a more “analog”design—one that more people couldbuild without specialized compo-nents. What evolved was a noisesource sampled by a very fast com-parator (see Figure 5). The compara-tor outputs a random pattern of 1’sand 0’s.

The noise diode (an NC201) is fil-tered and amplified by the LT1190high-speed operational amplifier (U1).The output feeds the LT1116 (U2), a12ns, single-supply, ground-sensingcomparator. The 2kΩ pot at the in-verting input of the LT1116 sets thethreshold to the comparator so that aquasi-equal number of 1’s and 0’s areoutput. U3 latches the output fromU2 so that the output from the com-parator remains latched throughoutone clock period. The two-level out-put is taken from U3’s Q0 output.

The additional circuitry shown inthe schematic diagram allows thecircuit to output four-level data forPAM (pulse amplitude modulation)testing. The random data from thetwo-level output is input to a shiftregister, which is reset on every fourthclock pulse. The output from the shiftregister is weighted by the three 5kΩresistors and summed into theLT1220 operational amplifier fromwhich the output is taken. The filternetwork between the 74HC74 outputand the 74HC4094 strobe input isnecessary to ensure that the outputdata is correct.

feedback amplifier. A4’s output, whichis also the circuit’s output, is sampledby the A5-based gain-control con-figuration. This closes a gain controlloop to A3. A3’s ISET current controlsgain, allowing overall output levelcontrol.

Figure 2 plots noise at a 1MHzbandpass, whereas Figure 3 showsRMS noise versus frequency in thesame bandpass. Figure 4 plots similarinformation at full bandwidth(5MHz). RMS output is essentiallyflat to 1.5MHz, with about ±2dBcontrol to 5MHz before sagging badly.

+ –

D1 NC201

16k1µF

+15V

1k

1k

10Ω

–

+

1k

1.6k

0.1(1kHz)

0.01(10kHz)

0.001(100kHz)

100pF(1MHz)

NC (5MHz)

3k

910Ω

0.1

+

–

15V

–15V

A5 LT1006

–

+

15V

–15V510Ω

10Ω

0.5µF

22µF

– +

22µF

10k

1M

LT1004 1.2V

4.7k–15V

1N4148 THERMALLY

COUPLED

10k

1µF NON POLAR

NC 201= NOISE COM=

NOISE COM CORP. (201) 261-8797

A4 LT1228

CFA

A2 LT1226

–

+A3

LT1228 gm

Noise_1.eps

Figure 1. Broadband random noise generator schematic

24 Linear Technology Magazine • February 1994

Clock-Synchronized SwitchingRegulator has Coherent Noise

Gated-oscillator-type switchingregulators permit high efficiency overextended ranges of output current.These regulators achieve this desir-able characteristic by using agated-oscillator architecture insteadof a clocked pulse-width modulator.This eliminates the “housekeeping”currents associated with the continu-ous operation of fixed-frequencydesigns. Gated-oscillator regulatorssimply self-clock at whateverfrequency is required to maintainthe output voltage. Typically, loop-oscillation frequency ranges from afew hertz into the kilohertz region,depending upon the load.

This asynchronous, variable fre-quency operation seldom createsproblems; some systems, however, are

sensitive to this characteristic. Thecircuit in Figure 1 slightly modifies agated-oscillator -type switchingregulator by synchronizing its loop-oscillation frequency to the system’sclock. In this fashion the oscillationfrequency and its attendant switch-ing noise, although variable, are madecoherent with system operation.

Circuit operation is best under-stood by temporarily ignoring theflip-flop and assuming that theLT1107 regulator’s AOUT and FB pinsare connected. When the output volt-age decays, the set pin drops belowVREF, causing AOUT to fall. This causesthe internal comparator to switchhigh, biasing the oscillator and out-put transistor into conduction. L1receives pulsed drive, and its flyback

events are deposited into the 100µFcapacitor via the diode, restoring out-put voltage. This overdrives the setpin, causing the IC to switch off untilanother cycle is required.

The frequency of this oscillatorycycle is load dependent and variable.If a flip-flop is interposed in theAOUT –FB pin path, as shown, thefrequency is synchronized to the sys-tem clock. When the output decays farenough (trace A, Figure 2) the AOUTpin (trace B) goes low. At the nextclock pulse (trace C) the flip-flop Q2output (trace D) sets low, biasing thecomparator-oscillator. This turns onthe power switch (VSW pin is trace E),which pulses L1. L1 responds inflyback fashion, depositing its energyinto the output capacitor to maintain

Figure 1. A synchronizing flip-flop forces switching regulator noise to be coherent with the clock

by Jim Williams, Sean Gold,and Steve Pietkiewicz

DESIGN IDEAS

1107_1.eps

+100µF

5VOUT

SW2

1N5817ILIMITVIN

VREF 1.25V

VREFAOUT

FB

100k*

82.5k*

47ΩL1

221k*

SET

GND

SW1

100k

VIN 2V TO 4V

VCCPRE2

CLR1 Q2

D2PRE1

CLK1 CLK2

100kHz CLOCK POWERED FROM 5V OUTPUT

L1 = * =

22µH COILTRONICS CTX-20-2 1% METAL FILM RESISTOR COILTRONICS (407) 241-7876

D1 GND

CLR2Q1Q1

COMPARATOR

OSCILLATOR

AMPLIFIER

47k

74HC74

LT1107

–

+

–

+

Linear Technology Magazine • February 1994 25

C3 180µF 400V

D1 MUR540

+

1146_1.eps

RL

OUTPUT

R1 1.5k

CL

OS

GND2

VCC

INPUT SIGNAL

SIGNAL GROUND

ISOLATION BARRIER

C2 0.1µF CER

+

D3 MUR1560

VCC = 13V V+ = 300V

SYSTEM GROUND

IRF840TL4426

+ C1 100µF 25V

D2 1N752A

LTC1146A

VIN

GND1

E = 5V/DIV

D = 5V/DIV

C = 5V/DIV

B = 5V/DIV

A = 50mV/DIV (AC COUPLED)

HORIZ = 20µs/DIV1107_2.eps

start-up, the flip-flop’s remaining sec-tion is connected as a buffer. TheCLR1– CLK1 line monitors output volt-age via the resistor string. If the circuitdoes not start, Q1 is asserted, CLR2sets, and loop operation commences.Although the circuit shown is a step-up type, any switching regulatorconfiguration can use this technique.

output voltage. This operation is simi-lar to the previously described case,except that the sequence is forced tosynchronize with the system clock bythe flip-flop’s action. Although theresulting loop’s oscillation frequencyis variable, it, and all its attendantswitching noise, are synchronous andcoherent with the system clock.

Because of its sampled nature, thisclocked loop may not start. To ensure

IntroductionThe LTC1146 low-power digital iso-

lator draws only 70µA of supplycurrent with VIN = 5V. Its low supplycurrent feature is well suited for bat-tery-powered systems that requireisolation, such as an isolated high-side driver. The LTC1146A is rated at2500VRMS and is UL approved. TheLTC1146 is intended for less strin-gent applications. It is rated at500VDC.

Theory of OperationOpto-isolators available today re-

quire supply currents in themilliampere range even for low-speedoperation (less than 20kHz). This highsupply current is another drain onthe battery. Figure 1 shows the alter-native of using an LTC1146A to drivean external power MOSFET (IRF840)at speeds to 20kHz with V+ = 300V.

The input pin of LTC1146A mustbe driven with a signal that swings atleast 3 volts (referred to GND1, whichis a floating ground). The OS pin out-puts a square wave corresponding tothe input signal, but with a timedelay. The amplitude of the outputsquare wave is equal to the potentialat the VCC pin. The TL4426 is a high-speed MOSFET driver used here tosupply gate-drive current to the pow-

er MOSFET. The power supply to theLTC1146A and the TL4426 is boot-strapped from a 13V supply referredto system ground. C1 supplies thecurrent to both the LTC1146A andthe TL4426 when the power MOSFETis being turned on. Its value shouldbe increased when the input signal’sON time increases. D3 prevents the

output from swinging negative due tostray inductance. If the output goesbelow ground, the gate-to-source volt-age of the IRF840 rises. This highpotential could damage the powerMOSFET. The output slew rate shouldbe limited to 1000V/µs to preventglitches on the OS output of theLTC1146A.

An Isolated High-Side Driver

Figure 1. Isolated high-side driver schematic diagram

DESIGN IDEAS

by James Herr

Figure 2. Waveforms for the clock-synchronized switching regulator. Theregulator switches (trace E) only on clocktransitions (trace C), resulting in clock-coherent output noise (trace A)

22 Linear Technology Magazine • February 1994

Baro_1.eps

1µF

L1 COILTRONICS

CTX50-1

100Ω

5

10T1

68k

6

NOVASENSOR NPH-8-100AH†

1µF NONPOLAR

–

+A2

LT10770.1µF 200k*

1%10k 1%

R2 1k

OUTPUT

698Ω 1%

R1** 50Ω

100Ω 1%

–

+A1

LT1077

0.1µF100k

100k

LT1004-1.2

1N4148

100k

AA CELL

LT1110

LL

SW1

GNDSET

VIN

SW2

150Ω

FB

AO6

8 3

7

2 1

5 4

3 4

1N41482 1

100Ω

100µF

430k

39k

1N5818

390µF 16V NICHICON PL

NOMINAL VALUE EACH SENSOR REQUIRES TRIM FOR 150mV ACROSS A1-A2

* **

4

LUCAS NOVASENSOR FREMONT, CA (510) 490-9100 COILTRONICS (407) 241-7876

†

+

++

A Single-Cell BarometerFigure 1, a complete barometric

pressure signal conditioner, operatesfrom a single 1.5V battery. Untilrecently, high accuracy and stabilityhave been obtainable only with bond-ed strain gage and capacitively basedtransducers, which are quite expen-sive. This design, using a recentlyintroduced semiconductor transduc-er, achieves .01"Hg (inches of mercury)uncertainty over time and tempera-ture. The 1.5V powered operationpermits portable application.

The 6kΩ transducer (T1) requiresprecisely 1.5mA of excitation, neces-sitating a relatively high voltage drive.A1’s positive input senses T1’s cur-rent by monitoring the voltage dropacross the resistor string in T1’s re-turn path. A1’s negative input is fixedby the 1.2V LT1004 reference. A1’soutput biases the 1.5V poweredLT1110 switching regulator. TheLT1110’s switching produces two

outputs from L1. Pin 4’s rectified andfiltered output powers A1 and T1.A1’s output, in turn, closes a feed-back loop at the regulator. This loopgenerates whatever voltage step-up isrequired to force precisely 1.5mAthrough T1. This arrangement pro-vides the required high-voltage drivewhile minimizing power consump-tion. This occurs because theswitching regulator produces onlyenough voltage to satisfy T1’s currentrequirements.

L1 pins 1 and 2 source a boosted,fully floating voltage, which is recti-fied and filtered. This potential powersA2. Because A2 floats with respect toT1, it can look differentially acrossT1’s outputs, pins 10 and 4. In prac-tice, pin 10 becomes “ground” and A2measures pin 4’s output with respectto this point. A2’s gain-scaled outputis the circuit’s output, convenientlyscaled at 3.000V = 30.00"Hg.

To calibrate the circuit, adjust R1for 150mV across the 100Ω resistorin T1’s return path. This sets T1’scurrent to the manufacturer’s speci-fied calibration point. Next, adjust R2at a scale factor of 3.000V = 30.00"Hg.If R2 cannot capture the calibration,reselect the 200kΩ resistor in serieswith it. If a pressure standard is notavailable, the transducer is suppliedwith individual calibration data, per-mitting circuit calibration.

This circuit, compared to a high-order pressure standard, maintained.01"Hg accuracy over months withwidely varying ambient pressureshifts. Changes in pressure, particu-larly rapid ones, correlated quitenicely to changing weather conditions.Additionally, because .01"Hgcorresponds to about 10 feet of alti-tude at sea level, driving over hillsand freeway overpasses becomes quiteinteresting. The circuit pulls 14mAfrom the battery, allowing about 250hours operation from one D cell.

DESIGN IDEAS

Figure 1. Schematic diagram: single-cell barometer

by Jim Williams andSteve Pietkiewicz

24 Linear Technology Magazine • May 1996

DESIGN FEATURES

CCFL_1.eps

FULL AMPLITUDE HIGH VOLTAGE

PARASITIC LOSS PATH

PARASITIC LOSS PATH

PARASITIC LOSS PATH

PARASITIC LOSS PATHS

DIODES INTERNAL IN LT118X-BASED CIRCUITS

TO FEEDBACK NODE

ESSENTIALLY 0V

ENERGY LOST IN PARASITIC PATHS = 1/2 CV2

BALLAST CAPACITOR

CCFL LAMP

CCFL_2.eps

1/2 AMPLITUDE HIGH VOLTAGE

1/2 AMPLITUDE HIGH VOLTAGE

PARASITIC LOSS PATH

PARASITIC LOSS PATH

PARASITIC LOSS PATH

PARASITIC LOSS PATHS ENERGY LOST IN

PARASITIC PATHS = 1/2 CV2

PARASITIC LOSS PATH

BALLAST CAPACITOR

CCFL LAMP

Figure 1. Ground-referred lamp drive has large energy loss in high voltage regions due to fullamplitude swing.

Figure 2. “Floating” lamp allows reduced bipolar drive, cutting losses due to parasitic capaci-tance paths. Formerly grounded lamp end’s paths absorb more energy than before, but overallloss is lower due to equation’s V2 term.

Selection Criteria for CCFL Circuits by Jim Williams

Previous LTC publications havediscussed issues and circuitry re-lated to powering cold cathodefluorescent lamps (CCFLs). 1 Theselamps are almost universally em-ployed for backlighting liquid crystaldisplays (LCDs). The large variety ofdisplays and applications necessitatesa wide range of circuit approaches. Asingle method providing optimal re-sults in all situations, althoughdesirable, remains elusive. As a re-sult, a very wide array of potentialsolutions have been developed andpresented. This makes selecting anapproach for any given applicationsomewhat confusing.

Comfort arrives with the realiza-tion that the circuits fall into twobroad categories. All approaches drivethe lamp in either a “grounded” or“floating” configuration. Understand-ing these terms and their significancein selecting a lamp-driving approachis the subject of this tutorial.

Sources of Energy Lossin Practical ApplicationsAchieving high efficiency for a back-light design requires careful attentionto the physical layout of the lamp, itsleads and the construction of thedisplay housing. Parasitic capacitancefrom any high voltage point to DC orAC ground creates a path for un-wanted current flow. This parasiticcurrent degrades electrical efficiency.The loss term is related to 1/2CV2fwhere C is the parasitic capacitance,V is the voltage at any point on thelamp and f is the operating frequency.Losses up to 25% have been observed.Layout techniques that increase para-sitic capacitance include long highvoltage lamp leads, reflective metalfoil around the lamp and displayssupplied in metal enclosures.

Grounded circuits drive the lampin single-ended fashion. Figure 1shows one lamp electrode receivingdrive with the other terminalessentially at ground. This causessignificant loss via parasitic pathsassociated with the lamp’s driven end.

This is so because of the large voltageswing in this region. The parasiticpaths near the lamp’s grounded endundergo relatively little swing,contributing small energy loss. Un-fortunately, the lost energy is heavilyvoltage dependent (E = 1/2CV2) andnet energy loss is excessive if driven-end parasitics are large. Figure 2’sconfiguration minimizes the lossesby altering the drive scheme. In thiscase the lamp is driven from bothends instead of one end beinggrounded.

This “floating” lamp arrangementrequires only half the voltage swing ateach end instead of full swing at oneend. This introduces more loss in theparasitic paths previously tied to thegrounded end. In most cases, theseincreased losses are favorably offsetby the reduced swing because of theV2 loss term associated with voltageamplitude.

The advantage gained varies con-siderably with display type, althougha 10% to 20% reduction in lost energyis common. In some displays lossreduction is not as good, and occa-sionally the improvement is negligible.Heavily asymmetric wiring to or withinthe display can sometimes make float-ing drive more lossy than groundeddrive. In such cases, testing in bothmodes is necessary to determinewhich type of drive is most efficient.

A second advantage of floating op-eration is extended illumination range.Grounded lamps operating at rela-tively low currents may display the“thermometer effect”; that is, lightintensity may be nonuniformly dis-tributed along the lamp’s length.

Figure 3’s grounded scheme showsthat although lamp-current densityis uniform, the associated field isimbalanced. The field’s low intensity,combined with its imbalance, means

Linear Technology Magazine • May 1996 25

DESIGN FEATURES

CCFL_3.eps

HIGH VOLTAGE LAMP

FIELD STRENGTH INCREASES WITH INCREASING DISTANCE

FROM GROUNDED END OF LAMP

ESSENTIALLY GROUNDED

TO FEEDBACK

HIGH VOLTAGE

FIELD STRENGTH INCREASES WITH INCREASING DISTANCE

FROM CENTER OF LAMP

TRANSFORMER SECONDARY

CCFL_4.eps

HIGH VOLTAGE

LAMP

Figure 4. Field strength versus distance for afloating lamp. Improving field imbalancepermits extended illumination range at lowlevels.

Figure 3. Field strength versus distance for a ground referred lamp. Field imbalance promotesuneven illumination at low drive levels.

that there is not enough energy tomaintain uniform phosphor glow be-yond some point. Lamps displayingthe thermometer effect emit most oftheir light near the driven electrode,with rapid emission fall-off as dis-tance from the electrode increases.

Some displays require extendedillumination range. “Thermometering”usually limits the lowest practicalillumination level. One acceptable wayto minimize thermometering is toeliminate the large field imbalance.The floating drive used to reduce en-ergy loss also provides a way tominimize thermometering.

Figure 4 shows the effects of float-ing drive on lamp-field balance. Thebalanced field provides excitation atboth lamp ends, aiding low currentillumination. In a well optimized float-ing-lamp display, thermometeringstarts in the lamp’s center, simulta-neously proceeding towards both endsas drive is reduced.

Selection CriteriaThe different characteristics ofgrounded and floating circuits shouldbe kept in focus when reviewing aparticular application’s requirements.

Selecting which CCFL circuit to usefor a specific application involvesnumerous trade-offs. A variety of is-sues determine which circuit is the“best” approach. At a minimum, theuser should consider the followingguidelines before committing to anyapproach.

Display CharacteristicsThe display characteristics (includ-ing wiring losses) should be wellunderstood. Typically, display manu-facturers list lamp requirements.These specifications are often obtainedfrom the lamp vendor, who usuallytests in free air, with no significantparasitic loss paths. This means thatthe actual required power, start andrunning voltages may dif fersignificantly from the datasheet speci-fications. The only way to be certain ofdisplay characteristics is to measurethem. The measured display energyloss can determine whether a floatingor grounded circuit is applicable. Lowloss displays (relatively rare) usuallyprovide better overall efficiency withgrounded drive. As losses becomeworse (unfortunately, relatively com-mon) floating drive becomes a betterchoice. Efficiency measurements inboth modes may be required to deter-mine the best choice.

Operating Voltage RangeThe operating voltage range spansthe minimum and maximum voltagesfrom which the circuit must operate.In battery-driven apparatus, the sup-ply range can easily be 3:1 or greater.The best backlight performance isusually obtained in the 8V–28V range.In general, potentials below 7V re-

quire some efficiency trade-offs atmoderate (1.5W to 3W) power levels.Some systems reduce backlight powerwhen running from the battery, andthis can have a pronounced effect onthe design. Even seemingly small (e.g.,20%) reductions in power may elimi-nate painful trade-offs. In particular,high-turns-ratio transformers arerequired to support low voltage op-eration at full lamp output. Thesetransformers work well, but are some-what less efficient than those withlower turns ratios, due to their highercharacteristic peak currents. Prevail-ing trends in battery technologyencourage system operation at lowvoltages, necessitating extreme carein transformer selection and Royercircuit design.

Auxiliary Operating VoltagesAuxiliary logic supply voltages shouldbe used (if available) to run CCFL“housekeeping” currents, such as ICVIN pins. This saves power. Alwaysrun switching regulators from thelowest potential available, usually3.3V or 5V. Many systems providethese voltages in switched form,making separate shutdown lines un-necessary. Turning off the switchingregulator’s supply shuts down theentire backlight circuit.

Line RegulationGrounded lamp circuits, by virtue oftheir true global feedback, providethe best line regulation. For abruptchanges, a user may notice anythingbeyond a 1% variation in regulation.A grounded circuit easily meets thisrequirement; a floating circuit willusually do so. Excursions beyond 1%,caused by slowly changing line in-puts, are not normally a problembecause they are not detectable. Rapidline changes, such as plugging in asystem AC line adapter, require goodregulation to avoid annoying displayflicker.

Power RequirementsThe CCFL’s power requirement, in-cluding display and wiring losses,should be well defined over all condi-

26 Linear Technology Magazine • May 1996

DESIGN FEATURES

seussI seireSX811TL seireSX711TL seireSX731TL

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egatlovCDelbairav,MWP,.toPtnerrucro

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segatlovylppushgih

langis-llamslanretxeseriuqeRtasetercsidemosdnarotsisnart

segatlovylppushgih

eziS llams,tnuoctnenopmocwoL.tnirptoofdraobllarevo

.scitengamzHk002

scitengamzHk001––llamS rofscitengamzHM1––llamSsnoisrevtsetsaf

ytilibapaCylppuStsartnoC snoitpoylppustsartnocsuoiraVtuptuoralopibgnidulcni,elbaliava

oN oN

Table 1. Characteristics of LT parts families

tions, including temperature andlamp-specification variations. Usu-ally, IC versions of floating lampcircuits are restricted to 3W to 4Woutput power, whereas grounded-cir-cuit power is easily scaled.

Supply Current ProfileThe backlight is often located far “for-ward” in the system. Impedance incables, switches, traces and connec-tors can build up to significant levels.This means that a CCFL circuit should

draw operating power continuously,rather than requiring discrete, highcurrent “chunks” from a lossy supplyline. Royer-based architectures arenearly ideal in this regard, pullingcurrent smoothly over time and re-quiring no special bypassing, supplyimpedance or layout treatment. Simi-larly, Royer-type circuits do not causesignificant disturbances to the sup-ply line, preventing noise injectionback into the supply.

Lamp Current CertaintyLamp current accuracy at full inten-sity is important for maintaininglamp life. Excessive overcurrentgreatly shortens lamp life, while yield-ing little luminosity benefit. Groundedcircuits are excellent in this category,with 1% accuracy usually achieved.Floating circuits are typically in the2% range. Tight current tolerancesdo not benefit unit/unit display lumi-nosity because lamp emission and

Linear Technology Magazine • May 1996 27

DESIGN FEATURES

display attenuation variations ap-proach ±20% and vary over life.

EfficiencyCCFL backlight efficiency should beconsidered from two perspectives. Theelectrical efficiency is the ability of thecircuit to convert DC power to highvoltage AC and deliver it to the load(lamp and parasitic) with minimumloss. The optical efficiency is perhapsmore meaningful to the user. It issimply the ratio of display luminosityto DC power into the CCFL circuit.The electrical and optical losses arelumped together in this measurementto produce a luminosity versus powerspecification. It is quite significantthat the electrical and optical peakefficiency operating points do not nec-essarily coincide. This is primarily

due to the dependence of the lamp’semissivity on wave shape. The opti-mum wave shape for emissivity mayor may not coincide with the circuit’selectrical operating peak. In fact, it isquite possible for inefficient circuitsto produce more light than more effi-cient versions. The only way to ensurepeak efficiency in a given situation isto optimize the circuit to the display.

ShutdownSystem shutdown almost always re-quires turning off the backlight. Inmany cases, the low voltage supply isalready available in switched form. Ifthis is so, the CCFL circuits turn off,absorbing very little power. If switchedlow voltage power is not available, theshutdown inputs may be used, re-quiring an extra control line.

Transient ResponseThe CCFL circuit should turn on thelamp without attendant overshoot orpoor control loop settling character-istics. This can cause objectionabledisplay flicker, and, in the worst case,result in transformer overstress andfailure. Properly prepared floating andgrounded CCFL circuits have goodtransient response, with LT118X-based types being inherently easierto optimize.

Dimming ControlThe method of dimming should beconsidered early in the design. All ofthe circuits shown in this article canbe controlled by potentiometers, DCvoltages and currents, pulse-widthmodulation or serial data protocols.Use a dimming scheme with high

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Table 1. (continued)

28 Linear Technology Magazine • May 1996

DESIGN FEATURES

accuracy at maximum current to pre-vent excessive lamp drive.

Open Lamp ProtectionThe CCFL circuits deliver a currentsource output. If the lamp is brokenor disconnected, the compliance volt-age is limited by the transformer turnsratio and DC input voltage. Excessivevoltage can cause arcing and resultantdamage. Typically, the transformerswithstand this condition, but openlamp protection will ensure againstfailures. This feature is built into theLT118X series; it must be added toother circuits.

SizeBacklight circuits usually have se-vere size and component-countlimitations. The board must fit withintightly defined dimensions. LT118Xseries-based circuits offer the lowestcomponent count, although boardspace is usually dominated by theRoyer transformer. In extremely tightspaces, it may be necessary to physi-cally segment the circuit, but thisshould be considered only as a lastresort.

Contrast Supply CapabilitySome LT118X parts provide contrast-supply outputs. The other circuits do

Table 2. Features of LT118X series parts

not. The LT118X’s onboard contrastsupply is usually an advantage, butspace is sometimes so restricted thatit cannot be used. In such cases thecontrast supply must be remotelylocated.

EmissionsBacklight circuits rarely cause emis-sion problems, and shielding isusually not required. Higher powerversions (for example, above 5W) mayrequire attention to meet emissionrequirements. The fast-rise switch-ing regulator output sometimescauses more RFI than the high volt-age AC waveform. If shielding is used,its parasitic effects are part of theinverter load and optimization mustbe carried out with the shield in place.

Summary of CircuitsThe interdependence of backlightparameters makes summarizing orrating various approaches a hazard-ous exercise. There is simply nointellectually responsible way tostreamline the selection and designprocess if optimum results are de-sired. A meaningful choice must bethe outcome of laboratory-based ex-perimentation. There are just toomany interdependent variables andsurprises for a systematic, theoreti-

cally based selection. Pure analyticsare pretty—working circuits comefrom the bench. Some generalizationsof limited use are, however, possible.Tables 1 and 2 attempt to summarizesalient characteristics versus parttype and may (however cautiously) beconsidered as a beginning point. 2

Table1 summarizes characteristicsof all the circuits. Table 2 focuses onthe features of the LT118X seriesparts.

References:

1. Williams, Jim. Measurement andControl Circuit Collection. LinearTechnology Corporation Applica-tion Note 45, June 1991.

2. Williams, Jim. IlluminationCircuitry for Liquid CrystalDisplays. Linear TechnologyCorporation Application Note 49,August 1992.

3. Williams, Jim. Techniques for92% Efficient LCD Illumination.Linear Technology CorporationApplication Note 55, August1993.

4. Bonte, Anthony. LT1182 FloatingCCFL with Dual Polarity Contrast.Linear Technology CorporationDesign Note 99, March 1995.

5. Williams, Jim. A Fourth Genera-tion of LCD Backlight Technology.Linear Technology CorporationApplication Note 65, December1995.

Notes:

1 LTC’s investigation of CCFLs has been reportedin a continuing series of publications, whichappear in the “References” at the end of thisarticle. In particular, reference 5 (the source ofthis text) reviews all previous work and presentsrecent findings.

2 Readers detecting author ambivalence about theinclusion of Tables 1 and 2 are not hallucinating.

Authors can be contacted at (408) 432-1900

traP 2811TL 3811TL 4811TL F4811TL 6811TL

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tsartnoCralopinUstuptuO oN oN oN

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38 Linear Technology Magazine • August 1996

DESIGN IDEAS

LTC1441-Based MicropowerVoltage-to-Frequency Converter

by Jim Williams

Figure 1 is a voltage-to-frequencyconverter. A 0V–5V input produces a0–10kHz output, with a linearity of0.02%. Gain drift is 60ppm/°C. Maxi-mum current consumption is only26µA, 100 times lower than currentlyavailable units.

To understand the circuit’s opera-tion, assume that C1’s negative inputis slightly below its positive input(C2’s output is low). The input voltagecauses a positive-going ramp at C1’sinput (trace A, Figure 2). C1’s outputis high, allowing current flow fromQ1’s emitter, through C1’s outputstage to the 100pF capacitor. The2.2µF capacitor provides high fre-quency bypass, maintaining lowimpedance at Q1’s emitter. Diode con-nected Q6 provides a path to ground.The voltage to which the 100pF unit

charges is a function of Q1’s emitterpotential and Q6’s drop. C1’s CMOSoutput, purely ohmic, contributes novoltage error. When the ramp at C1’snegative input goes high enough, C1’soutput goes low (trace B) and theinverter switches high (trace C). Thisaction pulls current from C1’s nega-tive input capacitor via the Q5 route(trace D). This current removal resetsC1’s negative input ramp to a poten-tial slightly below ground. The 50pFcapacitor furnishes AC positive feed-back (C1’s positive input is trace E)ensuring that C1’s output remainsnegative long enough for a completedischarge of the 100pF capacitor. TheSchottky diode prevents C1’s inputfrom being driven outside its negativecommon mode limit. When the 50pFunit’s feedback decays, C1 again

switches high and the entire cyclerepeats. The oscillation frequencydepends directly on the input-volt-age-derived current.

Q1’s emitter voltage must be care-fully controlled to get low drift. Q3and Q4 temperature compensate Q5and Q6 while Q2 compensates Q1’sVBE. The three LT1004s are the actualvoltage reference and the LM334 cur-rent source provides 12µA bias to thestack. The current drive providesexcellent supply immunity (betterthan 40ppm/V) and also aids circuittemperature coefficient. It does thisby using the LM334’s 0.3%/°C tempcoto slightly temperature modulate thevoltage drop in the Q2–Q4 trio. Thiscorrection’s sign and magnitudedirectly oppose the –120ppm/°C100pF polystyrene capacitor’s drift,

DIVF_01.eps

+

+

–

10kHz TRIM 200k

C1 1/2 LTC1441

+

–C2

1/2 LTC1441

1.2M*

15k

10M

100Hz TRIM 3M TYP

100pF†

INPUT 0–5V

0.01

100k

= HP5082-2810

= 1N4148

= 2N5089 = 2N2222 = POLYSTYRENE = 1% METAL FILM

Q1, Q2, Q8 ALL OTHER

† *

6.04k*

LM334

2.7M

0.1

50pF

+V = 6.2 → 12V

74C14

2.2µF

+0.47

LT1004 1.2V x 3

Q7Q5

Q1

Q6

Q4

Q8

Q3

Q2

GROUND ALL UNUSED 74C14 INPUTS

OUTPUT

Figure 1. 0.02% V/F converter requires only 26µA supply current

Linear Technology Magazine • August 1996 39

DESIGN IDEAS

aiding overall circuit stability. Q8’sisolated 100pF drive to the CMOSinverter prevents output loading frominfluencing Q1’s operating point. Thismakes circuit accuracy independentof loading.

The Q1 emitter-follower deliverscharge to the 100pF capacitor effi-ciently. Both base and collectorcurrent end up in the capacitor. The100pF capacitor, as small as accu-

FREQUENCY (kHz)

0

5

10

15

20

25

35

30

CURR

ENT

CONS

UMPT

ION

(µA)

12

DIVF_03.eps

0 1 2 3 4 5 6 7 8 9 10 11

SLOPE = 1.1µA/kHz

racy permits, draws only small tran-sient currents during its charge anddischarge cycles. The 50pF–100kpositive feedback combination drawsinsignificantly small switching cur-rents. Figure 3, a plot of supplycurrent versus operating frequency,reflects the low power design. At zerofrequency, comparator quiescent cur-rent and the 12µA reference stackbias account for all current drain.There are no other paths for loss. Asfrequency scales up, the 100pFcapacitor’s charge-discharge cycleintroduces the 1.1µA/kHz increaseshown. A smaller value capacitorwould cut power, but effects of straycapacitance and charge imbalancewould introduce accuracy errors.

Circuit start-up or overdrive cancause the circuit’s AC-coupled feed-back to latch. If this occurs, C1’soutput goes low; C2, detecting thisvia the 2.7M–0.1µF lag, goes high.This lifts C1’s positive input and

grounds the negative input with Q7,initiating normal circuit action.

To calibrate this circuit, apply50mV and select the indicated resis-tor at C1’s positive input for a 100Hzoutput. Complete the calibration byapplying 5V and trimming the inputpotentiometer for a 10kHz output.

Figure 2. Waveforms for the micropower V/Fconverter: charge-based feedback providesprecision operation with extremely low powerconsumption.

Figure 3. Current consumption versusfrequency for the V/F converter: charge/discharge cycles account for 1.1µA/kHzcurrent drain increase.

shutdown to cover the external tran-sistors. The thermal shutdown of theLT1210 activates when the junctiontemperature reaches 150˚C and hasabout 10˚C hysteresis. The thermalresistance RθJC of the TO-220 pack-age (LT1210CY) is 5˚C/Watt).

–

+

11.8kIN

2

36

5

7OUT

4

0.01

Q2, D44VH4

Q1, D45VH4

0.033Ω

0.033Ω

R1 6.2Ω

R2 6.2Ω

0.01

18V

3.6k

–18V

0.01

LT1210

8

7

6

4AP–P INTO 1Ω

50Ω LOAD

1Ω LOAD

FIGURE 6 CKT +10dBM INPUT

5

4

3

2

1

0

–1

–210K

GAIN

(dB)

100K 1MFREQUENCY (Hz)

10M

SummaryThe LT1210 is a great part; its perfor-mance in terms of speed, outputcurrent and output voltage is unsur-passed. Its C-Load™ output driveand thermal shutdown allow it totake its place in the real world—nokid gloves are required here. If thegenerous output specification of the

LT1210 isn’t big enough for yourneeds, just add a couple of transis-tors to dissipate the additional powerand you are on your way. Only theworldwide supply of transistors lim-its the amount of power you couldcommand with one of these parts.

Figure 6. ±10A/1MHz current-boosted powerop amp

Figure 7. Gain versus frequency response of current-boosted amplifier

LT1210, continued from page 37

A = 50mV/DIV

B = 5V/DIV

C = 5V/DIV

E = 5V/DIV

D = 1mA/DIV

HORIZ = 20µs/DIV

Linear Technology Magazine • June 199728

DESIGN IDEAS

–

+–

+

–

+–

+LTC1440

LTC1440

10M

10M

10M

0.047µF

Ø2

Ø1

5V

–5V

LT1495 LT1495

1/2 CD4016 1/2 CD4016

1µF

1µF

CCOMP 0.1µF

1M

1M

1M

10M

10k

10M

10k

1

2

3

4

5

13

Ø2

Ø1

Ø1

Ø2

1112

10

9

6

8

A1A A1B

–5V

5V

OUT

IN

C1A

C1B

0.05µV/˚C Chopped AmplifierRequires Only 5µA Supply Current

by Jim Williams

Figure 1 shows a chopped ampli-fier that requires only 5.5µA supplycurrent. Offset Voltage is 5µV, with0.05µV/˚C drift. A gain exceeding 108

affords high accuracy, even at largeclosed-loop gains.

The micropower comparators (C1Aand C1B) form a biphase 5Hz clock.The clock drives the input-relatedswitches, causing an amplitude-modulated version of the DC input toappear at A1A’s input. AC-coupledA1A takes a gain of 1000, presentingits output to a switched demodulatorsimilar to the aforementionedmodulator.

The demodulator output, a recon-structed, DC-amplified version of thecircuit’s input, is fed to A1B, a DCgain stage. A1B’s output is fed back,via gain setting resistors, to the inputmodulator, closing a feedback looparound the entire amplifier. Theconfiguration’s DC gain is set by thefeedback resistor’s ratio, in this case1000.

The circuit’s internal AC couplingprevents A1’s DC characteristics frominfluencing overall DC performance,

accounting for the extremely low off-set uncertainty noted. The highopen-loop gain permits 10ppm gainaccuracy at a closed-loop gain of 1000.

The desired micropower operationand A1’s bandwidth dictate the 5Hzclock rate. As such, the resultantoverall bandwidth is low. Full-powerbandwidth is 0.05Hz with a slew rateof about 1V/s. Clock-related noise,about 5µ V, can be reduced byincreasing CCOMP, with commensu-rate bandwidth reduction.

Figure 1. 0.05µV/˚C chopped amplifier requires only 5µA supply current

for the latest information

on LTC products, visit

www.linear-tech.com

Linear Technology Magazine • February 199824

DESIGN IDEAS

The LT1533 switching regulator1, 2

achieves 100µV output noise by usingclosed-loop control around its out-put switches to tightly controlswitching transition time. Slowingdown switch transitions eliminateshigh frequency harmonics, greatlyreducing conducted and radiatednoise.

The part’s 30V, 1A output transis-tors limit available power. It is possibleto exceed these limits while main-taining low noise performance byusing suitably designed outputstages.

LT1533 Ultralow Noise SwitchingRegulator for High Voltage orHigh Current Applications

High Voltage Input RegulatorThe LT1533’s IC process limitscollector breakdown to 30V. A com-plicating factor is that the transformercauses the collectors to swing to twicethe supply voltage. Thus, 15V repre-sents the maximum allowable inputsupply. Many applications requirehigher voltage inputs; the circuit inFigure 1 uses a cascoded3 outputstage to achieve such high voltagecapability. This 24V to 5V (VIN = 20V–50V) converter is reminiscent ofprevious LT1533 circuits, except for

the presence of Q1 and Q2.4 Thesedevices, interposed between the ICand the transformer, constitute a cas-coded high voltage stage. They providevoltage gain while isolating the ICfrom their large drain voltage swings.

Normally, high voltage cascodesare designed to simply supply voltageisolation. Cascoding the LT1533 pre-sents special considerations becausethe transformer’s instantaneous volt-age and current information must beaccurately transmitted, albeit at loweramplitude, to the LT1533. If this isnot done, the regulator’s slew-control

SYNC

DUTY

SHDN

PGND

NFB

FBRVSLRCSL

LT1533

VINCOL A COL B14

2 15

16

8

7

4

3

11

5

6

10

1500pF

0.002µF

18k

0.01µF

0.002µF

L2

10µF

10k

1k

+

L1 100µH

L3 100µH

5VOUT

1312

7.5k 1%

2.49k 1%

220µF

MBRS140

L1, L3: COILTRONICS CTX100-3 L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR INDUCTOR COILCRAFT B-07T TYPICAL Q1, Q2: MTD6N15 T1: COILTRONICS VP4-0860

AN70 F40

100µF

CT

RT

VC

OPTIONAL SEE TEXT( )+10k

12k

GND

9

24VIN (20V TO 50V)

Q3 MPSA42

Q4 2N2222

4.7µF

10k

9

4

3

101

12

2

11

7

6 T1

5

8

Q21k

220Ω10k220Ω

MBRS140

+

+Q1

Figure 1. A low noise 24V to 5V converter (VIN = 20V–50V): cascoded MOSFETs withstand 100V transformer swings, permitting the LT1533 tocontrol 5V/2A output.

by Jim Williams

Linear Technology Magazine • February 1998 25

DESIGN IDEAS

A = 20V/DIV

B = 5V/DIV(AC COUPLED)

C = 100V/DIV

10µs/DIV

SHDN

DUTY

SYNC

COL A

COL B

PGND

RVSL

RCSL

FBNFB

LT1533

GND

VIN

5V

14

2

15

16

13

12

7

11

3

4

5

6

10

1500pF

18k

0.01µF

10k

R2 2.49k 1%

L2

4.7µF

10k

+T1 L1

300µH12V L3

33µH

89

R1 21.5k 1%

+ +100µF 100µF

1N5817

1N5817

1N4148

1N4148

AN70 F42

CT

RT

VC

OPTIONAL FOR LOWEST RIPPLE( )

330Ω

330Ω

0.05Ω

0.05Ω4.7µF+

Q2

Q10.003µF

680Ω

L1: COILTRONICS CTX300-4 L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR INDUCTOR. COILCRAFT B-07T TYPICAL L3: COILTRONICS CTX33-4 Q1, Q2: MOTOROLA D45C1 T1: COILTRONICS CTX-02-13949-X1 : FERRONICS FERRITE BEAD 21-110J

A = 5mV/DIV

B = 100µV/DIV

2µs/DIV

loops will not function, causing adramatic output noise increase. TheAC-compensated resistor dividersassociated with the Q1–Q2 gate-drainbiasing serve this purpose, prevent-ing transformer swings coupled viagate-channel capacitance fromcorrupting the cascode’s waveform-transfer fidelity. Q3 and associatedcomponents provide a stable DC ter-mination for the dividers whileprotecting the LT1533 from the highvoltage input.

Figure 2 shows that the resultantcascode response is faithful, even with100V swings. Trace A is Q1’s source;traces B and C are its gate and drain,respectively. Under these conditions,at 2A output, noise is inside 400µVpeak.

Current BoostingFigure 3 boosts the regulator’s 1Aoutput capability to over 5A. It doesthis with simple emitter followers (Q1–Q2). Theoretically, the followerspreserve T1’s voltage and currentwaveform information, permitting theLT1533’s slew-control circuitry tofunction. In practice, the transistorsmust be relatively low beta types. At3A collector current, their beta of 20sources ≈150mA via the Q1–Q2 basepaths, adequate for proper slew-loopoperation.5 The follower loss limitsefficiency to about 68%. Higher inputvoltages minimize follower-inducedloss, permitting efficiencies in the low70% range.

Figure 4 shows noise performance.Ripple measures 4mV (Trace A) usinga single LC section, with high fre-

quency content just discernible. Add-ing the optional second LC sectionreduces ripple to below 100µV (traceB), and high frequency content isseen to be inside 180µV (note ×50vertical scale-factor change).

Notes:

1 Witt, Jeff. The LT1533 Heralds a New Class ofLow Noise Switching Regulators. Linear Technol-ogy VII:3 (August 1997).

2 Williams, Jim. LTC Application Note 70: A Mono-lithic Switching Regulator with 100µV OutputNoise. October 1997.

3 The term “cascode,” derived from “cascade tocathode,” is applied to a configuration that placesactive devices in series. The benefit may be higherbreakdown voltage, decreased input capacitance,bandwidth improvement or the like. Cascodinghas been employed in op amps, power supplies,oscilloscopes and other areas to obtain perfor-mance enhancement.

4 This circuit derives from a design by Jeff Witt ofLinear Technology Corp.

5 Operating the slew loops from follower base cur-rent was suggested by Bob Dobkin of LinearTechnology Corp.

Figure 2. MOSFET-based cascode permits the regulator to control100V transformer swings while maintaining a low noise 5V output.Trace A is Q1’s source, Trace B is Q1’s gate and Trace C is the drain.Waveform fidelity through cascode permits proper slew-controloperation.

Figure 4. Waveforms for Figure 3 at 10W output: Trace A showsfundamental ripple with higher frequency residue just discernible. Theoptional LC section results in Trace B’s 180µVP-P wideband noiseperformance.

Figure 3. A 10W low noise 5V to 12V converter: Q1–Q2 provide 5A output capacity while preserving the LT1533’s voltage/current slew control.Efficiency is 68%. Higher input voltages minimize follower loss, boosting efficiency above 71%.

Linear Technology Magazine • May 199820

DESIGN FEATURES

A 7ns, 6mA, Single-SupplyComparator Fabricated on Linear’s6GHz Complementary Bipolar Process

IntroductionThe LT1394 is an ultrafast (7ns), lowpower (6mA), single-supply compara-tor designed to operate on either 5Vor ±5V supplies. It has a maximumoffset voltage of 2.5mV, complemen-tary TTL compatible outputs andoutput latch capability. The LT1394is the first product made with LinearTechnology’s 6GHz complementarybipolar technology. This fine-linegeometry process results in a productwith dramatically improved speed andpower compared to industry-standardcomparators developed in slower NPN-only technologies.

These features combine to makethe LT1394 well suited for applica-

tions such as high performance NTSCcrystal oscillators, single-supply volt-age-to-frequency converters and highspeed, high accuracy level detectors.The LT1394 is offered in SO-8 and ispin compatible with the industry-standard LT1016 and LT1116comparators.

Circuit DescriptionA simplified schematic of the LT1394can be seen in Figure 1. There aredifferential inputs (+IN/–IN), differ-ential outputs (OUT/OUT), a latchinput (LATCH) and three power supplypins (VEE, VCC and GND). The circuittopology consists of a differential input

stage, a level-shifting gain stage, alatch stage and complementary out-put stages. The complementaryoutput stages offer improved flexibil-ity for the user; the latch stage providessuperior sampling accuracy of theinput signal without the need for anexternal latch.

The input stage of the LT1394 usesa PNP differential pair (Q1–Q2) withSchottky diodes in the emitters (D1–D2) and resistive loads (R1–R2). TheSchottky diodes in series with theemitters allow differential input volt-ages that are greater than thebase-emitter breakdown of the inputtransistors. Two additional Schottky

D15

D2 D1

D4

Q6 Q5

Q7

Q8

Q10

Q13 Q14

Q12

I5 I6 I7R8 R9 R11 R12

Q15

R7 R10

Q16 Q21

Q22

Q24 Q25Q30

D25

D26

OUT

OUT

D27

D28Q29

Q28

Q27Q26

Q23

Q20Q18Q17I13

Q33

D10

D9

Q11

Q9

Q34 Q35

I12I11I10I9I8

D5

D6

D7R1R2

D20

GND

D21

LATCH

D22

D23

D24

R4 R3 R6 R5

D3

Q3

Q4

I1 I2 I3 I4

Q2 Q1D16

D17D12

D11

D18

D19

IN+

IN–

VCC

VEE 1394_01.eps

D8

Q19

Q32

Q31VCC

VCCVEE

VCC

VCC

VCC

VCC

VCC

VEE

VEE

VEE

VEE

VEE

VEE

Figure 1. LT1394 simplified schematic

Authors can be contacted at (408) 432-1900

by Jim Williams and Brian Hamilton

Linear Technology Magazine • May 1998 21

DESIGN FEATURES

diodes (D11–D12) prevent outputphase reversal when either input istaken far enough below VEE to for-ward bias the base-collector junctionof its corresponding PNP inputtransistor. To allow single-supply op-eration, the input stage has beendesigned to have small voltage swingsacross load resistors R1 and R2. Thisensures that the input PNPs will notsaturate with the LT1394 inputs atVEE.

The signal path remains differen-tial as it is buffered and level shiftedvia transistors Q3–Q4 and diodes D3–D4. The level shift prevents currentsource I8 from saturating. The secondgain stage, comprising transistors Q5–Q6 and resistors R3–R4, takesadditional gain while level shiftingthe signal back to VCC. The differen-tial output of the second gain stage isbuffered by transistors Q7–Q8, whichthen drive the latch stage.

In the latch stage, transistors Q9–Q10 and resistors R5–R6 act as athird gain stage. Q11–Q12 buffer thesignal at resistors R5–R6, drivinganother differential pair (Q13–Q14).Q13 and Q14, when activated, pro-vide positive feedback to resistorsR5–R6, creating the latch. When theLATCH pin is low, the LT1394 is inflow-through or GAIN mode. CurrentI11 is steered through Q34, activatingthe Q9–Q10 differential pair. Whenthe LATCH pin is high, the LT1394 isin LATCH mode. Current I11 is steeredthrough Q35, activating the Q13–Q14differential pair. The output of thegain/latch stage has additional levelshifting from the emitters of transis-tors Q11–Q12 via diodes D9–D10.This level shifting prevents the out-put stage current sources I6 and I7from saturating.

The LT1394 provides complemen-tary outputs by using two identicaloutput stages connected in oppositephases. Examining the output cir-cuitry for the OUT pin, a PNPdifferential pair (Q15–Q16) is drivenfrom the outputs of the latch stage.When I6’s current is steered throughQ16, it drives R7 and the base of Q19.R7 improves switching speed byreducing the gain of the differential

pair Q15–Q16 and lowering theimpedance at the base of Q19. Q19’semitter current then drives the baseof Q23, turning it on until the OUTpin has been pulled low and Q23’sSchottky clamp diode has turned on.Conversely, if I6’s current is steeredthrough Q15, it allows R8 to pull upthe Darlington-connected outputtransistors Q21 and Q22, bringingthe OUT pin high. For faster outputswitching times, Q15’s collector cur-rent flows into the Q17/Q18/Q20current mirror. Q20’s collector cur-rent helps turn off Q23, whereas thecollector current of Q18 helps turnoff Q19.

Linear Technology’s6GHz ComplementaryBipolar TechnologyLinear Technology’s 6GHz comple-mentary bipolar technology (6GHzComBi) features vertical NPN and PNPtransistors with similar frequencyresponse and gain characteristics.Both the NPN and PNP transistorsfeature polysilicon emitters forimproved gain, a collector-to-emitterbreakdown voltage (BVCEO) greaterthan 12V and a unity gain frequency(fT) of 6GHz. The PNP transistors havea nominal current gain (β) of about45, while the NPNs have a β ofabout 100.

In addition to the transistors, the6GHz ComBi technology includesdiode, resistor and capacitor struc-tures. Schottky barrier diodes withlow parasitic capacitance and highbreakdown voltage are included forhigh speed voltage clamping andbreakdown protection of transistors.Low parasitic capacitance polysiliconresistors are included for use in highspeed signal paths. High resistivitydiffused resistors are used for biasingand low power circuitry. Polysilicon-oxide-metal capacitors offer lowparasitic capacitance, high capaci-tance density and low series resistancefor good high frequency performance.

When compared to a typical 30Vcomplementary bipolar process, thereduction of transistor BVCEO from30V to 12V has many benefits forapplications that do not require highersupply voltages. Dramatically reduceddepletion widths within the transis-tor allow a 50% decrease in area. Thisarea reduction improves speed bylowering parasitic capacitances asso-ciated with the transistor. The reducedvoltage requirement also allows a thin-ner, richer epitaxial (epi) region. Thischange to the epi region dramaticallyreduces the collector resistance of thetransistors, resulting in smaller

AN70 F51

–

+LT1394

5V

390Ω

200pF * 1% FILM RESISTOR ** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz

5V

FREQUENCY OUTPUT

3.9k* VIN 0V TO 5V

1M

MV-209 VARACTOR

DIODE

2k

2k

100pF

15pF

Y1**

100pF

CSELECT 0.05µF (SEE TEXT)

1M

1M1M*

1N4148 LT1004-2.5

47k*

1k*

Figure 2. A 4× NTSC subcarrier voltage tunable crystal oscillator; tuning range and bandwidthaccommodate a variety of phase-locked loops.

Linear Technology Magazine • May 199822

DESIGN FEATURES

INPUT VOLTAGE (V)0

FREQ

UENC

Y DE

VIAT

ION

(kHz

)

2 4 5

9

8

7

6

5

4

3

2

1

0

AN70 F52

1 3

14.3140MHz

14.31818MHz

14.3217MHz

AN70 F55

–

+LT1394

4.7k

5V

5V

Q5 2N2222

82Ω

4.7µF

1000pF

1k

INPUT 0V TO 2.5V

FREQUENCY OUTPUT

LT1004-2.5

8pF

10pF†

1M

+

* 1% FILM RESISTOR † POLYPROPYLENE, 5%

= 1N4148

= 2N2369 UNLESS NOTED

= 1N5712

= 74HC04

82pF

10k

10k 15k*

Q3

Q4

Q1

Q2

Q

Q

Figure 3. Control voltage vs output frequencyfor Figure 2; tuning deviation from the centerfrequency exceeds ±240ppm.

Figure 4. This simple charge pump–based 10MHz voltage-to-frequency converter has 40dBdynamic range and operates from a 5V supply.

–

+A2

1/2 LT1126

–

+

5V

5V

200pF

OUTPUT

AN70 F60

+INPUT

–INPUT

–5V

–5V

1µF

1µF

200pF

2k

1k

1k

2k10k

10k

200Ω

–

+A1

LM733 A = 100 –

+

LT1394

A3 1/2 LT1126

–

+

Figure 5. Waveforms for the 10MHz voltage-to-frequencyconverter; charge pump–based feedback provides linearityand fast response to input.

Figure 6. Parallel preamplified paths allow 18ns response to 500µVoverdrive.

transistors for a given current level.With this significant reduction in tran-sistor size, interconnects using a singlemetallization layer becomes muchmore difficult and would generatesignificant parasitic capacitance.Because of this, the 6GHz ComBiprocess uti l izes two levels ofmetallization.

Applications

4× NTSC Voltage-TunableCrystal OscillatorThe first of three representativeapplications for the LT1394 can beseen in Figure 2. This circuit is acrystal oscillator with voltage tuningof the output frequency. This applica-tion makes use of the LT1394’s highspeed, complementary outputs andsingle-supply 5V operation. Such volt-age controlled crystal oscillators(VCXO) are often employed whereslight variation of a stable carrier isrequired. This example is specificallyintended to provide a 4× NTSC sub-carrier tunable oscillator suitable forphase locking.

The resistors at the LT1394’s posi-tive input set a DC bias point of840mV. The 2kΩ– 200pF path sets upphase-shifted negative feedback, put-ting the DC output in the active regionwith a gain of 35 at the oscillationfrequency. The crystal’s path pro-vides resonant positive feedback andstable oscillation occurs. The varac-tor diode is biased from the tuninginput. The tuning network is arranged

so that a 0V to 5V drive provides areasonably symmetric, broad tuningrange around the 14.31818MHz cen-ter frequency. The capacitor labeledCSELECT sets the tuning bandwidth. Itshould be picked to complement loopresponse in phase-locking applica-tions. Figure 3 is a plot of frequencydeviation versus tuning input voltage.Tuning deviation from the 4× NTSC14.31818MHz center frequency ex-

A= 0.1V/DIV

B = 2V/DIV

C = 1V/DIV

D = 10mA/DIV

20ns/DIV

Linear Technology Magazine • May 1998 23

DESIGN FEATURES

Figure 7. 500µV input (Trace A) is split into wideband andlow frequency gain paths (Traces B and C) and recombined(Trace D). Trace E is the level-detector output.

Figure 8. Parallel-path level detector shows 18ns response(Trace B) to 500µV overdrive (Trace A).

ceeds ±240ppm for a 0V to 5V tuningrange.

Simple 10MHzSingle-Supply V/F ConverterA second application for the LT1394is shown in Figure 4. It is a simple10MHz single-supply voltage-to-fre-quency converter that makes use ofthe LT1394’s speed, single-supplyoperation and complementary out-puts. A 0V to 2.5V input produces a0Hz to 10MHz output with 40dB ofdynamic range, 1% linearity and 400ppm/°C gain drift. Power supplyrejection is 0.5% for 4.75V to 5.25Vsupply excursions.

To understand circuit operation,assume the LT1394’s positive inputis slightly below its negative input.The circuit’s input voltage causes apositive-going ramp at the com-parator’s positive input (Trace A,Figure 5). The Q output is low, forcingthe CMOS inverter outputs high. Thisallows current flow from diode Q1’scollector, through the CMOS invertersupply pin, to the 10pF capacitor. The4.7µF capacitor provides high fre-quency bypass, maintaining lowimpedance at Q1’s collector. Diodeconnected Q3 provides a path toground. The voltage to which the 10pFcapacitor charges is a function ofQ1’s collector potential and Q3’s drop.When the ramp at the comparator’spositive input goes high enough, theQ output goes high and the paralleledinverters switch low (Trace B). Thisaction pulls current from the 82pF

capacitor at the input via the Q1–10pF route (Trace D). This currentremoval resets the LT1394’s positiveinput ramp to a potential slightlybelow ground, forcing the Q outputlow and the paralleled inverters high.The 8pF capacitor at the LT1394’sinverting output furnishes AC posi-tive feedback to the negative input(Trace C). This ensures that the Qoutput remains high long enough fora complete discharge of the 10pFcapacitor. The Schottky diode pre-vents the LT1394’s input from beingdriven outside its negative commonmode limit. When the 8pF capacitor’sfeedback decays, the LT1394 againswitches and the entire cycle repeats.The oscillation frequency dependsentirely upon the input-derived cur-rent. The LT1004 is the circuit’svoltage reference, with Q1 and Q2temperature compensating Q3 andQ4.

Start-up or overdrive can causethe circuit’s AC-coupled feedback tolatch. If this occurs, the LT1394’soutput goes high, causing the paral-leled inverters to go low. After a timedetermined by the 1MΩ–1000pF RC,the associated lone inverter goes high.This lifts the LT1394’s negative inputand grounds the positive input withQ5, initiating normal circuit action.

To calibrate this circuit, apply 2.5Vand adjust the 10k potentiometer fora 10MHz output.

18ns 500µV Level DetectorThe ultimate limitation on compara-tor sensitivity is available gain.Unfortunately, increasing gain invari-ably involves giving up speed. Thegain vs speed trade-off in fast com-parators is usually a practicalcompromise designed to satisfy mostapplications. Some situations, how-ever, require more sensitivity (that is,higher gain) with minimal effect onspeed. Figure 6’s circuit adds a differ-ential preamplifier ahead of theLT1394, increasing gain. This permits500µV comparisons in 18ns. A paral-lel-path DC stabilization approacheliminates preamplifier drift as anerror source. A1 is the differentialamplifier, operating at a gain of 100.Its output is AC coupled to the LT1394.A1 has poorly defined DC character-istics, necessitating some form of DCcorrection. A2 and A3, operating at adifferential gain of 100, provide thisfunction. They differentially sense aband-limited version of A1’s inputsand feed DC and low frequencyamplified information to the compara-tor. The low frequency roll-off of A1’ssignal path complements A2–A3’s highfrequency roll-off. The summation ofthese two signal channels at theLT1394’s inputs results in flatresponse from DC to high frequency.

Figure 7 shows waveforms for thehigh sensitivity level detector. Trace Ais a 500µV overdrive on a 1mV stepapplied to the circuit’s positive input(negative input grounded). Trace Bshows the resulting amplified step atA1’s positive output. Trace C is A2’s

A = 1mV/DIV

B = 0.1V/DIV(AC-COUPLED)

C = 0.1V/DIV

D = 0.1V/DIV

E = 5V/DIV

5µs/DIV

A = 1mV/DIV

B = 1V/DIV

10ns/DIV

Linear Technology Magazine • May 199824

DESIGN FEATURES

RESPONSE TIME (ns)15

OVE

RD

RIV

E (µ

V)

1100

1000

900

800

700

600

50016 17 18

AN70 F68

Figure 9. Response time vs overdrive forthe composite level detector

band-limited output. A1’s widebandoutput combines with A2’s DC-cor-rected information to yield the correct,amplified composite signal at theLT1394’s positive input in Trace D.The LT1394’s output is Trace E. Fig-ure 8 details circuit propagation delay.The output responds in 18ns to a500µV overdrive on a 1mV step. Fig-ure 9 plots response time versusoverdrive. As might be expected,propagation delay decreases at higheroverdrives. A1’s noise limits usablesensitivity.

ConclusionInnovative circuit design, coupledwith Linear Technology’s 6GHzcomplementary bipolar processsimultaneously achieves the seem-ingly contradictory goals of high speedand low power. The LT1394 is easy touse, thanks to its single-supplycapability and complementary out-puts. Additional LT1394 applicationsappear in the forthcoming LinearTechnology Application Note, A SevenNanosecond Comparator for SingleSupply Operation.

CODE

0–1.0

UNIP

OLAR

INL

ERRO

R (L

SB)

–0.5

0

0.5

1.0

512 1024 1536 2048

1401_06c. EPS

2560 3072 3584 4096

Figure 6c. LTC1404 INL error

ApplicationsThe LTC1401 and LTC1404 will findapplications in telecommunications,digital signal processing, portable-computer data acquisition boards andhigh speed or multiplexed dataacquisition.

In telecommunication applicationssuch as HDSL (high-bit-rate digitalsubscriber line interface), high speedand low power dissipation are a mustbecause the systems are usually pow-ered by the phone line itself. Excellentdynamic performance is required ofthe ADC’s sample-and-hold. The serialinterface minimizes the number ofsignal lines that must be routed,thereby saving significant board

space. The 600ksps LTC1404, withits SO-8 footprint, is an excellentchoice for HDSL applications. At584ksps, with 2B1Q coding, theLTC1404 receives at 2.048Mbps overtwo wires.

Another common use of ADCs is indata acquisition applications. Sys-tem designers have always facedproblems in optimizing data acquisi-tion applications for speed, size, powerand cost, especially in the case ofportable designs. The high samplerate, the high level of functional inte-gration and the low cost of theseconverters make them ideal choicesfor these applications. The LTC1401

FREQUENCY (kHz)0

–120

BIPO

LAR

AMPL

ITUD

E (d

B)

–100

–80

–60

–40

–20

0

60 120 180 240

1401_06a.EPS

300

fSAMPLE = 600kHz fIN = 298.68kHz SINAD = 71dB THD = –84dB

CODE

0–1.0

UNIP

OLAR

DNL

ERR

OR (L

SB)

–0.5

0

0.5

1.0

512 1024 1536 2048

1401_06b.EPS

2560 3072 3584 4096

Figure 6a. LTC1404 FFT Figure 6b. LTC1404 DNL error

and LTC1404 can be easily interfacedto a low cost MUX (for example, aCD4051, 74HC4051 or LTC1391)through their high impedance inputs.The high input impedance of theseADCs eliminates the need for a bufferbetween the MUX and the ADC,resulting in savings of both cost andboard space.

ConclusionThe new LTC1401 and LTC1404 comewith full ADC performance and aneasy-to-use serial interface. Thesecomplete, stand alone, high speed,low power devices will simplify the jobof system designers.

LTC1401/LTC1404, continued from page 19

Linear Technology Magazine • August 199830

DESIGN INFORMATION

IntroductionInstrumentation, waveform genera-tion, data acquisition, feedbackcontrol systems and other applicationareas are beginning to utilize 16-bitdata converters. More specifically, 16-bit digital-to-analog converters (DACs)have seen increasing use. New com-ponents (see the sidebar “Componentsfor 16-Bit Digital-to-Analog Conver-sion” on page 31) have made 16-bitDACs a practical design alternative.These ICs provide 16-bit performanceat reasonable cost compared to previ-ous modular and hybrid technologies.The DC and AC specifications of themonolithic DACs approach or equalprevious converters at significantlylower cost.

DAC Settling TimeDAC DC specifications are relativelyeasy to verify. Measurement tech-niques are well understood, albeit oftentedious. AC specifications requiremore sophisticated approaches toproduce reliable information. In par-ticular, the settling time of the DACand its output amplifier is extraordi-narily difficult to determine to 16-bitresolution. DAC settling time is theelapsed time from input code applica-tion until the output arrives at and

Component and MeasurementAdvances Ensure 16-Bit DACSettling Time (Part One) by Jim Williams

remains within a specified error bandaround the final value. It is usuallyspecified for a full-scale 10V transi-tion. Figure 1 shows that DAC settlingtime has three distinct components.The delay time is very small and isalmost entirely due to propagationdelay through the DAC and outputamplifier. During this interval there isno output movement. During slewtime the output amplifier moves at itshighest possible speed towards thefinal value. Ring time defines the regionwhere the amplifier recovers fromslewing and ceases movement withinsome defined error band. There isnormally a trade-off between slewand ring time. Fast-slewing amplifi-ers generally have extended ring times,complicating amplifier choice and fre-quency compensation. Additionally,the architecture of very fast amplifi-ers usually dictates trade-offs thatdegrade DC error terms.

Measuring anything at any speedto 16 bits (≈0.0015%) is hard. Dynamicmeasurement to 16-bit resolution isparticularly challenging. Reliable16-bit settling-time measurement con-stitutes a high order difficulty problemrequiring exceptional care in approachand experimental technique.

Considerations for MeasuringDAC Settling TimeHistorically, DAC settling time hasbeen measured with circuits similarto that in Figure 2. The circuit usesthe “false sum node” technique. Theresistors and DAC-amplifier form abridge-type network. Assuming idealresistors, the amplifier output willstep to VIN when the DAC inputs moveto all ones. During slew, the settlenode is bounded by the diodes, limit-ing voltage excursion. When settlingoccurs, the oscilloscope probe voltageshould be zero. Note that the resistordivider’s attenuation means theprobe’s output will be one-half of theactual settled voltage.

In theory, this circuit allows settlingto be observed to small amplitudes. Inpractice, it cannot be relied upon toproduce useful measurements. Theoscilloscope connection presentsproblems. As probe capacitance rises,AC loading of the resistor junctioninfluences observed settling wave-forms. A 10pF probe alleviates thisproblem but its 10× attenuation sac-rifices oscilloscope gain. 1× probesare not suitable because of theirexcessive input capacitance. An active

DAC INPUT (ALL BITS)

DAC OUTPUT

AN74 F01

SETTLING TIME

SLEW TIME

RING TIME

ALLOWABLE OUTPUT ERROR BAND

DELAY TIME

DIGITAL INPUTS

REF

DAC

0V TO 10V TRANSITION

SETTLE NODE

INPUT FROM

PULSE GENERATOR

R

AN74 F02

R

INPUT STEP TO OSCILLOSCOPE

OUTPUT TO OSCILLOSCOPE

DIGITAL INPUTS

–VREF

–

+

OUTPUT AMPLIFIER

FB

Figure 2. Popular summing scheme for DAC-settling-time measurement provides misleadingresults. 16-bit measurement causes >200× oscilloscope overdrive. Displayed information ismeaningless.

Figure 1. DAC-settling-time componentsinclude delay, slew and ring times. Fastamplifiers reduce slew time, althoughlonger ring time usually results. Delaytime is normally a small term.

Linear Technology Magazine • August 1998 31

DESIGN INFORMATION

1× FET probe will work, but anotherissue remains.

The clamp diodes at the settle nodeare intended to reduce swing duringampl ifier s lewing, pr event ingexcessive oscilloscope overdrive.Unfortunately, oscilloscope overdriverecovery characteristics vary widelyamong different types and are notusually specified. The Schottky diodes’400mV drop means the oscilloscopemay see an unacceptable overload,bringing displayed results intoquestion.

At 10-bit resolution (10mV at theDAC output—5mV at the oscillo-scope), the oscilloscope typicallyundergoes a 2× overdrive at 50mV/DIV and the desired 5mV baseline isjust discernible. At 12-bit or higherresolution, the measurement becomeshopeless with this arrangement.Increasing oscilloscope gain bringscommensurate increased vulnerabil-ity to overdrive induced errors. At 16bits, there is clearly no chance ofmeasurement integrity.

The preceding discussion indicatesthat measuring 16-bit settling timerequires a high gain oscilloscope thatis somehow immune to overdrive. Thegain issue is addressable with anexternal wideband preamplifier thataccurately amplifies the diode-clamped settle node. Getting aroundthe overdrive problem is more difficult.

The only oscilloscope technologythat offers inherent overdrive immu-nity is the classical sampling ’scope.

DIGITAL INPUTS

REF

DAC

SETTLE NODE SWITCH

INPUT FROM

PULSE GENERATOR

R

AN74 F03

R

INPUT STEP TO OSCILLOSCOPE

OUTPUT TO OSCILLOSCOPE

OUTPUT AMPLIFIER

PREAMPLIFIER

DIGITAL INPUTS

–VREF

–

+

DELAYED PULSE GENERATOR

FB

Figure 3. Conceptual arrangement eliminates oscilloscope overdrive. A delayed pulse generator controlsthe switch, preventing the oscilloscope from monitoring settle node until settling is nearly complete.

Components for16-Bit D/A ConversionComponents suitable for 16-bit D/Aconversion are members of an eliteclass. 16 binary bits is one part in65,536—just 0.0015% or 15 parts-per -million. This mandates avanishingly small error budget andthe demands on components are high.The digital-to-analog converters listedin Table A all use Si-Chrome thin-

epyTtnenopmoCnoitubirtnoCrorrEC°07otC°0revO stnemmoC

CAD7951CTL tfirDniaGBSL2≈≈ ytiraeniLBSL1

stupnIlellaraPlluFstuptuOtnerruC

CAD5951CTL tfirDniaGBSL2≈≈ ytiraeniLBSL1

tupnIlaireSegakcaPniP-8tuptuOtnerruC

CAD0561CTLtfirDniaGBSL5.3≈

≈ tesffOBSL6≈ ytiraeniLBSL4

CADtuptuOegatloVetelpmoC

reifilpmA1001TL BSL1< eciohCdeepSwoLdooGytilibapaCtuptuOAm01

reifilpmA2101TL BSL1< eciohCdeepSwoLdooGnoitpmusnoCrewoPwoL

reifilpmA8641TL BSL2< stiB61otgniltteSsµ7.1elbaliavAtsetsaF

V59.6:ecnerefeRA991ML BSL1≈ ecnerefeRtfirDtsewoLpuorGsihtni

V01:ecnerefeR1201TL BSL4≈ eciohCesopruPlareneGdooG

V5:ecnerefeR7201TL BSL4≈ eciohCesopruPlareneGdooG

V01:ecnerefeR6321LT BSL01≈ %50.0otdemmirTycaruccAetulosbA

V690.4:ecnerefeR1641TL BSL01≈ 0561CTLrofdednemmoceR)evobAees(sCAD

Table A. Short-form descriptions of components suitable for 16-bit digital-to-analog conversion

film resistors for high stability andlinearity over temperature. Gain driftis typically 1ppm/°C or about 2LSBsover 0°C to 70°C. The amplifiers showncontribute less than 1LSB error over0°C to 70°C with 16-bit DAC drivensettling times of 1.7µs available. Thereferences offer drifts as low as 1LSBover 0°C to 70°C with initial trimmedaccuracy to 0.05%

Linear Technology Magazine • August 199832

DESIGN INFORMATION

Unfortunately, these instruments areno longer manufactured (although stillavailable on the secondary market). Itis possible, however, to construct acircuit that borrows the overloadadvantages of classical sampling’scope technology. Additionally, thecircuit can be endowed with featuresparticularly suited for measuring 16-bit DAC settling time.

Practical DAC-Settling-Time MeasurementFigure 3 is a conceptual diagram of a16-bit DAC-settling-time measure-ment circuit. This figure sharesattributes with Figure 2, althoughsome new features appear. In thiscase, the preamplified oscilloscope isconnected to the settle point by aswitch. The switch state is deter-mined by a delayed pulse generator,which is triggered from the same pulsethat controls the DAC. The delayedpulse generator’s timing is arrangedso that the switch does not close untilsettling is very nearly complete. Inthis way the incoming waveform issampled in time, as well as ampli-tude. The oscilloscope is neversubjected to overdrive—no off-screenactivity ever occurs.

Figure 4 is a more complete repre-sentation of the DAC settling timescheme. Figure 3’s blocks appear in

greater detail and some new refine-ments show up. The DAC-amplifiersumming area is unchanged. Figure3’s delayed pulse generator has beensplit into two blocks; a delay and apulse generator, both independentlyvariable. The input step to the oscillo-scope runs through a section thatcompensates for the propagation delayof the settling-time-measurementpath. The most striking new aspect ofthe diagram is the diode bridge switch.Borrowed from classical samplingoscilloscope circuitry, it is the key tothe measurement. The diode bridge’sinherent balance eliminates charge-

injection-based errors in the output.It is far superior to other electronicswitches in this characteristic. Anyother high speed switch technologycontributes excessive output spikesdue to charge-based feedthrough. FETswitches are not suitable because theirgate-channel capacitance permitssuch feedthrough. This capacitanceallows gate-drive artifacts to corruptthe oscilloscope display, inducing over-load and defeating the switch’s purpose.

The diode bridge’s balance, com-bined with matched, low capacitance,monolithic diodes and complementaryhigh speed switching, yields a cleanly

Figure 5. Diode bridge switch trims include AC and DC balance and switch drivetiming skew. Remaining diodes in monolithic array are used for temperature control.

ON V+

OFF V–

V– ON

V+

OFF

SKEW COMPENSATION

OUTPUT

AC BALANCE

DC BALANCE

AN74 F05

INPUT

SENSE

BRIDGE TEMPERATURE

CONTROL

HEAT

–

+V+

ALL DIODES = CA3039 MONOLITHIC ARRAY

DIGITAL INPUTS

REF

DAC0V TO 10V TRANSITION

SETTLE NODE

INPUT FROM

PULSE GENERATOR

R

AN74 F04

R

TIME CORRECTED INPUT STEP TO OSCILLOSCOPE

OUTPUT TO OSCILLOSCOPE 0.01V/DIV = 500µV/DIV AT DAC AMPLIFIER OUTPUT

OUTPUT AMPLIFIER

SAMPLING BRIDGE DRIVER

SAMPLING BRIDGE SWITCH

DIGITAL INPUTS

–VREF

–

+ RESIDUE AMPLIFIER

BRIDGE SWITCHING CONTROL

VARIABLE DELAY

DELAYED PULSE GENERATOR

BRIDGE DRIVER/RESIDUE AMPLIFIER DELAY COMPENSATION

VARIABLE WIDTH PULSE GENERATOR

SAMPLING BRIDGE TEMPERATURE

CONTROL

×40×1

FB

Figure 4. Block diagram of DAC-settling-time measurement scheme: diode bridge switch minimizes switchingfeedthrough, preventing residue-amplifier oscilloscope overdrive. Temperature control maintains 10µV switchoffset baseline. Input step-time reference is compensated for ×1 and ×40 amplifier delays.

Linear Technology Magazine • August 1998 33

DESIGN INFORMATION

switched output. The monolithic diodebridge is also temperature controlled,providing a bridge offset error below10µV, stabilizing the measurementbaseline. The temperature control isimplemented using uncommitteddiodes in the monolithic array as heaterand sensor.

Figure 5 details considerations forthe diode bridge switch. The bridgediodes tend to cancel each other’s tem-perature coefficient—unstabilizedbridge drift is about 100µV/°C and thetemperature control reduces residualdrift to a few microvolts/°C.

Bridge temperature control isachieved by using one diode as a sen-sor. Another diode, running in reversebreakdown (VZ ≈ 7V), serves as theheater. The control amplifier, compar-ing the sensor diode to a voltage at itsnegative terminal, drives the heaterdiode to temperature stabilize the array.

DC balance is achieved by trimmingthe bridge on-current for zero input–output offset voltage. Two AC trims arerequired. The “AC balance” corrects fordiode and layout capacitive imbalancesand the “skew compensation” correctsfor any timing asymmetry in the nomi-

nally complementary bridge drive.These AC trims compensate smalldynamic imbalances that could resultin parasitic bridge outputs.

ConclusionThis concludes part one of this article.Part two, which will appear in theNovember issue of Linear Technologymagazine, details the settling time cir -cuitry and presents results. Both partsrepresent a distillation of a full-lengthLTC application note, AN74, Compo-nent and Measurement AdvancesEnsure 16-Bit DAC Settling Time.

New 16-Bit Bipolar Output DAC inNarrow SO-16 Package by Hassan Malik

Linear Technology introduces itsfirst bipolar, voltage output 16-bitdigital to analog converter, theLTC1650. The LTC1650 is availablein a narrow 16-pin SO package, mak-ing it the smallest bipolar, 16-bitvoltage output DAC on the markettoday. The LTC1650 operates from± 5V supplies and draws 5mA. It isequipped with a rail-to-rail, low noise,deglitched output amplifier that canbe configured to operate in a unipolaror bipolar mode. The mid-scale glitchis under 2nV-s and the full-scalesettling time in unipolar mode is 4µs.

The LTC1650 is 16-bit monotonicover the industrial temperature range,

with a typical differential nonlinear-ity of less than ±0.3LSB. Figures 1and 2 show a typical application forthe part and its DNL curve. TheLTC1650 is equipped with an output-span-setting resistor tied to the UNI/BIP pin. When this pin is tied to theVOUT pin, the output will swing fromREFLO to REFHI; when the pin is tiedto REFHI, the output swings from–REFHI to REFHI.

The LTC1650 has a user-definedvoltage to which its output resets onpower-up or when the part is cleared.The voltage on the VRST pin is appliedto the output through a transmissiongate when the part powers up or is

cleared. There are supply brown-outdetectors on all three supplies, AVDD,DVDD and AVSS. When any of thesesupplies drops below 2.5V, the part iscleared, connecting the output to VRST,and the RSTOUT pin changes to alogic low.

The 3-wire serial interface of theLTC1650 is SPI/QSPI and MICRO-WIRE™ compatible. All the logicinputs are TTL/CMOS compatible andthe CLK input is equipped with aSchmitt trigger that allows direct op-tocoupler interfacing. There is also aDOUT pin for daisy-chaining severalDACs. The digital feedthrough is0.05nV-s.MICROWIRE is a trademark of National SemiconductorCorp.

Figure 1. LTC1650 block diagramFigure 2. The LTC1650 bipolar output DAChas ±0.3LSB typical DNL.

–

+

16-BIT DAC

16-B

IT D

AC R

EGIS

TER

16-B

IT S

HIFT

REG

ISTE

R

POWER-ON RESET SUPPLY SENSE

CLR

VRST

AVDD

5VRSTOUT

VOUT

UNI/BIP

REFLODGND 1650 TA01

108

7

5

6

12,13

4.096V5V

–5V

CS/LD

CLK

DIN

DOUT

REFHI11 15

9

2

1

16

4AVSS

14

DVDD3

CODE0

–1.0

DNL

ERRO

R (L

SB)

–0.8

–0.4

–0.2

0

1.0

0.4

16384 32768

1650 TA02

–0.6

0.6

0.8

0.2

49152 65535

Linear Technology Magazine • November 1998 31

DESIGN INFORMATION

Component and MeasurementAdvances Ensure 16-Bit DACSettling Time (Part Two) by Jim Williams

IntroductionReliable measurement of 16-bit DACsettling time is extremely challeng-ing. Part one of this article (in theAugust 1998 issue of Linear Technol-ogy magazine) described a method formaking this measurement. This sec-ond part discusses detailed circuitryand presents results.

DetailedSettling-Time CircuitryFigure 1 is a detailed schematic of the16-bit DAC settling-time-measure-ment circuitry. The input pulse

switches all DAC bits simultaneouslyand is also routed to the oscilloscopevia a delay-compensation network.The delay network, composed ofCMOS inverters and an adjustableRC network, compensates theoscilloscope’s input step signal forthe 12ns delay through the circuit’smeasurement path. The DACamplifier’s output is compared againstthe LT1236-10V reference via the pre-cision 3k summing resistor ratio set.

The LT1236 also furnishes the DACreference, making the measurementratiometric. The clamped settle nodeis unloaded by A1, which drives thesampling bridge. Note the additionalclamp diodes at A1’s output. Thesediodes prevent any possibility ofabnormal A1 outputs (due to lostsupply or supply sequencing anoma-lies) from damaging the diode array.A3 and associated components tem-

+

7

11 D5

AC BALANCE

2.5kRESIDUE

AMPLIFIER

OUTPUT TO OSCILLOSCOPE 0.01V/DIV = 500µV/DIV AT DAC AMPLIFIER OUTPUT

SAMPLING BRIDGESAMPLING BRIDGE

TEMPERATURE CONTROL

108

4

14

1.1k

Q1

Q4

11

1013

8

7

9 6Q3

5pF

3pF

0.1µF 10µF

510Ω

D633Ω*

1.3k*

Q2

D7

CA3039 ARRAY121 13

–5V

–5V

–5V

SKEW COMP 2.5k

3

2 5

2.2k1.1k

5V

15V15V

–15V

–5V

1k

0.01µF

2.2k 10µF 0.1µF

470Ω

560Ω

51Ω820Ω 51Ω680Ω

500Ω BASELINE

ZERO

62Ω

HEAT

SENSE

: 74HC04

: 1N4148

SAMPLING BRIDGE AND TEMPERATURE CONTROL DIODES: HARRIS CA3039M (800) 442-7747 *1% FILM RESISTOR **VISHAY VHD-200, RATIO SET: 10ppm MATCHING D7 TO D9: 1N5711 Q1, Q2: MRF-501 Q3, Q4: LM3045 ARRAY USE IN-LINE COAXIAL 50Ω TERMINATOR FOR PULSE GENERATOR INPUT. DO NOT MOUNT 50Ω RESISTOR ON BOARD DERIVE 5V AND –5V SUPPLIES FROM ±15V. USE LT317A FOR 5V, LT1175-5 FOR –5V CONSTRUCTION IS CRITICAL—SEE TEXT

Q5 2N2219

1.5k* (SELECT— SEE TEXT)

10k*

10k*

–

+A2

LT1222

–

+A3

LT1012

0.1µF 10µF+

+

VCC RC1

5k

5VWIDTH

SAMPLE DELAY/ WINDOW GENERATOR

5V

5V

74HC123

5V

4.7k

4.7k

20k DELAY

1000pF

5.1k

C1 Q1 Q2 CLR2 B2 A2

A1 B1 CLR1 Q1 Q2 C2 RC2 GND

470pF

AN74 F06

5.1k

REF

5V

15V

LT1236-10

OUTNC IN

47µF TANT0.1µF

510Ω

–10VREF

GNDSAMPLING

BRIDGE DRIVER

SETTLE NODE3k**

–15V

15V

–15V

–15V

DUT LTC1597

CCOMP (SELECT— SEE TEXT)

0V TO 10V TRANSITION

TIME CORRECTED INPUT STEP TO OSCILLOSCOPE

–

+

15pF

1k

5VPULSE

GENERATOR INPUT

50Ω IN-LINE TERMINATION (SEE TEXT AND NOTES)

BRIDGE DRIVER/RESIDUE AMPLIFIER DELAY COMPENSATION ≈12ns AUT

LT1468+

3k**

D8 D9

–

+

A1 LT1220

SAMPLING BRIDGE SWITCHING CONTROL

Figure 1. Detailed schematic of DAC-settling-time measurement circuit; optimum performance requires attention to layout.

Linear Technology Magazine • November 199832

DESIGN INFORMATION

perature control the sampling diodebridge by comparing a diodes’s for-ward drop to a stable potential derivedfrom the –5V regulator. Another diode,operated in the reverse direction (VZ ≈7V) serves as a chip heater. The pinconnections shown on the schematichave been selected to provide the besttemperature-control performance.

The input pulse triggers the74HC123 one shot. The one shot isarranged to produce a delayed (con-trollable by the 20k potentiometer)pulse whose width (controllable bythe 5k potentiometer) sets diode bridgeon-time. If the delay is set appropri-ately, the oscilloscope will not see anyinput until settling is nearly complete,eliminating overdrive. The samplewindow width is adjusted so that allremaining settling activity is observ-able. In this way, the oscilloscope’soutput is reliable and meaningful datamay be taken. The one shot’s output

is level shifted by the Q1–Q4 transis-tors, providing complementaryswitching drive to the bridge. Theactual switching transistors, Q1–Q2,are UHF types, permitting true differ-ential bridge switching with less than1ns of time skew.

A2 monitors the bridge output,provides gain and drives the oscillo-scope. Figure 2 shows circuitwaveforms. Trace A is the input pulse,trace B the DAC amplifier output,trace C the sample gate and trace Dthe residue amplifier output. Whenthe sample gate goes low, the bridgeswitches cleanly and the last 1.5mVof slew are easily observed. Ring timeis also clearly visible and the ampli-fier settles nicely to final value. Whenthe sample gate goes high, the bridgeswitches off, with only 600µV of feed-through. The 100µV peak beforebridge switching (at ≈3.5 vertical divi-

sions) is feedthrough from A1’s out-put, but it is similarly well controlled.Note that there is no off-screen activ-ity at any time—the oscilloscope isnever subjected to overdrive.

The circuit requires trimming toachieve this level of performance. Thebridge temperature control point isset by grounding Q5’s base prior toapplying power. Next, apply powerand measure A3’s positive input withrespect to the –5V rail. Select theindicated resistor (1.5k nominal) for avoltage at A3’s negative input (again,with respect to –5V) that is 57mVbelow the positive input’s value.Unground Q5’s base and the circuitwill control the sampling bridge toabout 55°C:

25°C ROOM +

= 30°C RISE = 55°C

57mV 1.9mV/°C DIODE DROP

A = 10V/DIV

B = 10V/DIV

C = 10V/DIV

D = 500µV/DIV

1µs/DIV 1µs/DIV

B = 10V/DIV

A = 10V/DIV

C = 500µV/DIV

Figure 2. Settling time circuit waveforms include time-correctedinput pulse (Trace A), DAC amplifier output (Trace B), sample gate(Trace C) and settling-time output (Trace D). The sample gatewindow’s delay and width are variable.

Figure 3. Settling time circuit’s output (Trace C) with unadjustedsampling bridge AC and DC trims. The DAC is disabled and thesettle node grounded for this test. Excessive switch-drivefeedthrough and baseline offset are present. Traces A and B arethe input pulse and sample window, respectively.

1µs/DIV

B = 10V/DIVA = 10V/DIV

C = 500µV/DIV

B = 500µV/DIV

1µs/DIV

A = 10V/DIV

Figure 5. Oscilloscope display with inadequate sample gatedelay: the sample window (Trace A) occurs too early,resulting in off-screen activity in the settle output (Trace B).The oscilloscope is overdriven, making displayedinformation questionable.

Figure 4. The settling time circuit’s output (Trace C) with thesampling bridge trimmed. As in Figure 3, the DAC is disabled and thesettle node grounded for this test. Switch drive feedthrough andbaseline offset are minimized. Traces A and B are the input pulseand sampling gate, respectively.

Linear Technology Magazine • November 1998 33

DESIGN INFORMATION

The DC and AC bridge trims aremade once the temperature control isfunctional. Making these adjustmentsrequires disabling the DAC andamplifier (disconnect the input pulsefrom the DAC and set all DAC inputslow) and shorting the settle nodedirectly to the ground plane. Figure 3shows typical results before trimming.Trace A is the input pulse, trace B thesample gate and trace C the residueamplifier output. With the DAC-amplifier disabled and the settle nodegrounded, the residue amplifier out-put should (theoretically) always bezero. The photo shows this is not thecase for an untrimmed bridge. AC andDC errors are present. The samplegate’s transitions cause large, off-screen residue amplifier swings (noteresidue amplifier’s response to thesample gate’s turn-off at the ≈8.5 ver-tical division). Additionally, the residueamplifier output shows significant DCoffset error during the sampling inter-val. Adjusting the AC balance and

skew compensation minimizes theswitching induced transients. The DCoffset is adjusted out with the base-line zero trim. Figure 4 shows theresults after making these adjust-ments. All switching-related activityis now well on-screen and offset erroris reduced to unreadable levels. Oncethis level of performance has beenachieved, the circuit is ready for use.Unground the settle node and restorethe input pulse connection to the DAC.

Using the Sampling-BasedSettling Time CircuitFigures 5 through 7 underscore theimportance of positioning the sam-pling window properly in time. InFigure 5 the sample gate delay ini-tiates the sample window (trace A) tooearly and the residue amplifier’soutput (trace B) overdrives the oscil-loscope when sampling commences.Figure 6 is better, with only slight off-screen activity. Figure 7 is optimal.

All amplifier residue is well inside thescreen boundaries.

In general, it is good practice to“walk” the sampling window up to thelast millivolt or so of amplifier slewingso that the onset of ring time isobservable. The sampling basedapproach provides this capability andit is a very powerful measurementtool. Additionally, remember thatslower amplifiers may requireextended delay and/or sampling win-dow times. This may necessitate largercapacitor values in the 74HC123 one-shot timing networks.

CompensationCapacitor EffectsThe DAC amplifier requires frequencycompensation to get the best possiblesettling time. The DAC has appreciableoutput capacitance, complicatingamplifier response and making care-ful compensation capacitor selectioneven more important. Figure 8 showseffects of very light compensation.

1µs/DIV

A = 10V/DIV

B = 500µV/DIV

1µs/DIV

A = 10V/DIV

B = 500µV/DIV

Figure 7. Optimal sample-gate delay positions thesampling window (Trace A) so that all settle output(Trace B) information is well inside screen boundaries.

Figure 6. Increasing the sample-gate delay positionsthe sample window (Trace A) so settle output (TraceB) activity is on-screen.

500ns/DIV

A = 5V/DIV

B = 500µV/DIV

500ns/DIV

A = 5V/DIV

B = 500µV/DIV

Figure 9. Excessive feedback capacitanceoverdamps response (tSETTLE = 3.3µs).

Figure 8. This settling profile with inadequate feedbackcapacitance shows underdamped response. Excessive ringingfeeds through during the sample gate off-period (third through ≈sixth vertical divisions) but is tolerable (tSETTLE = 2.8µs).

Linear Technology Magazine • November 199834

DESIGN INFORMATION

Trace A is the time-corrected inputpulse and trace B the residue ampli-fier output. The light compensationpermits very fast slewing but excessiveringing amplitude over a protractedtime results. The ringing is so severethat it feeds through during a portionof the sample gate off-period, althoughno overdrive results. When samplingis initiated (just prior to the sixthvertical division) the ringing is seen tobe in its final stages, although still

offensive. Total settling time is about2.8µs. Figure 9 presents the oppositeextreme. Here, a large value compen-sation capacitor eliminates all ringingbut slows down the amplifier so muchthat settling stretches out to 3.3µs.The best case appears in Figure 10.This photo was taken with the com-pensation capacitor carefully chosenfor the best possible settling time.Damping is tightly controlled and set-tling time goes down to 1.7µs.

Settling Timesof Various AmplifiersThe previous results, using theLT1468 amplifier, provide extremelyfast settling times with high accuracyover temperature. Many applicationscan tolerate reduced speed, reducedtemperature stability or both. Set-tling times for a number of amplifiers,along with commentary, can be foundin LTC Application Note 74, Figure34. “Optimized” settling times wererecorded after individually trimmingthe feedback capacitors. The “con-servative” times represent theworst-case settling times using stan-dard-value compensation capacitorswith no trimming.

ConclusionThe sampling-based settling-time cir-cuit appears to be a very usefulmeasurement solution. Expanded dis-cussion and tutorial appear in thisarticle’s “root” publication: LTCApplication Note 74, Component andMeasurement Advances Ensure 16-Bit DAC Settling Time.

500ns/DIV

B = 500µV/DIV

A = 5V/DIV

Figure 10. Optimal feedback capacitance yields a tightlydamped signature and the best settling time (tSETTLE = 1.7µs).

Net1 and Net2 Serial Interface ChipSet Supports Test Mode by David Soo

Some serial networks use a test modeto exercise all of the circuits in theinterface. The network is divided intolocal and remote data terminalequipment (DTE) and data-circuit-terminating equipment (DCE), asshown in Figure 1. Once the networkis placed in a test mode, the local DTEwill transmit on the driver circuitsand expect to receive the same sig-nals back from either a local or remoteDCE. These tests are called local orremote loopback.

As introduced in the February 1998issue of Linear Technology, theLTC1543/LTC1544/LTC1344A chipset has taken the integrated approach

to multiple protocol. By using thischip set, the Net1 and Net2 designwork is done. The LTC1545 extendsthe family by offering test mode capa-bility. By replacing the 6-circuitLTC1544 with the 9-circuit LTC1545,the optional circuits TM (Test Mode),RL (Remote Loopback) and LL (LocalLoopback) can now be implemented.

Figure 2 shows a typical applica-tion using the LTC1543, LTC1545and LTC1344A. By just mapping thechip pins to the connector, the designof the interface port is complete. Thechip set supports the V.28, V.35, V.36,RS449, EIA-530, EIA-530A or X.21protocols in either DTE or DCE mode.

Shown here is a DCE mode connec-tion to a DB-25 connector. Themode-select pins, M0, M1 and M2,are used to select the interface proto-col, as summarized in Table 1.

LOCAL DTE

LOCAL DCE LL REMOTE

DCERL REMOTE

DTE

5451CTL/3451CTLemaNedoM 2M 1M 0M

desUtoN 0 0 0

A035-AIE 0 0 1

035-AIE 0 1 0

12.X 0 1 1

53.V 1 0 0

63.V/944SR 1 0 1

82.V/232SR 1 1 0

elbaCoN 1 1 1

Table 1. Mode pin functions

Figure 1. Serial network

Linear Technology Magazine • September 1999 35

DESIGN IDEAS

SMBus Controlled CCFL Power Supplyby Jim Williams

Figure 1 shows a cold cathode fluo-rescent lamp (CCFL) power supplythat is controlled via the popularSMBus interface. The LT1786 CCFLswitching regulator receives theSMBus instruction. The IC convertsthis instruction to a current, whichappears at the IOUT pin. This current,routed to the ICCFL pin, provides a setpoint for switching regulator opera-tion. The resultant duty cycle at theVSW pin pulls current through L2. L2,acting as a switched current sink,drives a resonant Royer convertercomposed of Q1–Q2, C1 and L1. Thehigh voltage sine wave produced at

L2’s secondary drives the floatinglamp.

Current flow into the Royer con-verter is monitored by the IC at pin 13(“Royer” in Figure 1).1 Royer currentcorrelates tightly with lamp current,which, in turn, is proportional tointensity. The IC compares the Royercurrent to the SMBus-derived cur-rent, closing a lamp-intensity controlloop. The SMBus permits wide-rangeregulated lamp-intensity control andallows complete IC shutdown. Opti-mal display and lamp characteristicspermit 90% efficiency. The circuit iscalibrated by correlating SMBus

instruction codes with attendant RMSlamp current. Detailed informationon circuit operation and measure-ment techniques appears in thereferences below.

BAT8V TO 28V

16

15

14

13

12

11

10

9

ICCFL

DIO

CCFL VC

AGND

SHDN

SMBSUS

ADR

CCFL VSW

BULB

BAT

ROYER

VCC

IOUT

SCL

SDA

CCFLPGND

LT1786F

LAMP

10 6

L1

R1750Ω

L2100µH

3 2 1 54

+

+

C7, 1µF

C1*0.068µF

C51000pF

R2220k

R3100k

C3A2.2µF35V

C42.2µF

3V ≤ VCC≤ 6.5V

TOSMBusHOST

C3B2.2µF35V

C227pF3kV

+

Q2* Q1*SHUTDOWN

C1 MUST BE A LOW LOSS CAPACITOR, C1 = WIMA MKI OR MKP-20(914) 347-2474

= PANASONIC ECH-U(201) 348-7522

Q1, Q2 = ZETEX ZTX849

OR ROHM 2SC5001

0µA TO 50µA ICCFL CURRENT GIVES 0mA TO 6mA LAMP CURRENT FOR A TYPICAL DISPLAY.

FOR ADDITIONAL CCFL/LCD CONTRAST APPLICATION CIRCUITS, REFER TO THE LT1182/83/84/84F DATA SHEET

D1BAT85

1

2

3

4

5

6

7

8D1

1N5818

L1 = COILTRONICS CTX210605

L2 = COILTRONICS CTX100-4

*DO NOT SUBSTITUTE COMPONENTS

COILTRONICS (561) 241-7876

(516) 543-7100

(800) 955-7646

Figure 1. 90% efficient floating CCFL with 2-wire SMBus lamp-current control

References:1. Williams, Jim. Linear Technology

Application Note 65: A FourthGeneration of LCD BacklightTechnology. November 1995.

2. LT1786F Data Sheet. LinearTechnology Corp. 1998.

1 Local historians can’t be certain, but this may bethe only IC pin ever named after a person.

Analog Inputs WelcomeThe scaleable amplification systemdetailed in Figure 4 can be drivenwith analog inputs while still main-taining full isolation. Such a systemis detailed in Figure 5, where theanalog input is filtered (to preventailiasing) and converted to PWM. Fig-ure 5 goes on to show the use of an

RS485 differential driver to drive atwisted pair line. The receiver end ofthe twisted pair line is terminatedwith a resistor and put across theisolation barrier. This provides verygood ESD protection on both ends ofthe line.

ConclusionThe LT1684 is useful in a wide varietyof applications. The LT1684 is a highlyintegrated solution for use in anysystem that requires digital control ofhigh output voltage or high outputpower.

Ring Tone, continued from page 29

Linear Technology Magazine • November 1999 27

DESIGN IDEAS

Cost and Space Efficient Backlightingfor Small LCD Panels by Jim Williams

A generation of small, portable,“palmtop” computing devices hasrecently appeared. These productshave small LCD displays that usecold cathode fluorescent lamps(CCFLs) for backlighting. These lampsrequire high voltage AC current drive.Circuitry for this purpose should bephysically small, cost effective andelectrically efficient.

Figure 1 shows a design that meetsthe above criteria. The configurationis a current-fed resonant Royerconverter driven by an LT1317Bmicropower switching regulator. TheLT1317B effects a switch-mode cur-

rent sink, supplying the requiredRoyer drive to close a loop at the FBpin. This path includes the lamp anda filter network that rectifies T1’shigh voltage AC output into DC. Inthis case, the circuit’s operating point,and hence, the lamp current, is set bya potentiometer. Operating-pointvariation can also be achieved byvoltage controlling the optional in-put, indicated on the schematic.1 Withthe components shown, size is about10mm (W) by 5mm (H) by 40mm (L).The Shutdown pin facilitates circuitturnoff, although removing powerfrom the VIN pin has similar results.

The closed loop operation yieldsexcellent line regulation while ensur-ing that lamp currents never violateminimum or maximum values. Thesecharacteristics allow operationdirectly from the battery withoutintensity variation, flicker or shorten-ing of lamp life. Simplicity, lowcomponent count, small size and costeffectiveness make this circuit anexcellent choice for “palmtop” LCDillumination.

1 Those finding this description intolerably briefare directed to LTC Application Note 65, wherethis circuit receives more scholarly attention.

VIN

SHDN

VSW

FB

VC GND

LT1317B

+

+

Q1 Q20.15µF*750Ω

1 5 4 3 2

6 10LAMP

T1

L1100µH

22k

MMB-0914

DIMMING0V–3V

(OPTIONAL)

10k

0.1µF 820Ω**

2k1µF

10µF

V+(3V–9V TYP)

MBR0520

T1: TOKO BLC210(408) 432-8281

L1: SUMIDA CD43-100(847) 956-0666

Q1, Q2: ZETEX ZDT-1048 (DUAL)(516) 543-7100

* WIMA MKI(914) 347-2474

** 1% FILM RESISTOR† MOTOROLA

(800) 441-2447DO NOT SUBSTITUTECOMPONENTS

BAV-99†

SHUTDOWN

3

2 1

Figure 1. Palmtop computer LCD backlight supply

For more information on parts featured in this issue, seehttp://www.linear-tech.com/go/ltmag

For more information on parts featured in this issue, seehttp://www.linear-tech.com/go/ltmag

DESIGN IDEASCost and Space EfficientBacklighting for Small LCD Panels................................................... 27

Jim Williams

High Efficiency PolyPhase ConverterCombines Power from Multiple Inputs................................................... 28

Wei Chen and Craig Varga

Isolated RS485 TransceiverBreaks Ground Loops .................. 29Mitchell Lee

Sharp Gain Roll-Offs Using theLTC1562 Quad Operational Filter IC(Part 3) ........................................ 31Nello Sevastopoulos

Using the LT1719 Comparator forLow Dispersion Sine Wave toSquare Wave Conversion ............. 34Joseph G. Petrofsky

Linear Technology Magazine • December 200236

DESIGN IDEAS

Many single supply powered applica-tions require amplifier output swingswithin millivolt or even sub-millivoltlevels of ground. Amplifier outputsaturation limitations normallypreclude such operation. Figure 1’spower supply bootstrapping schemeachieves the desired characteristicswith minimal component addition.

Bootstrapped Power Supply PermitsSingle Rail Amplifier Output Swing toGround (and Below) by Jim Williams

A1, a chopper stabilized amplifier,has a clock output. This outputswitches Q1, providing drive to thediode-capacitor charge pump. Thecharge pump output feeds A1’s V–

terminal, pulling it below zero, per-mitting output swing to (and below)ground. If desired, the negative out-put excursion can be limited by eitherclamp option shown.

Reliable start-up of this boot-strapped power supply scheme is avalid concern, warranting investiga-tion. In Figure D2, the amplifier’s V–

pin (Trace C) initially rises at supplyturn-on (Trace A) but heads negativewhen amplifier clocking (Trace B) com-mences at about midscreen.

The circuit provides a simple wayto obtain output swing to zero volts,permitting a true “live at zero” output.

Figure 2. Amplifier bootstrapped supply start-up. Amplifier V– pin (trace C) initially risespositive at 5V supply (trace A) turn-on. Whenamplifier internal clock starts (trace B, 5thvertical division), charge pump activates,pulling V– pin negative.

5ms/DIV

A5V/DIV

B5V/DIV

C0.2V/DIV

–

+

Q12N3904

10µF

10µF

39k

100k

1k

5V

1k

≈ –3.5VHERE

V –

V +

5V

A1LTC1150

CLKOUT

100Ω

+

+

DASHED LINE CIRCUITRY = CLAMP OPTIONS. SEE TEXT

= BAT85

Figure 1. Single rail powered amplifier has true zero volt output swing. A1’s clock outputswitches Q1, driving diode-capacitor charge pump. A1’s V– pin assumes negative voltage,permitting zero (and below) volt output swing.

20µA. The SHDN pin can easily beconfigured to provide a supply under-voltage lockout (UVLO) function.

Protection features include cur-rent limiting, which facilitates startupinto a high capacitance load; andcross conduction prevention circuitry,which keeps the two switches frombeing on simultaneously.

The LT3439 is available in a ther-mally enhanced 16-pin TSSOP withexposed underside metal.

Low Noise Step-up ConverterProduces ±15V at 100mAfrom a 5V InputFigure 1 shows a design that providesregulated ±15V at 100mA outputsfrom a 5V±5% input. Output ripple isless than 150µV or 0.001% of VOUTmeasured at full load. Efficiency ofthe supply is approximately 71%measured at full load.

The LT1964-BYP and the LT1761-BYP linear regulators regulate theoutput to within 0.1% of nominal overthe full line and load range.

ConclusionThe LT3439 DC Transformer Drivergreatly simplifies the design of effi-cient low noise isolated powersupplies. By reducing a major sourceof the EMI with voltage and currentslew control, designs using theLT3439 avoid expensive shielding andfiltering requirements and save thecost and time incurred by multipleiterative layouts.

LTC3439, continued from page 35

For more information on parts featured in this issue, seehttp://www.linear.com/go/ltmag

For more information on parts featured in this issue, seehttp://www.linear.com/go/ltmag

38 Linear Technology Magazine • September 200538

DESIGN IDEAS

biased, 1A, 0.5Hz square wave load applied to the battery. The battery’s internal resistance causes a 0.5Hz amplitude modulated square wave to appear at the Kelvin-sensed, S2-S3-A2 synchronous demodulator. The demodulator DC output is buffered by chopper stabilized A2, which provides the circuit output. A2’s internal 1 kHz clock, level shifted by Q2, drives the CD4040 frequency divider. One divider output supplies the 0.5Hz square wave; a second 500Hz output activates a charge pump, providing a –7V potential to A2. This arrangement allows A2’s output to swing all the way to zero volts.

The circuit pulls 230µA from its 9V battery power supply, permitting about 3000 hours battery life. Other specifications include operation down to 4V with less than 1mV (0.001Ω) output variation, 3% accuracy and battery-under-test range of 0.9V–13V. Finally, note that battery discharge current and repetition rate are easily varied from the values given, permit-ting observation of battery resistance under a variety of conditions.

via Q1’s drain. The 1N5821 provides reverse battery protection.

The voltage across the 0.1Ω resis-tor, and hence the battery load, is determined by A1’s “+” input voltage. This potential is alternately switched, via S1, between 0.110V and 0.010V derived from the 2.5V reference driven 3-resistor string. S1’s 0.5Hz square wave switching drive comes from the CD4040 frequency divider. The result of this action is a 100mA

Determine the Real Internal Resistance of a BatteryIntroductionAn accurate measure of a battery’s true internal resistance can reveal much about its condition or its suitability for an application, but measurement is not as easy as hooking up a preci-sion ohmmeter. Inherent capacitance of a battery reduces the accuracy of measurements taken with a common AC-based milliohmmeters operating in the kHz range. Figure 1, a very simplistic battery model, shows a resistive divider with a partial shunt capacitive term. This capacitive term introduces error in AC based measure-ment. Also, the battery’s unloaded internal resistance can significantly differ from its loaded value. A realistic determination of internal resistance must be made under loaded conditions at or near DC.

Figure 2’s circuit meets these requirements, permitting accurate internal resistance determination of batteries up to 13V over a range of 0.001Ω to 1.000Ω. A1, Q1 and associ-ated components form a closed loop current sink which loads the battery

by Jim Williams

–

+

LTC17982.5V

15

6

14

7

9

5

1

2

16

13

4

3

0.001µF

2.7kS1

S2

S3

2.5VOUT

9VIN

A1LT1077

–

+A2

LTC1150

10k

10k

10k237k

1%

10k1%

1k1%

0.010V

0.110V

9V

9V9V

9V

9V

Q1IRLR-024

0.1Ω1%

SWITCHEDCURRENT SINK

–

+BATTERYUNDERTEST

SENSE

SENSE

FORCE

FORCE

1µF1µF

10µF

10µF

1µF

NC

1N5821

1

V–

OUTPUT0 – 1.000V =0 – 1.000Ω

200pF

200k

100k

≈1kHz SQUARE WAVE

≈0.5Hz SQUARE WAVE≈ –7VCD4040

÷2048÷2 R

BAT85

BAT85

+VCLK

Q22N3904

FREQUENCYDIVIDER AND

CHARGE PUMP

MODULATOR

SYNCRONOUSDEMODULATOR

LTC6943

SINGLE POINT GND AT 0.1Ω RESISTOR = LTC6943 PIN NUMBERHEAT SINK Q1

#

Figure 2. Battery internal resistance is determined by repetitively stepping calibrated discharge current and reading resultant voltage drop. S1 based modulator, clocked from frequency divider, combines with A1-Q1 switched current sink to generate stepped, 1A battery discharge cycles. S2-S3-A2 synchronous demodulator extracts modulated voltage drop information, provides DC output calibrated in Ohms.

INTERNALIMPEDANCETERMS

USERTERMINALS

Figure 1. Simplistic model shows battery impedance terms include resistive and capacitive elements. Capacitive component corrupts AC based measurement attempts to determine internal DC resistance. More realistic results occur if battery voltage drop is measured under known load.

Linear Technology Magazine • March 2006 3939

DESIGN IDEAS L

Figure 1’s circuit combines the 5V rail-to-rail performance of the LTC6241 with a pair of extremely low noise JFETs configured in a chopper based carrier modulation scheme to achieve extraordinarily low noise and DC drift. This circuit’s performance suits the demanding transducer sig-nal conditioning situations such as high resolution scales and magnetic search coils.

The LTC1799’s output is divided down to form a 2-phase 925Hz square wave clock. This frequency, harmonically unrelated to 60Hz, pro-vides excellent immunity to harmonic beating or mixing effects which could cause instabilities. S1 and S2 receive complementary drive, causing the A1-based stage to see a chopped version of the input voltage. A1’s square wave output is synchronously demodulated by S3 and S4. Because these switches

are synchronously driven with the input chopper, proper amplitude and polarity information is presented to DC output amplifier A2. This stage integrates the square wave into a DC voltage, providing the output. The out-put is divided down (R2 and R1) and fed back to the input chopper where it serves as a zero signal reference. Gain, in this case 1000, is set by the

R1-R2 ratio. Because the input stage is AC coupled, its DC errors do not affect overall circuit characteristics, resulting in the extremely low offset and drift noted.

Figure 2, noise measured over a 50 second interval, shows 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is attributed to the input JFET’s die size and current density. L

40nVP–P Noise, 0.05µV/°C Drift, Chopped FET Amplifier by Jim Williams

HORIZ = 5s/DIV

VERT = 20nV/DIV

Figure 2. Noise measures 40nVP–P in 50s sample period

+

–

+

–

BIAS

10M

1µF

1µF

141516

32

1

S4S3 240k

1µF

OUTPUTA2

LTC6241HV

A1LTC6241HV

1µF

INPUT

10k

8

7

11

S1S2

9

6

10

R210k

R110Ω

NOISEOFFSET

DRIFT

OPEN-LOOP GAINI

= 40nVP-P 0.1Hz TO 10Hz= 1µV= 0.05µV/°C R2 R1= 10= 150pA

+1GAIN =9

0.001µF

0.47µF

100k

Ø1

Ø1

Ø2

Ø2

= 0.1% METAL FILM RESISTOR= 1% METAL FILM RESISTOR

***

= LTC201 QUAD

= LSK389= LINEAR INTEGRATED SYSTEMS FREMONT, CA

1µF

DIVRSET

LTC1799

V +

74C90 ÷ 10

18.5kHz

OUT 74C74 ÷ 2

TOØ1

POINTS

TOØ2

POINTS

Q Q

54.2k*

TO LTC201 V+ PIN

5V

5V –5V

5V 5V

925Hz

TO LTC201 V – PIN

1µF

909Ω**

5V

–5V

909Ω**

LSK3893k

499Ω**

+

+

100k

Figure 1. 40nV noise chopper amplifier

34 Linear Technology Magazine • September 200634

L DESIGN IDEAS

by Jim Williams

Waveforms for the circuit include the AC coupled output (Figure 3, trace A), C1’s output (trace B) and Q1’s drain flyback events (trace C). When the output drops below 5V, C1 goes low, turning on Q1. Q1’s resultant flyback events continue until the 5V output is restored. This pattern repeats, main-taining the output.

The 5V output can supply up to 2mA, sufficient to power circuitry or supply bias to a higher power switch-ing regulator when more current is required. The circuit will start into loads of 300µA at 300mV input; 2mA loading requires a 475mV supply. Figure 4 plots minimum input volt-age vs output current over a range of loads.

J-FET-Based DC/DC Converter Starts and Runs from 300mV SupplyA J-FET’s self-biasing characteristic can be utilized to construct a DC/DC converter powered from as little as 300mV. Solar cells, thermopiles and single stage fuel cells, all with out-puts below 600mV, are typical power sources for such a converter.

Figure 1, an N-channel J-FET I-V plot, shows drain-source conduction under zero bias (gate and source tied together) conditions. This property can be exploited to produce a self-starting DC/DC converter that runs from 0.3V to 1.6V inputs.

Figure 2 shows the circuit. Q1 and T1 form an oscillator with T1’s second-ary providing regenerative feedback to Q1’s gate. When power is applied, Q1’s gate is at zero volts and its drain conducts current via T1’s primary. T1’s phase inverting secondary responds by going negative at Q1’s gate, turning it off. T1’s primary current ceases, its secondary collapses and oscilla-tion commences. T1’s primary action causes positive going “flyback” events

at Q1’s drain, which are rectified and filtered. Q2’s approximately 2V turn-on potential isolates the load, aiding start-up. When Q2 turns on, circuit output heads towards 5V. C1, powered from Q2’s source, enforces output regulation by comparing a portion of the output with its internal voltage reference. C1’s switched output con-trols Q1’s on-time via Q3, forming a control loop.

MIN

IMUM

INPU

T VO

LTAG

E TO

MOU

NTAI

N V O

UT =

5V

(V)

OUTPUT CURRENT (µA)20000

0.6

0400 800 1200 1600

0.1

0.2

0.4

0.3

0.5 WITH QUIESCENT CONTROLCIRCUITRY (FIGURE 5)

WITHOUT QUIESCENT CONTROLCIRCUITRY (FIGURE 2)

Figure 4. J-FET based DC/DC converter of Figure 2 starts and runs into 100µA load at VIN = 275mV. Regulation to 2mA is possible, although required VIN rises to 500mV. Quiescent current control circuitry of Figure 5 slightly increases input voltage required to support load at VIN < 500mV.

A0.1V/DIV

AC COUPLED

B5V/DIV

C5V/DIV

5ms/DIV

Figure 3. J-FET based DC/DC converter waveforms. When supply output (trace A) decays, C1 (trace B) switches, allowing Q1 to oscillate. Resultant flyback events at Q1 drain (trace C) restore supply output.

–

+

+

VIN0.3V TO 1.6V

VOUT5V2mA

100Ω

3.83M*

1.21M*

0.01µF

0.001µF

+100µF6.8µF

Q2TP-0610L

Q1

3

6

5

7

Q3VN2222L

BAT85

T1

C1LTC1440

T1: COILTRONICS VP-1-1400 TIE WINDINGS (1,12)(2,4) (8,10)(9,11)*1% METAL FILM RESISTORQ1: PHILIPS BF-162, 2 DEVICES IN PARALLEL

1N5817

1.18V REF OUT

Figure 2. J-FET based DC/DC converter runs from 300mV input. Q1-T1 oscillator output is rectified and filtered. Load is isolated until Q2 source arrives at approximately 2V, aiding start-up. Comparator and Q3 close loop around oscillator, controlling Q1’s on-time to stabilize 5V output.

10mA/DIV

100mV/DIV

Figure 1. Zero volt biased JFET I-V curve shows 10mA conduction at 100mV, rising above 40mA at 500mV. Characteristic enables construction of DC/DC converter powered from 300mV supply.

Linear Technology Magazine • September 2006 3535

DESIGN IDEAS L

–

+

+

VIN0.3V TO 1.6V

VOUT5V2mA

51Ω

3.83M*

470k

1.21M*

0.01µF

+

+

100µF

1µF

6.8µF

Q2TP-0610L

Q1

Q4

3

6

5

7

Q3VN2222L

6.8V1N4692

T1

C1LTC1440

T1: COILTRONICS VP-1-1400 TIE WINDINGS (1,12)(2,4) (8,10)(9,11) * 1% METAL FILM RESISTOR Q1, Q4: PHILIPS BF-162, Q1 IS 2 DEVICES IN PARALLEL 1N4148

1N5817

1.18V REF OUT

10M

1M

Figure 5. Adding Q3, Q4 and bootstrapped negative bias generator reduces quiescent current. Comparator directed Q3 switches Q4, more efficiently controlling Q1’s gate drive. Q2 and zener diode isolate all loading during Q1 start-up.

Q3’s shunt control of Q1 is simple and effective, but results in a 25mA quiescent current drain. Figure 5’s modifications reduce this figure to 1mA by series switching T1’s secondary. Here, Q3 switches series-connected Q4, more efficiently controlling Q1’s gate drive. Negative turn-off bias for Q4 is bootstrapped from T1’s sec-ondary; the 6.8V zener holds off bias supply loading during initial power application, aiding start-up. Figure 4 shows minimal penalty imposed by the added quiescent current control circuitry. L

until the positive side reaches 87% of its final voltage. The output disconnect is also designed so that both channels can collapse together gently when the chip is shut down.

Output DisconnectIn a standard boost regulator, the inductor and Schottky diode provide a DC current path from the input to the output, even when the regulator is shut down. Any load at the output when the chip is shut down can continue to drain the VIN source. The LT3487 addresses this issue with an on-chip output disconnect. The output dis-connect is a PNP pass transistor that eliminates the DC loss path. The pass transistor is controlled by a circuit that varies its base current to keep it at the edge of saturation, yielding the best compromise between voltage drop

across the PNP and quiescent current. The disconnect in the LT3487 can support loads of 50mA with a VCE of less than 210mV.

VBAT PinThe VBAT pin is an innovation that allows output disconnect operation in a wide range of applications. VBAT monitors the voltage at the input of the boost inductor and allows the positive output to stay active until the CAP node falls to 1.2V above VBAT. This ensures that output disconnect continues op-erating even after the part goes into shutdown. Since output disconnect continues to work, the positive output doesn’t fall sharply to ground before the negative bias discharges. The VBAT pin allows the inductors to be powered from a different source than VIN while still maintaining the discon-nect operation. This can be useful in

a system using a 2-cell supply where a low voltage boost provides 3.3V for the VIN supply. By connecting VBAT as well as the inductors to the 2-cell supply, the positive output is able to stay on as long as possible when the part goes into shutdown.

ApplicationsThe LT3487 can be used in a CCD bias as well as other applications that require a positive and negative bias such as ±12V data acquisition systems. The boost channel can pro-duce voltages up to 30V as long as the part can meet the required duty cycle. Similarly, the inverting channel can produce voltages down to –30V. This high voltage capability allows the LT3487 to be used in many LCD applications.

ConclusionThe LT3487 simplifies and shrinks CCD bias supplies without compro-mising on performance or features. The soft-start and output disconnect features ensure that the input battery doesn’t encounter current spikes or shutdown leakage. The high current capability satiates even the most pow-er-hungry video applications. L

VRUN/SS2V/DIV

IIN1A/DIV

VPOS10V/DIV

VNEG10V/DIV

500µs/DIV

Figure 3. Startup without soft-start capacitor

VRUN/SS2V/DIV

IIN200mA/DIV

VPOS10V/DIV

VNEG10V/DIV

10ms/DIV

Figure 4. Startup with 100nF soft-start capacitor

LT3487, continued from page 13

forthe latest information

on LTC products, visit

www.linear.com

Linear Technology Magazine • June 2007 4141

DESIGN IDEAS L

Quartz crystal RMS operating cur-rent is critical to long-term stability, temperature coefficient and reliability. Accurate determination of RMS crys-tal current, especially in micropower types, is complicated by the necessity to minimize introduced parasitics, particulary capacitance, which corrupt crystal operation.

Figure 1’s high gain, low noise amplifier combines with a commer-cially available closed core current

probe to permit the measurement. An RMS-to-DC converter supplies the RMS value. The quartz crystal test circuit shown in dashed lines exemplifies a typical measurement situation. The Tektronix CT-1 current probe monitors crystal current while introducing minimal parasitic loading. The probe’s 50Ω terminated output is fed to A1. A1 and A2 take a closed loop gain of 1120; excess gain over a nominal gain of 1000 corrects for the

CT-1’s 12% low frequency gain error at 32.768kHz.1 A3 and A4 contribute a gain of 200, resulting in total amplifier gain of 224,000. This figure results in a 1V/µA scale factor at A4 referred to the gain corrected CT-1’s output. A4’s LTC1563-2 bandpass filtered output feeds an LTC1968-based RMS-to-DC converter (A5), which provides the circuit’s output. The signal processing path constitutes an extremely narrow band amplifier tuned to the crystal’s

Sub-µA RMS Current Measurement for Quartz Crystals by Jim Williams

–

+

–

+

1.5k*

49.9Ω*

–

+

1740Ω*

39Ω(SEE TEXT)

49.9Ω*

39pF

A1LT1028

A2LT1222

–

+

825Ω*

61.9Ω*

A3LT1222

–

+

825Ω*

63.4Ω*

A4LT1222

–

+C1

LTC1440

A5LT1077

1µF

5V

2V

2V

5V

–5V

–5V

A = 1120 (CT-1 GAIN ERROR AT 32.768kHz ≈ 12%, SEE TEXT)

A = 200

A = 224,000

1k

LTC1563-2

GND

V+

LPB

INVB

SB

SA

EN

LP

INVA

LPA

V–

5V

5V

RMS-TO-DC CONVERTER

32.7kHz BANDPASS FILTER

CRYSTAL OSCILLATOR TEST CIRCUIT

84.5k*

42.2k*

20k*

2M

1M

21k*

24.9k*5.62k*

43k

LTC1968

V+

E G

OUT

R

I1

I2

10k10k

1µF

10pF

10µF

0.01µF

0.1µF

10µF

OUT0V–1V = 0µA–1µA

EPSON C-100Rf = 32.768kHz

1.2M

TEKTRONIX CT-1CURRENT PROBE5mV/mA (5µV/µA)

*1% METAL FILM RESISTOR10µF, 1µF CAPACITORS = WIMA MKS-2

Figure 1. Op amps A1–A4 furnish gain of > 200,000, permitting sub-µA crystal current measurement. The LTC1563-2 bandpass filter smooths residual noise while providing unity gain at 32.768kHz. The LTC1968 RMS-to-DC converter supplies RMS calibrated output.

42 Linear Technology Magazine • June 200742

L NEW DEVICE CAMEOS

frequency. Figure 2 shows typical cir-cuit waveforms. Crystal drive, taken at C1’s output (trace A), causes a 530nA RMS crystal current, which is repre-sented at A4’s output (Trace B) and the RMS-to-DC converter input (Trace C). Peaking visible in Trace B’s unfiltered

presentation derive from inherent and parasitic paths shunting crystal.

Typical circuit accuracy is 5%. Uncertainty terms include the trans-former’s tolerances, its approximately 1.5pF loading and resistor/RMS-to-DC converter error. Calibrating the

circuit reduces error to less than 1%. Calibration involves driving the transformer with 1µA at 32.7kHz. This is facilitated by biasing a 100k, 0.1% resistor with an oscillator set at 0.1V output. The output voltage should be verified with an RMS voltmeter hav-ing appropriate accuracy. Figure 1 is calibrated by padding A2’s gain with a small resistive correction, typically 39Ω.LNotes

1 The validity of this gain error correction at one sinusoidal frequency—32.768kHz—was investi-gated with a 7-sample group of Tektronix CT-1s. Device outputs were collectively within 0.5% of 12% down for a 1.00µA, 32.768kHz sinusoidal input current. Although this tends to support the measurement scheme, it is worth noting that these results are as measured. Tektronix does not guarantee performance below the specified –3dB, 25kHz low frequency roll-off.

A2V/DIV

B1µA/DIV

C1µA/DIV

10µs/DIV

Figure 2. The 32.768kHz output of the crystal oscillator (Trace A) and crystal current monitored at A4 output (Trace B) and the RMS-to-DC converter input (Trace C). Peaks in Trace B’s unfiltered waveform derive from inherent and parasitic paths shunting the crystal.

New Device CameosHigh Voltage Dual Input Li-Ion Battery ChargerThe LTC4075HVX is a standalone linear charger that is capable of charging a single-cell Li-Ion/Polymer battery from both wall adapter and USB inputs. The charger can detect power at the inputs and automatically select the appropriate power source for charging.

No external sense resistor or block-ing diode is required for charging due to the internal MOSFET architecture. The LTC4075HVX features a maximum 22V rating for both wall adapter and USB inputs although charging stops if the selected power source exceeds the overvoltage limit (typical 6V). Internal thermal feedback regulates the battery charge current to maintain a constant die temperature during high power operation or high ambient temperature conditions. The float voltage is fixed at 4.2V and the charge current is pro-grammed with an external resistor. The LTC4075HVX terminates the charge cycle when the charge current drops below the programmed termination threshold after the final float voltage is reached.

Other features include automatic recharge, undervoltage lockout,

charge status outputs, and “power present” status outputs to indicate the presence of wall adapter or USB power. No trickle charge allows full current from the charger when a load is con-nected directly to the battery.

Small 1.8A Step-Down Regulator Switches at 4MHz for Space-Sensitive ApplicationsThe LTC3568 is a 10-lead DFN, syn-chronous, step-down, current mode, DC/DC converter, intended for me-dium power applications. It operates within a 2.5V to 5.5V input voltage range and switches at up to 4MHz, making it possible to use tiny capaci-tors and inductors that are under 1mm in height. The output of the LTC3568 is adjustable from 0.8V to 5V, and its 0.11Ω switches allows up to 1.8A of output current at high efficiency. By using the LTC3568 in a small 3mm × 3mm, 10-lead DFN package, a com-plete DC/DC converter can consume less than 0.3 square inches of board real estate.

Efficiency is extremely important in battery-powered applications, and the LTC3568 keeps efficiency high with an automatic, power saving Burst Mode

operation, which reduces gate charge losses at low load currents. With no load, the part only draws 60µA, and in shutdown, the device draws less than 1µA, making it ideal for low current applications.

The LTC3568 uses a current-mode, constant frequency architecture that benefits noise sensitive applications. Burst Mode operation is an efficient solution for low current applications, but sometimes noise suppression is a priority. To reduce noise problems, a pulse-skipping mode and a forced continuous mode are available, which decreases the ripple noise at low currents. Although not as efficient as Burst Mode operation at low cur-rents, pulse-skipping mode and forced continuous mode still provide high ef-ficiency for moderate loads. In dropout, the internal P-channel MOSFET switch is turned on continuously, thereby maximizing the usable battery life.

A Power Good output is available for power supply monitoring or for Power On Reset use. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output voltages are not within about ±7.5%.

The LTC3568’s small size, high efficiency, low component count and flexibility make it an ideal DC/DC converter for portable devices. L

34 Linear Technology Magazine • March 200934

L DESIGN IDEAS

This article is excerpted from the Linear Technology Application Note AN122 with the same title.

IntroductionMost circuit designers are familiar with diode dynamic characteristics such as charge storage, voltage dependent capacitance and reverse recovery time. Less commonly acknowledged and manufacturer specified is diode forward turn-on time. This parameter describes the time required for a diode to turn on and clamp at its forward volt-age drop. Historically, this extremely short time, units of nanoseconds, has been so small that user and vendor alike have essentially ignored it. It is rarely discussed and almost never specified. Recently, switching regula-tor clock rate and transition time have become faster, making diode turn-on time a critical issue. Increased clock rates are mandated to achieve smaller magnetics size; decreased transition times somewhat aid overall efficiency but are principally needed to minimize IC heat rise. At clock speeds beyond about 1MHz, transition time losses are the primary source of die heating.

A potential difficulty due to diode turn-on time is that the resultant

transitory “overshoot” voltage across the diode, even when restricted to nanoseconds, can induce overvoltage stress, causing switching regulator IC failure. As such, careful testing is required to qualify a given diode for a particular application to insure reli-ability. This testing, which assumes low loss surrounding components and layout in the final application, measures turn-on overshoot voltage due to diode parasitics only. Improper

associated component selection and layout will contribute additional over-stress terms.

Diode Turn-On Time PerspectivesFigure 1 shows typical step-up and step-down voltage converters. In both cases, the assumption is that the diode clamps switch pin voltage excursions to safe limits. In the step-up case, this limit is defined by the switch pins

Figure 1. Typical voltage step-up/step-down converters. Assumption is diode clamps switch pin voltage excursion to safe limits.

OUTPUTVREG

IC REGULATOR

REFGND

VIN SWITCH PIN

SWITCH

CONTROL

FEEDBACK NODE

+V

OUTPUTVREG

IC REGULATOR

REFGND

VIN

SWITCHPIN

SWITCH

CONTROL

FEEDBACK NODE

+V

STEP-UP STEP-DOWN

Diode Turn-On Time Induced Failures in Switching RegulatorsNever Has So Much Trouble Been Had by So Many with So Few Terminals

by Jim Williams and David Beebe

Figure 2. Diode forward turn-on time permits transient excursion above nominal diode clamp voltage, potentially exceeding IC breakdown limit.

AN122 F02DIODE TURN-ON TIME

DIODE ON VOLTAGE

IC BREAKDOWN LIMIT

AN122 F03

DIODEUNDERTEST

5ΩMEASUREMENT POINT

PULSE INtRISE ≤ 2nsAMPLITUDE = 5V + VFWD

Figure 3. Conceptual method tests diode turn-on time at 1A. Input step must have exceptionally fast, high fidelity transition.

Linear Technology Magazine • March 2009 3535

DESIGN IDEAS L

maximum allowable forward voltage. The step-down case limit is set by the switch pins maximum allowable reverse voltage.

Figure 2 indicates the diode requires a finite length of time to clamp at its forward voltage. This forward turn-on time permits transient excursions above the nominal diode clamp volt-age, potentially exceeding the IC’s breakdown limit. The turn-on time is typically measured in nanoseconds, making observation difficult. A further complication is that the turn-on over-shoot occurs at the amplitude extreme of a pulse waveform, precluding high resolution amplitude measurement. These factors must be considered when designing a diode turn-on test method.

Figure 3 shows a conceptual method for testing diode turn-on time. Here, the test is performed at 1A although other currents could be used. A pulse

steps 1A into the diode under test via the 5Ω resistor. Turn-on time volt-age excursion is measured directly at the diode under test. The figure

AN122 F05

LT1086

22µF22µF120Ω

1k

1k

+V ADJUST (RISE TIME TRIM)

+V TYPICAL 17VVIN = 20V

*

+V

Q1Q4

+V

Q2Q5

+V

Q3Q6

1Ω

1Ω

1Ω

5Ω**

OUTPUT62Ω50Ω

2pF TO 12pFEDGEPURITY

EDGE PURITY100Ω

PULSEINPUT

MINIMIZE INDUCTANCE IN ALL PATHS

= 2N3866

= 2N3375

** = TEN PARALLELED 50Ω RESISTORS* = BYPASS EVERY TRANSISTOR WITH 22µF SANYO OSCON PARALLELED WITH 2.2µF MYLAR

+ +

*

*

Figure 5. Pulse amplifier includes paralleled, darlington driven RF transistor output stage. Collector voltage adjustment (“rise time trim”) peaks Q4 to Q6 FT, input RC network optimizes output pulse purity. Low inductance layout is mandatory.

1V/DIV

2ns/DIV AN122 F06

Figure 6. Pulse amplifier output into 5Ω. Rise time is 2ns with minimal pulse-top aberrations.

AN122 F04

DIODEUNDERTEST

5Ω

OSCILLOSCOPE1GHz BANDWIDTH

tRISE = 350ps

PULSE CURRENTAMPLIFIERtRISE = 2ns

PULSE GENERATORtRISE < 1ns Z0 PROBE

≈1A

TYPICALLY5V TO 6V, 30nsWIDE

Figure 4. Detailed measurement scheme indicates necessary performance parameters for various elements. Subnanosecond rise time pulse generator, 1A, 2ns rise time amplifier and 1GHz oscilloscope are required.

36 Linear Technology Magazine • March 200936

L DESIGN IDEAS

AN12

2 F0

5

LT10

86

22µF

22µF

120Ω

1k 1k

+V A

DJUS

T (R

ISET

IME

TRIM

)

+V, T

YPIC

AL 1

7VV I

N =

20V

*

+V

Q1Q4

+V

Q2Q5

+V

Q3Q6

1Ω 1Ω 1Ω

5Ω**

DIOD

EUN

DER

TEST

62Ω

50Ω

2pF

TO 1

2pF

EDGE

PURI

TY

EDGE

PUR

ITY

100Ω

HP-2

15A

PULS

E GE

NERA

TOR

t RIS

E =

800p

sP W

IDTH

= 3

0ns

MIN

IMIZ

E IN

DUCT

ANCE

IN A

LL P

ATHS

=

2N3

866

=

2N3

375

** =

TEN

PAR

ALLE

LED

50Ω

RES

ISTO

RS*

= B

YPAS

S EV

ERY

TRAN

SIST

OR W

ITH

22

µF S

ANYO

OSC

ON P

ARAL

LELE

D W

ITH

2.

2µF

MYL

AR

ADJU

ST P

ULSE

GEN

ERAT

OR A

MPL

ITUD

E FO

R 5.

5V A

MPL

ITUD

E AT

5Ω

RES

ISTO

R

Z 0 P

ROBE

= T

EKTR

ONIX

P-

6056

, 500

Ω21

5A

≈ 6.7V

≈ 5.5V

7104

7A29

7B15

7B10

7A29

TEKT

RONI

X71

04/7

A29/

7B10

/7B1

51G

Hz (t

RISE

= 3

50ps

)OS

CILL

OSCO

PE

+

+

* *

Figu

re 7

. Com

plet

e di

ode

forw

ard

turn

-on

tim

e m

easu

rem

ent

arra

ngem

ent

incl

udes

sub

nano

seco

nd r

ise

tim

e pu

lse

gene

rato

r, p

ulse

am

plifi

er, Z

0 pr

obe

and

1GH

z os

cillo

scop

e.

Linear Technology Magazine • March 2009 3737

DESIGN IDEAS L

Figure 8. “Diode Number 1” overshoots steady state forward voltage for ≈3.6ns, peaking 200mV.

Figure 9. “Diode Number 2” peaks ≈750mV before settling in 6ns... > 2x steady state forward voltage.

200mV/DIV

2ns/DIV AN122 F08

200mV/DIV

2ns/DIV AN122 F09

Figure 12. “Diode Number 5” peaks offscale with extended tailing (note horizontal slower scale compared to Figures 8 thru 10).

200mV/DIV

5ns/DIV AN122 F12

Figure 10. “Diode Number 3” peaks 1V above nominal 400mV VFWD, a 2.5x error.

Figure 11. “Diode Number 4” peaks ≈750mV with lengthy (note horizontal 2.5x scale change) tailing towards VFWD value.

200mV/DIV

2ns/DIV AN122 F10

200mV/DIV

5ns/DIV AN122 F11

38 Linear Technology Magazine • March 200938

L DESIGN IDEAS

is deceptively simple in appearance. In particular, the current step must have an exceptionally fast, high-fidelity transition and faithful turn-on time determination requires substantial measurement bandwidth.

Detailed Measurement SchemeA more detailed measurement scheme appears in Figure 4. Necessary per-formance parameters for various elements are called out. A subnano-second rise time pulse generator, 1A, 2ns rise time amplifier and a 1GHz oscilloscope are required. These speci-fications represent realistic operating conditions; other currents and rise times can be selected by altering ap-propriate parameters.

The pulse amplifier necessitates careful attention to circuit configura-tion and layout. Figure 5 shows the amplifier includes a paralleled, Dar-lington driven RF transistor output stage. The collector voltage adjustment (“rise time trim”) peaks Q4 to Q6 FT; an input RC network optimizes output pulse purity by slightly retarding input pulse rise time to within amplifier passband. Paralleling allows Q4 to Q6

to operate at favorable individual cur-rents, maintaining bandwidth. When the (mildly interactive) edge purity and rise time trims are optimized, Figure 6 indicates the amplifier produces a transcendently clean 2ns rise time output pulse devoid of ringing, alien components or post-transition excur-sions. Such performance makes diode turn-on time testing practical.1

Figure 7 depicts the complete diode forward turn-on time measurement ar-rangement. The pulse amplifier, driven by a sub-nanosecond pulse generator, drives the diode under test. A Z0 probe monitors the measurement point and feeds a 1GHz oscilloscope.2, 3, 4

Diode Testing and Interpreting ResultsThe measurement test fixture, prop-erly equipped and constructed, permits diode turn-on time testing with excellent time and amplitude resolution.5 Figures 8 through 12 show results for five different diodes from various manufacturers. Figure 8 (Diode Number 1) overshoots steady state forward voltage for 3.6ns, peaking 200mV. This is the best performance of the five. Figures 9 through 12 show

increasing turn-on amplitude and time which are detailed in the figure captions. In the worst cases, turn-on amplitudes exceed nominal clamp voltage by more than 1V while turn-on times extend for tens of nanoseconds. Figure 12 culminates this unfortunate parade with huge time and amplitude errors. Such errant excursions can and will cause IC regulator breakdown and failure. The lesson here is clear. Diode turn-on time must be characterized and measured in any given application to insure reliability. LNotes1 An alternate pulse generation approach appears in

Linear Technology Application Note 122, Appendix F, “Another Way to Do It.”

2 Z0 probes are described in Linear Technology Ap-plication Note 122 Appendix C, “About Z0 Probes.” See also References 27 thru 34.

3 The subnanosecond pulse generator requirement is not trivial. See Linear Technology Application Note 122 Appendix B, “Subnanosecond Rise Time Pulse Generators For The Rich and Poor.”

4 See Linear Linear Technology Application Note 122 Appendix E, “Connections, Cables, Adapters, Attenuators, Probes and Picoseconds” for relevant commentary.

5 See Linear Technology Application Note 122 Ap-pendix A, “How Much Bandwidth is Enough?” for discussion on determining necessary measurement bandwidth.

amount of ambient noise in the room. Figure 3 shows the noise spectrum in the chamber without any devices run-ning. This can be used to determine the actual noise produced by the DUT.

Figure 4 shows the worst case LTM8032 emissions plot, which oc-curs at maximum power out, 10V at

90

70

50

EMIS

SION

S LE

VEL

(dBµ

V/m

)

30

10

80

60

40

20

0

–100 100 200 300 400 500

FREQUENCY (MHz)600 700 800 900 1000

EN55022CLASS BLIMIT

90

70

50

EMIS

SION

S LE

VEL

(dBµ

V/m

)

30

10

80

60

40

20

0

–100 100 200 300 400 500

FREQUENCY (MHz)600 700 800 900 1000

EN55022CLASS BLIMIT

Figure 3. The baseline measurement of ambient noise in the 5-meter chamber (no devices operating) Figure 4. The LTM8032 emissions for 20W out, 36VIN

2A, from the maximum input voltage, 36V. There are two traces in the plot, one for the vertical and horizontal orientations of the test lab’s receiver antenna. As shown in the figure, the LTM8032 easily meets the CISPR 22 class B limits, with 20db of margin for most of the frequency spectrum, with either antenna orientation.

ConclusionThe LTM8032 switching step-down regulator is both easy to use and quiet, meeting the radiated emissions re-quirements of CISPR22 and EN55022 class B by a wide margin. L

LTM8032, continued from page 33

Authors can be contactedat (408) 432-1900

6 Linear Technology Magazine • December 2009

L DESIGN FEATURES

IntroductionFrequently, voltage reference stabil-ity and noise define measurement limits in instrumentation systems. In particular, reference noise often sets stable resolution limits.

Reference voltages have decreased with the continuing drop in system power supply voltages, making refer-ence noise increasingly important. The compressed signal processing range mandates a commensurate reduction in reference noise to maintain resolu-tion. Noise ultimately translates into quantization uncertainty in ADCs, introducing jitter in applications such as scales, inertial navigation systems, infrared thermography, DVMs and medical imaging apparatus.

A new low voltage reference, the LTC6655, has only 0.3ppm (775nV) noise at 2.5VOUT. Table 1 lists salient specifications in tabular form. Ac-curacy and temperature coefficient are characteristic of high grade, low voltage references. 0.1Hz to 10Hz noise, particularly noteworthy, is un-equalled by any low voltage electronic reference.

Noise MeasurementSpecial techniques are required to verify the LTC6655’s extremely low noise. Figure 1’s approach appears in-nocently straightforward but practical

775 Nanovolt Noise Measurement for a Low Noise Voltage ReferenceQuantifying Silence

implementation represents a high or-der difficulty measurement. This 0.1Hz to 10Hz noise testing scheme includes a low noise preamplifier, filters and a peak-to-peak noise detector. The pre-amplifiers 160nV noise floor, enabling accurate measurement, requires spe-cial design and layout techniques. A forward gain of 106 permits readout by conventional instruments.

by Jim Williams

Figure 2’s detailed schematic re-veals some considerations required to achieve the 160nV noise floor. The references’ DC potential is stripped by the 1300µF, 1.2k resistor combina-tion; AC content is fed to Q1. Q1-Q2, extraordinarily low noise JFETs, are DC stabilized by A1, with A2 provid-ing a single-ended output. Resistive feedback from A2 stabilizes the con-figuration at a gain of 10,000. A2’s

SWEEPGATE OUT

DC OUT0V TO 1V = 0µVP-PTO 1µVP-P AT INPUT

VERTICALINPUT

≈700nVNOISE

0.1Hz TO 10Hz

OSCILLOSCOPE

OUTPUT

A = 106

0.1Hz TO 10Hz FILTER ANDPEAK-TO-PEAK NOISE DETECTOR0µV TO 1µV = 0V TO 1V, A = 100

LOW NOISEAC PRE-AMP

EN, 0.1Hz TO 10Hz = 160nVA = 10,000

RESET

LTC66552.5V REFERENCE

Figure 1. Conceptual 0.1Hz to 10Hz noise testing scheme includes low noise preamplifier, filter and peak-to-peak noise detector. Pre-amplifier’s 160nV noise floor, enabling accurate measurement, requires special design and layout techniques.

Table 1. LTC6655 reference tabular specifications. The LTC6655 accuracy and temperature coefficient are characteristic of high grade, low voltage references. 0.1Hz to 10Hz noise, particularly noteworthy, is unequalled by any low voltage electronic reference.

SPECIFICATION LIMITSOutput Voltages 1.250, 2.048, 2.500, 3.000, 3.300, 4.096, 5.000Initial Accuracy 0.025%, 0.05%

Temperature Coefficient 2ppm/°C, 5ppm/°C

0.1Hz to 10Hz Noise 0.775µV at VOUT = 2.500V, Peak-to-Peak Noise is within this Figure in 90% of 1000 10-Second Measurement Intervals

Additional Characteristics

5ppm/V Line Regulation, 500mV Dropout, Shutdown Pin, ISUPPLY = 5mA, VIN = VO + 0.5V to 13.2VMAX, IOUT(SINK/SOURCE) = ±5mA, ISHORT-CIRCUIT = 15mA.

Linear Technology Magazine • December 2009 7

DESIGN FEATURES L

+ –

100k

100k

SHIE

LD

SHIE

LDED

CAN

1N46

9710

V

AC L

INE

GROU

ND

1300

µF

9V

100k

*

10Ω

*

+–

1k*

200Ω

*

2k

453Ω

*90

9Ω*

15V

15V

–15V

–15V

1µF

1µF

A1LT

1012

A2LT

1097

– IN

PUT

Q15

* =

1% M

ETAL

FIL

M**

= 1

% W

IREW

OUND

, ULT

RONI

X105

A

=

1N41

48

= 2N

4393

=

1/4

LTC2

02

SEE

LINE

AR T

ECHN

OLOG

Y AP

PLIC

ATIO

N NO

TE 1

24, A

PPEN

DIX

C FO

R PO

WER

, SHI

ELDI

NG A

ND G

ROUN

DING

SCH

EME

=

TANT

ALUM

,WET

SLU

G

I L

EAK

< 5n

A

SE

E LI

NEAR

TEC

HNOL

OGY

APP

LICA

TION

NOT

E 12

4, A

PPEN

DIX

B

=

POLY

PROP

YLEN

E

A4 3

30µF

OUT

PUT

CAPA

CITO

RS =

<20

0nA

LEAK

AGE

AT 1

V DC

AT 2

5°C

Q1, Q

2 =

THER

MAL

LY M

ATED

2SK3

69 (M

ATCH

VGS

10%

)OR

LSK

389

DUAL

THER

MAL

LY L

AGSE

E TE

XT

A =

104

LOW

NOI

SEPR

E-AM

P

REFE

RENC

EUN

DER

TEST

0.15

µF

750Ω

*

10k

–15V

Q32N

2907

Q20.

022µ

F

1µF

**1.

2kSD

LTC6

655

2.5V

INS F

+

1µF

0.1µ

F

124k

*12

4k*

–+A3

LT10

12

1M*

10k*

100Ω

*33

0Ω* IN

OUT

ROOT

-SUM

-SQU

ARE

CORR

ECTI

ONSE

E TE

XT

330µ

F16

V

330µ

F16

V

+

+

330µ

F16

V

330µ

F16

V

+–A4

LT10

12

0.1µ

F

0.1µ

F

10k

A =

100

AND

0.1H

z TO

10H

z FI

LTER

1µF

RST

+–A5

1/4

LT10

58–+

A71/

4 LT

1058

1k

PEAK

TO

PEAK

NOIS

E DE

TECT

OR

O TO

1V

=O

TO 1

µV

+ PE

AK

4.7k

P

P

1µF

RST

15

0.1µ

F

+–A6

1/4

LT10

58

–+A8

1/4

LT10

58

1k–

PEAK

4.7k

10k

100k

100k

P

T

T

–+

DVM

TO O

SCIL

LOSC

OPE

INPU

T VI

A IS

OLAT

ED P

ROBE

,1V

/DIV

= 1

µV/D

IV,

REFE

RRED

TO

INPU

T,SW

EEP

= 1s

/DIV

FROM

OSC

ILLO

SCOP

ESW

EEP

GATE

OUT

PUT

VIA

ISOL

ATIO

NPU

LSE

TRAN

SFOR

MER

RESE

T PU

LSE

GENE

RATO

R0.

22µF

C2RC

2

+15

+15

CLR2

+1574

C221

RST

= Q2

+V

+15

A2

B2

10k

BAT-

85

BAT-

85

10k

+

+

0.00

5µF

–15

10k

0.00

5µF

Figu

re 2

. Det

aile

d no

ise

test

cir

cuit

ry. T

herm

ally

lagg

ed Q

1-Q

2 lo

w n

oise

JFE

T p

air

is D

C s

tabi

lize

d by

A1-

Q3;

A2

deli

vers

A =

10,

000

prea

mpl

ifier

out

put.

A3-

A4

form

0.1

Hz

to

10H

z, A

= 1

00, b

andp

ass

filt

er; t

otal

gai

n re

ferr

ed t

o pr

e-am

plifi

er i

nput

is

106 .

Pea

k-to

-pea

k no

ise

dete

ctor

, res

et b

y m

onit

orin

g os

cillo

scop

e sw

eep

gate

, sup

plie

s D

VM

out

put.

8 Linear Technology Magazine • December 2009

L DESIGN FEATURES

mated and lagged in epoxy at a time constant much greater than A1’s DC stabilizing loop roll-off, preventing offset instability and hunting. The entire A1-Q1-Q2-A2 assembly and the reference under test are completely enclosed within a shielded can.1 The reference is powered by a 9V battery to minimize noise and insure freedom from ground loops.

Peak-to-peak detector design con-siderations include JFETs used as peak trapping diodes to obtain lower leakage than afforded by conventional diodes. Diodes at the FET gates clamp reverse voltage, further minimizing leakage.2 The peak storage capacitors highly asymmetric charge-discharge profile necessitates the low dielectric absorption polypropelene capacitors specified.3 Oscilloscope connections via galvanically isolated links prevent

output is routed to amplifier-filter A3-A4 which provides 0.1Hz to 10Hz response at a gain of 100. A5-A8 com-prise a peak-to-peak noise detector read out by a DVM at a scale factor of 1 volt/microvolt. The peak-to-peak noise detector provides high accuracy measurement, eliminating tedious in-terpretation of an oscilloscope display. Instantaneous noise value is supplied by the indicated output to a monitoring oscilloscope. The 74C221 one-shot, triggered by the oscilloscope sweep gate, resets the peak-to-peak noise detector at the end of each oscilloscope 10-second sweep.

Numerous details contribute to the circuit’s performance. The 1300µF capacitor, a highly specialized type, is selected for leakage in accordance with the procedure given in Appendix B. Furthermore, it, and its associ-

ated low noise 1.2k resistor, are fully shielded against pick-up. FETs Q1 and Q2 differentially feed A2, forming a simple low noise op amp. Feedback, provided by the 100k-10Ω pair, sets closed loop gain at 10,000. Although Q1 and Q2 have extraordinarily low noise characteristics, their offset and drift are uncontrolled. A1 corrects these deficiencies by adjusting Q1’s channel current via Q3 to minimize the Q1-Q2 input difference. Q1’s skewed drain values ensure that A1 is able to capture the offset. A1 and Q3 supply whatever current is required into Q1’s channel to force offset within about 30µV. The FETs’ VGS can vary over a 4:1 range. Because of this, they must be selected for 10% VGS matching. This matching allows A1 to capture the offset without introducing signifi-cant noise. Q1 and Q2 are thermally

10ms/DIV

2mV/DIV

AN124 F04

Figure 3. Preamplifier rise time measures 10ms; indicated 35Hz bandwidth ensures entire 0.1Hz to 10Hz noise spectrum is supplied to succeeding filter stage.

1s/DIV

E = 20V/DIV

D = 1V/DIV

C = 0.5V/DIV

B = 0.5V/DIV

A = 5mV/DIV

AN124 F05

Figure 4. Waveforms for peak-to-peak noise detector include A3 input noise signal (trace A), A7 (trace B) positive/A8 (trace C) negative peak detector outputs and DVM differential input (trace D). Trace E’s oscilloscope supplied reset pulse lengthened for photographic clarity.

1s/DIV

100nV/DIV

AN124 F06

Figure 5. Low noise circuit/layout techniques yield 160nV 0.1Hz to 10Hz noise floor, ensuring accurate measurement. Photograph taken at Figure 3’s oscilloscope output with 3V battery replacing LTC6655 reference. noise floor adds ≈2% error to expected LTC6655 noise figure due to root-sum-square noise addition characteristic; correction is implemented at Figure 2’s A3.

1 MINAN124 F07TIME

AMPL

ITUD

E

100nV

0V

Figure 6. Peak-to-peak noise detector output observed over six minutes shows <160nv test circuit noise. Resets occur every 10 seconds. 3V battery biases input capacitor, replacing LTC6655 for this test.

Linear Technology Magazine • December 2009 9

DESIGN FEATURES L

DVM differential input (Trace D). Trace E’s oscilloscope supplied reset pulse has been lengthened for photographic clarity.

Circuit noise floor is measured by replacing the LTC6655 with a 3V battery stack. Dielectric absorption effects in the large input capacitor require a 24-hour settling period before measurement. Figure 5, taken at the circuit’s oscilloscope output, shows 160nV 0.1Hz to 10Hz noise in a 10 second sample window. Because noise adds in root-sum-square fashion, this represents about a 2% error in the LTC6655’s expected 775nV noise figure. This term is accounted for by placing Figure 2’s “root-sum-square correction” switch in the appropri-ate position during reference testing. The resultant 2% gain attenuation first order corrects LTC6655 output noise reading for the circuit’s 160nV noise floor contribution. Figure 6, a strip-chart recording of the peak-to-

ground loop induced corruption. The oscilloscope input signal is supplied by an isolated probe; the sweep gate output is interfaced with an isolation pulse transformer. For more details, see Linear Technology Application Note 124, Appendix C.

Noise Measurement Circuit PerformanceCircuit performance must be charac-terized prior to measuring LTC6655 noise. The preamplifier stage is verified for >10Hz bandwidth by applying a 1µV step at its input (reference discon-nected) and monitoring A2’s output. Figure 3’s 10ms rise time indicates 35Hz response, insuring the entire 0.1Hz to 10Hz noise spectrum is sup-plied to the succeeding filter stage.

Figure 4 describes peak-to-peak noise detector operation. Waveforms include A3’s input noise signal (Trace A), A7 (Trace B) positive/A8 (Trace C) negative peak detector outputs and

peak noise detector output over six minutes, shows less than 160nV test circuit noise.4 Resets occur every 10 seconds. A 3V battery biases the input capacitor, replacing the LTC6655 for this test.

Figure 7 is LTC6655 noise after the indicated 24-hour dielectric absorp-tion soak time. Noise is within 775nV peak-to-peak in this 10 second sample window with the root-sum-square cor-rection enabled. The verified, extremely low circuit noise floor makes it highly likely this data is valid. In closing, it is worth mention that the approach taken is applicable to measuring any 0.1Hz to 10Hz noise source, although the root-sum-square error correction coefficient should be re-established for any given noise level. LNotes1 The preamplifier structure must be carefully

prepared. See Appendix A in Linear Technology Application Note 124, “Mechanical and Layout Considerations,” for detail on preamplifier con-struction.

2 Diode-connected JFETs’ superior leakage derives from their extremely small area gate-channel junc-tion. In general, JFETs leak a few picoamperes (25°C) while common signal diodes (e.g. 1N4148) are about 1,000× worse (units of nanoamperes at 25°C).

3 Teflon and polystyrene dielectrics are even better but the Real World intrudes. Teflon is expensive and excessively large at 1µF. Analog types mourn the imminent passing of the polystyrene era as the sole manufacturer of polystyrene film has ceased production.

4 That’s right, a strip-chart recording. Stubborn, lo-cally based aberrants persist in their use of such archaic devices, forsaking more modern alterna-tives. Technical advantage could account for this choice, although deeply seated cultural bias may be indicated.

1s/DIV

500nV/DIV

AN124 F08

Figure 7. LTC6655 0.1Hz to 10Hz noise measures 775nV in 10-second sample time.

and external clock synchronization features, and comes in a 10-pin MSOP or 3mm × 3mm DFN package, both with an exposed ground pad.

The LT3991 has a typical minimum switch on time of 110ns at room and 150ns at 85°C, which allow higher switching frequencies for large step-down ratios when compared to other parts with similar high input voltage ratings. Figure 8 shows a 48V input to a 3.3V output application with a switching frequency of 300kHz. The 10µH inductor and 47µF output ca-pacitor yield a small overall solution

size. The output capacitor can be a small ceramic capacitor, as opposed to a tantalum capacitor, because the LT3991 does not need any output capacitor ESR for stability.

ConclusionThe LT3971 and LT3991 are ultralow quiescent current regulators that can regulate a 12V input to a 3.3V output during no load conditions with only 2.8µA of input current. Light load operation with single current pulses keeps the output voltage ripple to less than 15mV. These buck regulators can also provide up to 1.2A of output

current. The LT3971 and LT3991 are well suited for keep-alive and remote monitoring systems with low duty cycle, high current, pulsed outputs. The wide input range from 4.3V up to 38V for the LT3971, and 55V for the LT3991, along with the program-mable input voltage enable threshold feature, allow these converters to be driven from a wide range of input sources. The ultralow quiescent cur-rent performance of the LT3971 and LT3991 make them great choices for battery-operated systems where power conservation is critical. L

LT971/91, continued from page