The graduation thesis plea of XXX University

A 107 dB DR, 106dB SNDR Sigma-Delta ADC

Using aCharge-Pump Integrator for

Audio Application

A 107 dB DR, 106dB SNDR Sigma-Delta ADC

Using aCharge-Pump Integrator for

Audio Application

The final year project presentation

Student No.：Sam, (DB028791); Hubert,

(DB029125)

Supervisor： Prof. Sin-Weng Sai

Co-Supervisor： Prof. U Seng Pan

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1. Introduction

2. Basic theory of Sigma-Delta ADC

5. Charge Pump Integrator

4. Architecture Chosen

7. Circuit Partial Design

6. Behavioral Model

CONTENTS

3. Target specification

8. Conclusion

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Introduction01

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Introduction

A/D converter2

Audio in life1

Audio standard3

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Introduction

A/D converter2

Audio in life1

Audio standard3

ADC

Analog Digital

Signal: Continuous signal which represents physical measurements.

Discrete time signals generated by digital modulation.

Example: Human voice in air, analog electronic devices.

Computers, CDs, DVDs, and other digital electronic devices.

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Introduction

A/D converter2

Audio in life1

Audio standard3

ADC

Increase the quality, reduce the noise and Cumulative distortion.

Save energy, use converter instead of the amplifier in transmission.

Information safety, Given the timing information, the transmitted waveform

can be reconstructed

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Introduction

A/D converter2

Audio in life1

Audio standard3

Frequency range: 20~20k Hz

Sound Pressure Level(SPL) = human ear's audible sounds is from 0 dB SPL (hearing threshold) to 140 dB SPL (pain threshold) 

People’s hearing range

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Introduction

A/D converter2

Audio in life1

Audio standard3

Compact Disc Digital Audio (CDDA or CD-DA) is the standard format for audio Compact Discs. The standard is defined in the Red Book

44.1 KHz 16bit about 96dB dynamic range

symphony orchestra 110dB SPL

Library 30 dB SPL110 dB - 30 dB = only 80 dB real dynamic range if you brought the orchestra into your home

Good enough for listeners !

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Introduction

A/D converter2

Audio in life1

Audio standard3

？16 bit enough?

An professional requires more during mixing and mastering. Multiplying that noise by a few thousand times eventually becomes noticeable.

Keep the accumulated noise at a very low level !

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Basic theory of Sigma-Delta ADC02

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Basic theory

Key features2

Different ADC1

Sigma Delta

SAR

Subranging/Pipelined

Signal Bandwidth

Conv

ersi

on R

esol

utio

n

Flash

High resolution

Low bandwidth

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Basic theory

Key features2

Different ADC1

Signal to noise ratio for Nyquist ADC

𝑆𝑁𝑅∨  𝑑𝐵=10 𝑙𝑜𝑔𝑃 𝑠𝑖𝑔𝑛

𝑃𝑛𝑜𝑖𝑠𝑒

where Psign and Pnoise are the power of the signal and the power of the noise in the band of interest.Sine wave as example:

𝑃𝑠𝑖𝑛𝑒=1𝑇∫

0

𝑇 𝑋𝐹𝑆2

4𝑠𝑖𝑛2 (2𝜋 𝑓𝑡 )𝑑𝑡 ≈ 1

𝑇 ∫0

𝑇 𝑋𝐹𝑆2

4(2𝜋 𝑓𝑡 )2𝑑𝑡=(∆ ∙2𝑛)2

8

∴𝑆𝑁𝑅𝑠𝑖𝑛𝑒∨  𝑑𝐵=(6.02 ∙𝑛+1.78 ) 𝑑𝐵

𝑃𝑄=∆2

12

Every bit of quantizer improves the SNR by 6.02 dB!!!

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Basic theory

Key features2

Different ADC1

Oversampling

(OSR)

Noise shaping

(Order)

ADC

fs

A

fs/2 fs

Nyquist Operation

ADC

kfs

B

fs/2 kfs/2

Oversampling+ Digital filter

Digital filter

ƩΔMOD

kfs

fs/2 kfs/2

Oversampling+ Digital filter+ Noise shaping

Digital filter

C

kfs

kfs

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Target specification

03

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Target specification Our target

2Products’ use1

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Target specification Our target

2Products’ use1

NAME SNR

Normal products

pcm1870 90dB

pcm1808 99dB

pcm1851a 101dB

pcm1803a 103dB

Audio Sigma-Delta ADC From TI Company

From the table, listing some the audio ADCs use in

car audio system. The SNR performance is 99dB.

Thus We set our target as 105dB SNR, After setting the target, the structure of the ƩΔ ADC will be chosen to build the system.

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Architecture Chosen04

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Architecture Chosen Quantizer and OSR

2Architecture1

Single Loop Architecture

CIFB – Cascade Integrators with Distributed Feedback

CIFF – Cascade Integrators with Distributed Feed-forward

CRFB – Cascade Resonator with Distributed Feedback

CRFF – Cascade Resonator with Distributed Feed-forward

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b1

c2 c3 a3

DAC

b4

-c1

v(n)y(n)

u(n)

a2

a3

b2b1

c1 c2 c3

DAC

b3 b4

-a1 -a2 -a3

v(n)y(n)

u(n)

- b1 = b4 = 1

Architecture Chosen Quantizer and OSR

2Architecture1

NTF

CIFB

CIFF

-ai = bi for i ≤ 3-b4 = 1

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b1

c2 c3 a3

DAC

b4

-c1

v(n)y(n)

u(n)

a2

a3

-g1

b2b1

c1 c2 c3

DAC

b3 b4

-a1 -a2 -a3

-g1

v(n)y(n)

u(n)

- b1 = b4 = 1

CRFB

CRFF

10-3

10-2

10-1

100

-140

-120

-100

-80

-60

-40

-20

0

20

Further increase SNR by optimizing NTF zero

NTF

Architecture Chosen Quantizer and OSR

2Architecture1

-ai = bi for i ≤ 3-b4 = 1

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Feedforward Feedback

Only one DAC required Requires many feedback DACs

Needs an extra adder No extra adder

First integrator is fastest Last integrator is fastest

First opamp is power hungry First opamp is power hungry

With Resonator Without Resonator

Advantage Higher SNDR Simpler Structure

Disadvantage

More Complex Structure

(Resonator)

Lower SNDR

Architecture Chosen Quantizer and OSR

2Architecture1

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A single loop 3rd order CRFB Σ-Δ ADC with 1.5 bit quantizer and 256 OSR are designed.

01

02

03

05

1.5 Bit Quantizer

Higher SNR Ensure

linearity

3rd order architecture Higher SNR

OSR=256

Higher SNR Decrease the Thermal

Noise

Architecture Chosen Quantizer and OSR

2Architecture1

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Charge Pump Integrator05

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CRFB architecture using conventional SC integrator

CRFB architecture using CP SC integrator

Φ1aΦ1

Φ2

Φ2Φ1a

Φ1

VIP

Φ1a

VIP

Φ2a

FEEDBACK

VREFP

Φ1aΦ2a

VREFN

Φ2

Φ2

Φ1aΦ1

Φ2

Φ2Φ1a Φ1

VIPΦ1a

VIP

Φ2a

VREFP

Φ1a Φ2a

VREFN

Φ2

Φ2

Φ1aΦ2

Φ1

Φ1Φ1a

Φ2

VIP

Φ1a

VIP

Φ2

Φ1a Φ2

Φ2

Φ2

Φ2

Φ1aΦ2a

VFBN

Φ1aΦ2a

VFBP

Φ1aΦ1

Φ2

Φ2Φ1a Φ1

Φ2a

VREFP

Φ2a

VREFN

VIP

VIP

First Integrator

Second Integrator

Third Integrator

Adder

Φ2

VIP Φ1aΦ1

Φ1a2VREFP

Φ1

Φ2a

Φ2

VIN

Φ1aΦ1

Φ1a

2VREFN Φ1

Φ2a

Φ2

Φ1aΦ1

Φ2

Φ2Φ1a

Φ1

VIP

Φ1a

VIP

Φ2a

FEEDBACK

VREFP

Φ1aΦ2a

VREFN

Φ2

Φ2

Φ1aΦ1

Φ2

Φ2Φ1a Φ1

VIPΦ1a

VIP

Φ2a

VREFP

Φ1a Φ2a

VREFN

Φ2

Φ2

Φ1aΦ2

Φ1

Φ1Φ1a

Φ2

VIP

Φ1a

VIP

Φ2

Φ1a Φ2

Φ2

Φ2

Φ2

Φ1aΦ2a

VFBN

Φ1aΦ2a

VFBP

First Integrator(CP)

Second Integrator

Third Integrator

Adder

Φ2

Charge Pump Integrator Introduction

1Conclusion2

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VINΦ1 Φ2

Φ2

VREF

Φ1

VOUT

Cs

Ci

VINVOUT

Φ2 Φ2

Φ1

Φ1Φ2

Cs1=Cs/2

Cs2=Cs/2

Ci2

VOUTVref

Cs

Cl

VOUT

Cs/4

Cs/2k

2Vref

Cl

Conventional

Charge-pump

Φ 2

𝐶𝑠 /𝑘

Φ 2

Charge Pump Integrator Introduction

1Conclusion2

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Conventional Charge-pump

𝑃𝑂𝑊 𝑂𝑃∝𝑔𝑚

VOUTVref

Cs

Cl

𝐶𝑠 /𝑘

VOUT

Cs/4

Cs/2k

2Vref

Cl

𝑔𝑚=𝜔−3 𝑑𝐵𝐶𝐿

𝛽

𝐶𝐿=𝐶𝑠

𝑘+1+𝐶𝑙

𝛽=1

𝑘+1

𝐶𝐿 ′=𝐶𝑠 /2𝑘+2

+𝐶𝑙

𝛽 ′=2

𝑘+2𝐶𝐿

𝛽=𝐶 𝑠+𝐶𝑙(𝑘+1) (

𝐶𝐿

𝛽) ′=

𝐶𝑠

4+𝐶𝑙 (

𝑘2

+1)

𝑔𝑚′ =

𝑔𝑚

4𝑃𝑂𝑊 𝑜𝑝

′ =𝑃𝑂𝑊𝑂𝑃

4

(𝐶𝐿

𝛽 )′

≈𝐶𝐿

4 𝛽

Charge Pump Integrator Introduction

1Conclusion2

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S W

O TEasier to implement by adding capacitor

May cause unmatched problem and high requirements to other parts

STRENGTH WEAKNESS

OPPORTUNITY THREATS

Reduce the power consumption of the amplifier

Need double supply voltage(two 0.25um transistor)

Charge Pump Integrator Introduction

1Conclusion2

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Behavioral Model06

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Behavioral ModelModel with Non-idealities2

Ideal Model1

The 3rd order CRFB with noise block in Matlab

104

105

106

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0PSD of a 3rd-Order Sigma-Delta Modulator

Frequency [Hz]

PS

D [

dB]

SNR = 134.8dB @ OSR=256

ENOB = 22.10 bits @ OSR=256

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Behavioral ModelIdeal Model1

Model with Non-idealities2

The main non-idealities

75%

20%5%

kT/C plus Op-amp thermal noiseOther noiseQuantization noise

Operational amplifier non-idealities:

1. Bandwidth of Op-amp;

2. Slew rate of Op-amp;

3. Operational amplifier saturation

voltages.

Thermal noise of Switch Capacitor

structure.

noise of op-amp.

clock jitter at the input sampler.

30/47

Behavioral ModelIdeal Model1

Model with Non-idealities2

Finite DC gain SNR

80dB 134.8dB

60dB 134.8dB

58dB 132.3dB

54dB 128.1dB

50dB 120.4dB

104

105

106

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0PSD of a 3rd-Order Sigma-Delta Modulator

Frequency [Hz]

PS

D [

dB]

DC gain requirement of first op-amp

Repeat the operation to obtain behavioral model of the system

-0.05 0 0.050

50

100

150

200

250First Integrator Output

Voltage [V]

Occ

urre

nces

-0.4 -0.2 0 0.2 0.40

50

100

150

200

250Second Integrator Output

Voltage [V]

Occ

urre

nces

-1 -0.5 0 0.5 10

50

100

150

200

250Third Integrator Output

Voltage [V]

Occ

urre

nces

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Behavioral ModelIdeal Model1

Model with Non-idealities2

Sigma-delta Parameter SNR (dB)

Ideal modulation 134.8

Finite DC gain (A=58dB,

58dB, 50dB)130.6

Finite

bandwidth(GBW=100MHz)134.8

Finite Slew-rate

(SR=60V/us)134.8

Saturation voltages (|Vmax|

=1V)134.8

Sampling Jitter (Δ) 130.7

Switch (kT/C) noise

(Cs=10pF)110.4

Input-referred operational

amplifier noise (Vn=1.5uV)108

Including all of the non-

idealities107-107.5

Behavioral Model of The Project

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In cadence simulation, the first Op-amp gain requirement is 58 dB for 133dB SNR, now change the architecture:

The gain of first Op-amp(dB)

simulation result of Cadence(dB)

54 133

50 133

48 133

46 132

42 130

It is clearly found that the requirement of first Op-amp is reduced

Behavioral ModelIdeal Model1

Model with Non-idealities2

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Circuit Partial Design07

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Circuit Partial Design

Quantizer3

Op-amp1

Optimization2

Op-amp DesignVDD

GND

VIPVIN

VCMFB

VB1

vOPvON

M2 M3

M4

M6

M5

M7

M8 M9

M10 M11

M1VB4

VB2

VB3

M12

M14

M13

M15

VCMFB1

vOP1vON1

vOP1 vON

vON1 vOP

C1R1

1st

C1 C2 C3 C4

Φ1 Φ2 Φ2 Φ1

Φ1 Φ2 Φ2 Φ1

VCM

VCMFB

VBIAS VBIAS

VCM

VOP VON

CMFB

Op-Amp: Main structure Bias Circuit Switched-capacitor

CMFB

Switch4

VDD

GND

IREF

VREF

1

VB0

VREFP

2 3

VB34

VREFP VREFP

VB1 VB25 6

VB27

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Circuit Partial Design

Quantizer3

Op-amp1

Optimization2

Op-amp Design VDD

GND

VIPVIN

VCMFB VB2 VB2

VB1

VB4

VB3 VB3

vOPvONM1

M2 M3

M4

M8

M12

M6

M10

M7

M11

M5

M9

M13

M14 M15

M18 M19

M16 M17

VDD

GND

VIPVIN

VCMFB

VB1

vOPvONM2 M3

M4

M6

M5

M7

M8 M9

M10 M11

M1

VB4

VB2

VB3

M12

M14

M13

M15

VCMFB1

vOP1vON1

2nd 3rd

Switch4

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Zero Optimization

Φ1a

Φ1 Φ2a Φ2

Φ2 C1C2

C3

Vo3Vi2

For the CRFB structure, it needs a local feedback from third integrator output to second integrator input to make up a resonator which effects the zero.

Q=g ∙V 𝑜3Q2=V 𝑜3 ¿¿

CbVi2 Vo3

Extremely small

Circuit Partial Design

Quantizer3

Op-amp1

Optimization2

Switch4

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1.5 Bit Quantizer

Circuit Partial Design

C1

C2

VCMVREFP

VCMVREFN

VIP

VIN

Φ1

Φ2

Φ1

Φ2

Φ2Φ2

C1

C2

VCMVREFN

VCMVREFP

VIP

VIN

Φ1

Φ2

Φ1

Φ2

Φ2Φ2

CLK

D0

D1

VDD

VSS

M7

vIN

M6

M5M4

M8 M9M10 M11

M2 M3

M1

vIP

vOP

vON

CLK CLK

CLK

Quantizer3

Op-amp1

Optimization2

Switch4

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Circuit Partial Design

CMOS switch

Vin Vout

CH

Ron,p Ron,n

Ron,eq

VTHP VDD-VTH

VIN

CLK

CLK’

It is often used very large or small voltage input, under such situation, the transmission resistor will change critically

Quantizer3

Op-amp1

Optimization2

Switch4

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Circuit Partial Design

Bootstrapped Switch

M1

sw1

Vss Vss

Vdd

sw3

sw2

sw5

sw4

Vin

Vout

Φ1

Φ1

Φ2 Φ2

Φ2

M1

M2

Input

Output

M3 M4

M5

M6 M7 M8

C1 C2C0

Vdd

Vss

To obtain constant conductance, the bootstrap technique can be used to keep the gate-source voltage at a certain value.

Quantizer3

Op-amp1

Optimization2

Switch4

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Conclusion08

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ConclusionComparison2

System Performance1

103

104

105

106

107

-140

-120

-100

-80

-60

-40

-20

0

Frequency(Hz)

PSD(

dB)

PdydB

Output PSD for the system Measured SNDR versus input amplitude

Technology Sampling Frequenc

y

Bandwidth Peak SNDR

Power Consumption

FOM

65nm CMOS 10.24MHz 20kHz 106dB 1.332mW 204f/conv.

107dB Dynamic Range

Summary3

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  CPConventio

nal

Peak

SNDR106dB 102dB

Power

consumpti

on

1.332mW 1.972mW

FOM 204f/conv. 479f/conv.

It achieves a higher SNDR but cost less power by using CP integrator

Transistor level comparison of system using CP And Conventional

32.4%

Power consumption

32.4% decrease because of first stage

ConclusionComparison2

System Performance1

Summary3

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Comparison with Other Σ-Δ ADC

ConclusionComparison2

System Performance1

Summary3

This work

JSSC/06 CICC/11TCAS-1/13

JSSC/09 JSSC/08 JSSC/03

  [1] [2] [5] [4] [3] [6]

Tech[um]

0.065 0.065 0.065 0.13 0.18 0.13 0.35

Supply[V]

1.0 1.2 1.0 1.2 0.7 0.9 2

Input Range[Vpp-diff]

0.9 1.0 0.9 0.4 1.0 1.1 /

OSR 256 300 64 128 100 128 154

BW[kHz]

20 20 24 10 20 24 20

SNDR[dB]

106 95 95 87.8 81 89 105

Power[uW]

1332 2200 371 148 36 1500 68000

FOM[fJ/conv.]

204 11200 170 369 98 1360 11700

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For audio application => high SNDR (target ≥105dB)

Suppress the in-band noise (oversampling and noise shaping)

3rd CRFB Sigma-Delta modulator architecture using CP integrator is selected

As a result, with a full-scale input of 900mVpp differential the CRFB ADC using charge-pump integrator achieves 106 dB SNDR and 107dB dynamic range in audio bandwidth (20kHz), while consuming 1.332mW power.

ConclusionComparison2

System Performance1

Summary3

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Reference

1. Dorrer, L., et al. "A 2.2 mW, continuous-time sigma-delta ADC for voice coding with

95dB dynamic range in a 65nm CMOS process." Solid-State Circuits Conference,

2006. ESSCIRC 2006. Proceedings of the 32nd European. IEEE, 2006.2. Liu, L., et al. "A 95dB SNDR audio ΔΣ modulator in 65nm CMOS." Custom Integrated

Circuits Conference (CICC), 2011 IEEE. IEEE, 2011.

3. M. G. Kim, G.-C. Ahn, P. Hanumolu, S.-H. Lee, S.-H. Kim, S.-B. You,J.-W. Kim, G. C.

Temes, and U.-K. Moon, “A 0.9 V 92 dB double-sampled switched-RC delta-sigma

audio ADC,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1195–1206, May 2008.

4. Y. Chae and G. Han, “Low voltage, low power, inverter-based switched-capacitor

delta-sigma modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 458–472, Feb.

2009.

5. Nilchi, Alireza, and David A. Johns. "A low-power delta-sigma modulator using a

charge-pump integrator." Circuits and Systems I: Regular Papers, IEEE Transactions

on 60.5 (2013): 1310-1321.

6. Yang, YuQing, et al. "A 114-dB 68-mW chopper-stabilized stereo multibit audio ADC in

5.62 mm 2." Solid-State Circuits, IEEE Journal of 38.12 (2003): 2061-2068. 46/47

THANK YOU !

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