the d0 silicon microstrip tracker (d0smt)

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R. LiptonVertex ‘98 Santorini, Greece

The D0 Silicon Microstrip Tracker (D0SMT)

Outline Design Detector Studies

Coupling capacitors

Radiation Damage

LASER tests Electronics and readout Mechanical Assembly Production Testing Summary and prospects

Installation in the spring of 2000

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D0SMT Components

Major SMT Subsystems•Single Sided Ladder (3 chip)•Double Sided 2o Ladder (9 chip)•Double Sided 90o Ladder (6 chip)•H Disk (SS back-to-back)•F Disk (DS)

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Barrel/Disk Module

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H DISK

• Silicon IR = 94.5 mm, OR = 236 mm at wedge centerlineSilicon IR = 94.5 mm, OR = 236 mm at wedge centerline• Readout mounts on outer silicon detectorReadout mounts on outer silicon detector• Wedges alternate between two surfaces of a central Wedges alternate between two surfaces of a central

cooling/support channelcooling/support channel• Effective stereo angle = 15Effective stereo angle = 15oo

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F Disk

• Silicon IR = 26 mm, OR = 105.27 mm at wedge centerlineSilicon IR = 26 mm, OR = 105.27 mm at wedge centerline• Readout mounts outboard of silicon, which allows disk to Readout mounts outboard of silicon, which allows disk to

fit within a gap of 8 mmfit within a gap of 8 mm• Wedges alternate between two surfaces of a centralWedges alternate between two surfaces of a central

cooling/support channel (beryllium)cooling/support channel (beryllium)• Effective stereo angle = 30 degreesEffective stereo angle = 30 degrees• p-side Trace angle = -15p-side Trace angle = -15oo with respect to wedge centerline with respect to wedge centerline

Pitch = 50 μmPitch = 50 μm• n-side Trace angle = +15n-side Trace angle = +15oo with respect to wedge centerline with respect to wedge centerline

Pitch = 62.5 μmPitch = 62.5 μm

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Capacitor Studies

In a double sided detector with grounded electronics, coupling capacitor breakdown will limit the lifetime of the detector.

Studies Eliminate “black hole” effect in the SVX chip

by bypassing parasitic transistor at the input (see VTX ‘96)

Effect of wirebonding on capacitor breakdown

5-10% of capacitors fail at 50-100V after bonding (normally Vbd=140V) on SS detectors

No excess failures see on DS detectors with PECVD layer

Single Sided Detectors0-100 V

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Vo

lta

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bondedunbonded

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n-side Capacitor Studies

When electronics are connected to the n-side of a detector with shorted capacitors we see an anomalous current from the amplifier input

Current is reduced when electronics is disconnected

Effect seen on n-side only Caused by forward bias of the p-stop n junction

Detector Characteristics

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V Bias

I Bias (microamp)

V Pstop

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n-side Capacitor Studies

p Stop Study

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V Strip

Istrip (x.1 ma)

V Pstop

50al

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n

n+ p+p+

~1VSVX

I strip

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Irradiation Studies

Expect ~1 Mrad exposure for the inner layer per 4fb1

Irradiation with 8 GeV Protons from the Fermilab booster 1 MeV Neutrons (Lowell Mass.)

Study Evolution of deletion characteristics Performance of detector and electronics

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Irradiation StudiesCluster size


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Irradiation Studiesnoise


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H Disk IrradiationD

eple

tion

volta

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)NN

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(10

(10

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m33 ))

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Neutron fluence (10Neutron fluence (101313/cm/cm22))

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Neutron fluence (10Neutron fluence (101313/cm/cm22))

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Neutron Studies

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Detector Studies using ~1 MeV neutron source

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Irradiation StudiesLASER Plateau


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Detector Production

Five detector types - 3-chip, 9-chip, 6-chip, F wedge, H wedge.

All radiation testing complete laser and cosmic ray studies

Measure in-situ rise times charge sharing distributions

Probe testing 100 V capacitor breakdown test on each

channel CV or alpha test to measure depletion IV Test Spot checks on

Interstrip resistance Coupling capacitance Strip currents

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Micron Detector Delivery

9 Chip DS Ladders

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8/19/93 11/27/93 3/7/94 6/15/94 9/23/94 1/1/95 4/11/95 7/20/95 10/28/95 2/5/96 5/15/96

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9 chip schedule

9 Chip Ladder Production

F Disk Wedges

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F Disk Wedge Delivered

F Disk Wedge Scheduled

F Disk Wedge Production

Needed forschedule

Needed forschedule

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Readout System

LOCATING NOTCHES

BERYLLIUM

HDI

SILICON

SVX CHIPS

HDI FLATLINE CABLE

FPGA

Fiber receiver

Fiber Driver

D0 Silicon Readout Scheme

VRBVRBCD0 Clock

System

Trigger Manager

Monitor System

Sequencer Cd (platform)

VME

Fiber Optic Links

Transition Card (cryostat)

pigtail

low mass cable

high mass cable

VBD

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D0SMT - Electronics

SVXII Chip - done and tested Most issues involve bypassing and clock

quality Needs careful hybrid(HDI) design

HDIs - delivery pacing production Single layer flex 4 mil pitch, 2 mil vias

Cables: low mass, good frequency response (53

Mhz), low attenuation, no reflections, no radiation of clock signal to the calorimeter, fits in the allowed space.

High impedance stripline 3 segments

low mass section of varying length low mass fixed length “high mass” high quality section

System tests underway now

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Where we were “burned”

HDI flex circuit - good prototypes but no good production circuits

Find reliable company (Dyconex) pay extra $$$

Detector delivery - ordered detectors 2 years early but waited for BABAR, H1…

still a serious problem Cables

low mass, high impedance striplines are difficult pay extra $$$

But we are now in production and expect to be on schedule

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Mechanical Systems

Design Philosophy Build planar assemblies (ladders, wedges,

disks) precisely under (Zeiss) CMM Use mechanical tolerances to determine

ladder placement in barrel (~15 m) Minimum Mass

Be support structures Carbon fiber overall support

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Ladder Assembly

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Module Assembly

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Ladder Assembly

Match notches in Be support to posts in bulkhead

15 micron tolerance on Notched and posts 2 micron tolerances achieved in ladders

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-12 -10 -8 -6 -4 -2 0 2 4 6 8 10

Mean = 0.7 micrometers

Sigma = 1.9 micrometers

13 ladders, 78 fiducial locations Detector fiducials relative Detector fiducials relative to beryllium notchesto beryllium notches

Transverse offset from nominal (μmTransverse offset from nominal (μm))

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Rise Time Studies



Use LASER to excite SSD, Monitor preamp

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Production Testing

HDI Burn-in Encapsulation

HDI Spot-check Ladder assembly

Ladder Spot-check Ladder repairs

Ladder burn-in LASER Test Insertion into detector

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Laser TestingChannel uniformity

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Laser TestingChannel Gains

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Ladder and HDI

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Summary

We have achieved: low mass flex/beryllium hybrids SVX II chip, 53 MHz readout Minimal dead area Precise construction A workable double sided design for

“moderate” radiation doses Now we just have to build another 787,968

channels

the d0 silicon microstrip tracker (d0smt)

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