the control logic andreas klappenecker cpsc321 computer architecture
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The Control Logic
Andreas KlappeneckerCPSC321 Computer
Architecture
Verilog HDL
Verilog Programming Suppose that we have a module foo Our goal is to instantiate and wire a
module foon that contains n copies of the module foo.
Many textbooks on Verilog suggest to write down the n instance explicitly if n = 1024 then this is not a viable option reusability of the code would be limited
Example 1
foo foo foo foofoo foofoo foo
foon
=
Example 1
module foo(out, a,b);
output out;
input a, b;
xor (out, a, b);
endmodule
module foon(out, a, b);
parameter n = 8;
output [n-1:0] out;
input [n-1:0] a, b;
foo foon[n-1:0](out,a,b);
endmodule
Example 2
foo foo
foon
=
foofoofoofoofoofoo
Example 2
module foo(out, a,b);
output out;
input a, b;
xor (out, a, b);
endmodule
module foon(out, a, enable);
parameter n = 8;
output [n-1:0] out;
input [n-1:0] a;
input enable;
foo foon[n-1:0] (out, a,
{out[n-2:0],enable});
endmodule
Remarks The module vector operator is not available in
Icarus Verilog nor in Veriwell The features shown work in vcs
foo foon[n-1:0](out,a,{out[n-2:0],enable}); out and a range over [n-1:0] {out[n-2:0], enable} gives vector [n-1:0]
The suggested for-loop construction does not work
Control
MIPS Multicycle DatapathIncomplete (branch and jumps…)
Control What are the control signals? Finite state machine control
Instruction fetch instruction decode
memory reference R-type branch jump
Multicycle Datapath and Control Lines
High-Level Picture What happens precisely during each
step of fetch/decode/execute cycles Construct the finite state control
machine High-level view
Instruction Fetch/Decode/Execute
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction for branches
Action for jumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Instruction Fetch & Decode FSM
Memory-Reference FSM
• Address calculation
• Load sequence
• read from memory
• store to register
• Access memory
• Store sequence write
R-type Instruction
• Execution of instruction
• Completion of instruction
Branch Instruction
Implementation of FSM
A FSM can be implemented by a register holding the state and a block of combinatorial logic
Task of the combinatorial logic:
• Assert appropriate signals
• Generate the new state to be stored in the register