The Central Processing UnitInstruction Sets:Characteristicsand Functions

What is an instruction set?The complete collection of instructions that are understood by a CPUMachine CodeBinaryUsually represented by assembly codes

Elements of an InstructionOperation code (Op code)Do thisSource Operand referenceTo thisResult Operand referencePut the answer hereNext Instruction ReferenceWhen you have done that, do this...

Source and result operands can be in one of three areas:

Main memory (or virtual memory or cache)CPU registerI/O device

Instruction RepresentationIn machine code each instruction has a unique bit patternFor human consumption (well, programmers anyway) a symbolic representation (called mneumonics) is usede.g. ADD, SUB, LOADOperands can also be represented in this way

ADD A,B 0000 0001 1000 0000 1000 1010

Instruction TypesData processing (arithmetic and logic instructions)Data storage (memory instructions)Data movement (I/O instructions)Program flow control (test and branch instructions)

Number of Addresses (a)3 addressesOperand 1, Operand 2, Resulta = b + c;May be a forth - next instruction (usually implicit)Not commonNeeds very long words to hold everythingE.g. ADD A, B, C; store result of A+B in C

Number of Addresses (b)2 addressesOne address doubles as operand and resulta = a + bReduces length of instructionRequires some extra workTemporary storage to hold some resultsE.g. ADD A, B; store result of A+B in A

Number of Addresses (c)1 addressImplicit second addressUsually a dedicated register (called accumulator)Common on early machines (when memory was scarce)E.g. ADD B; add result of Acc. + B in Acc.

Number of Addresses (d)0 (zero) addressesAll addresses implicitUses a stacke.g. push a push b add pop c

c = a + b

Number of Addresses (e)E.g., Y=(A-B)/(C+DxE)

Number of Addresses (f)InstructionCommentSUB Y, A, BY A-BMPY T, D, ET DxEADD T, T, CT T+CDIV Y, Y, TY Y/T

Three-address instructions

InstructionCommentMOVE Y, A Y ASUB Y, B Y Y-BMOVE T, D T DMPY T, E T TxEADD T, C T T+CDIV Y, T Y Y/T

(b) Two-address instructions

Number of Addresses (g)InstructionCommentLOAD DAC DMPY EAC ACxEADD CAC AC+CSTOR YY ACLOAD A AC ASUB B AC AC-BDIV Y AC AC/YSTOR Y Y AC

(c) One-address instructions

How Many AddressesMore addressesMore complex (powerful?) instructionsMore registersInter-register operations are quickerFewer instructions per programFewer addressesLess complex (powerful?) instructionsMore instructions per program (more complex programs and longer total execution time) Faster fetch/execution of individual instructions

Design Decisions (1)Operation repertoire (how fast can we decode?)How many ops?What can they do?How complex are they?Data typesInstruction formats (how fast can we fetch?)Length (in bits) of op code fieldNumber of addressesVariable length instruction possible (more complex in fetching)Memory occupation is not really a problem anymore

Design Decisions (2)RegistersNumber of CPU registers availableWhich operations can be performed on which registers?Addressing modesThe mode or modes by which the address of an operand is specified.

RISC v CISC

Types of OperandMachine instructions operate on data. The most important general categories of data are:AddressesNumbersInteger or fixed point/floating point/decimalCharactersASCII etc.Logical DataBits or flags

Types of OperationData TransferArithmeticLogicalConversionI/OSystem ControlTransfer of Control

Data TransferSpecifySourceDestinationAmount of dataMay be different instructions for different movementse.g. IBM 370Or one instruction and different addressese.g. VAX

ArithmeticAdd, Subtract, Multiply, DivideSigned IntegerFloating point ?May includeIncrement (a++)Decrement (a--)Negate (-a)

LogicalBitwise operationsAND, OR, NOT

ConversionE.g. Binary to Decimal

Input/OutputMay be specific instructionsMay be done using data movement instructions (memory mapped)May be done by a separate controller (DMA)

Systems ControlPrivileged instructionsCPU needs to be in specific state Ring 0 on 80386+Kernel modeFor operating systems use

Transfer of ControlBranche.g. branch to x if result is zeroSkipe.g. increment and skip if zeroISZ Register1Branch xxxxADD ASubroutine callc.f. interrupt call

8086 InstructionsMOVADDMUL

Pentium (x86) Data Types8 bit Byte16 bit word32 bit double word64 bit quad wordAddressing is by 8 bit unitA 32 bit double word is read at addresses divisible by 4

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