the c embedded networks c field rogrammable g arraysvaughn/papers/micro2014_noc.pdf ·...

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THE CASE FOR EMBEDDED NETWORKSON CHIP ON FIELD-PROGRAMMABLE

GATE ARRAYS.................................................................................................................................................................................................................

THE AUTHORS PROPOSE AUGMENTING THE FPGA ARCHITECTURE WITH AN EMBEDDED

NETWORK ON CHIP TO IMPLEMENT THE SYSTEM-LEVEL COMMUNICATION

INFRASTRUCTURE AND MITIGATE THE HARDWARE DESIGN CHALLENGES FACED BY

CURRENT BUS-BASED INTERCONNECTS. WITH A FLEXIBLE INTERFACE BETWEEN THE NOC

AND THE FPGA FABRIC, AN EMBEDDED NOC MAINTAINS CONFIGURABILITY AND

SIMPLIFIES THE DISTRIBUTION OF I/O DATA THROUGHOUT THE CHIP, AND IS ALWAYS

MORE ENERGY-EFFICIENT COMPARED TO CUSTOM BUSES CONFIGURED INTO THE FABRIC.

......Computing applications areincreasing in size and complexity, whilemulticore CPUs and GPUs are con-strained by a power and memory wall.Field-programmable gate arrays (FPGAs)offer an alternative computing platform thatdemonstrates considerable performance-per-watt improvements for some applica-tions.1-4 These improvements are enabledby the customization of hardware to theexact application computing and memoryneeds. Such customization can make veryefficient use of the silicon but comes at thecost of high design time and effort.

Although CPUs and GPUs have a prede-fined datapath and memory hierarchy, eachFPGA application is designed out of an arrayof logic and other blocks to form a custom-ized datapath and memory hierarchy. Thisflexibility is both the blessing and the curse ofFPGAs; the high degree of customizationallows very fine-grained optimization and a

correspondingly high level of parallelism, butit comes at the cost of increased design effortand time. An FPGA designer must designthe custom computing kernels and then inte-grate the system using a form of system-levelinterconnect (often pipelined buses) thatconnects these kernels to each other and,more importantly, to external interfaces suchas DDRx and PCI Express (PCIe).

On CPUs and GPUs, connecting to exter-nal interfaces is as simple as specifying pro-gram instructions to access the relevantdevice registers; the hardware that moves thedata already exists. On FPGAs, however, usu-ally no program instructions exist, becausethe custom datapath implements only theexact application. The designer must archi-tect a custom interconnect that connects theassortment of custom kernels in an applica-tion and integrates them with interfaces toexternal memory and other I/Os. These ker-nels can have different data widths and

Mohamed S. Abdelfattah

Vaughn Betz

University of Toronto

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80 Published by the IEEE Computer Society 0272-1732/14/$31.00�c 2014 IEEE

operating frequencies and can be located any-where on the FPGA device. Furthermore,this system interconnect must adhere to thestringent timing constraints of external devi-ces, such as DDRx or PCIe, which is no triv-ial task.

For example, the task of creating the inter-connect to access DDR3 memory is verycommon in all reconfigurable computingapplications but is quite challenging. On theDDR3 side are 64 bits at 1,600 MHz, and,on the FPGA side, a custom bus configuredfrom the FPGA fabric can typically run at200 MHz. The only way to overcome thisspeed mismatch is to go parallel; 64 bits areconverted into a slow 512-bit-wide bus onthe FPGA. This huge bus uses many FPGAresources and hence much power, and itsdesign at 200 MHz is not simple. Systemintegration tools such as Xilinx’s XPS andAltera’s Qsys have been developed to auto-mate and ease the creation of a system inter-connect out of the FPGA fabric. Even withthese tools, however, connecting to externalmemory often requires many compilationand design tweaks and, therefore, high designtime and effort. We propose a change to thehardware itself, to embed networks on chip5

(NoCs) on the FPGA device to abstract themovement of latency-tolerant data, such asDDRx transfers, thereby simplifying the inte-gration of systems on FPGAs. As we willshow, this change also improves area andpower efficiency.

Network architectureNoCs are forecast to become the main

interconnection substrate for large systemson chip (SoCs); they have been described byBenini and De Micheli as “…the only pathto mastering the complexity of SoC designsin the years to come.”6 As FPGAs becomeever larger reconfigurable computing plat-forms, we believe that they too will benefitfrom NoCs in integrating their computingkernels, memory, and I/O. In this section, wepresent our NoC architecture alternatives.

Currently, hierarchical buses are config-ured out of the FPGA fabric to interconnectlarge systems. This approach lets us adapt thebus structure to each specific application butrequires the buses to be built from very

low-level components (logic blocks andprogrammable interconnect). NoCs in-stead communicate via packets transmittedthrough routers that provide both bufferingand switching. We embed application-agnostic NoC components in the FPGAsilicon to achieve high efficiency, while thedynamic switching of the NoC still lets usmove data between modules configured any-where in the FPGA. We must also be able toconnect any module on the FPGA to theNoC; we achieve this high level of configura-bility with a new “fabric port” between theembedded NoC and the FPGA fabric.

Figure 1 details the envisioned NoC, whichconsists of routers, links, and fabric ports.Crucially, NoC routers are connected to exter-nal interfaces, such as DDRx, PCIe, and Giga-bit Ethernet, allowing these interfaces toaccess the entire FPGA fabric through theembedded NoC with timing closure guaran-tees. We use high-performance, full-featured,packet-switched routers,7 because we believethat the capabilities offered by these routers—such as virtual channels—are useful for largeFPGA systems. A clear use-case for virtualchannels is to assign a higher priority tolatency-sensitive packets, such as DDR3 datadestined for a control processor, and lower pri-ority to more latency-tolerant transfers.

The fabric port allows access to the NoCby the diverse modules that can be

Router(Hard)

Computingmodule

Links(Hard or soft)

FPGA

DD

Rx

cont

rolle

rP

CIe

con

trol

ler Fa

bric

port

Figure 1. An embedded mesh network on chip (NoC) implemented on a

field-programmable gate array (FPGA). The NoC consists of routers, links,

and fabric ports.

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JANUARY/FEBRUARY 2014 81

configured into an FPGA by adapting thewidth, speed, and operating voltage of databetween a module on the FPGA fabric andthe embedded NoC. Unlike with NoCs formultiprocessors, we cannot predict the oper-ating frequency (between 100 to 400 MHz)or data width of our design modules. Eachmodule in a design could be different. We fixthe embedded NoC frequency to its maxi-mum speed (up to 1 GHz) and use a fabricport to match the fabric bandwidth to theNoC bandwidth at each NoC router, thusallowing each design module to run at anindependent speed and data width. This fab-ric port is hardwired to NoC routers on oneside and connects—through programmablemultiplexers—to the FPGA fabric intercon-nect on the other side, which allows it toreach any module configured on the FPGA.Inside the fabric port, we use time-domainmultiplexing logic to adapt the data width,and an asynchronous first-in, first-out(FIFO) buffer for clock-domain crossing. Wealso include voltage-domain-crossing circui-try to be able to run an embedded NoC at alower voltage than the rest of the FPGA,effectively trading excess NoC speed forenergy efficiency. We study the implementa-tion of NoC components8,9 and focus on thequestion of which components should beimplemented as “hard” or “soft.”

• Soft: Constructs a digital circuit byprogramming the reconfigurableFPGA fabric. This entails program-ming components, such as logicblocks, memories, and the soft inter-connect (short wires and program-mable multiplexers) between them.

• Hard: Fabricates a specialized (em-bedded) module on the FPGA silicon

using ASIC technology. Although thisapproach rids part of the FPGA of itsreconfigurability and requires anarchitectural change, a hard block ismuch more efficient than its softcounterpart. The interconnect alsocan be hardened. “Hard links” arededicated metal connections thatcontain no multiplexers; thus, theyare faster than soft links but arenonconfigurable.

Routers are 30� smaller, 6� faster, anduse 14� less power when implemented hardrather than soft,8,9 and the case for hardeningthem is compelling. For links, the answer isnot as decisive; we therefore propose two newNoC architectures and summarize thestrengths of each in Table 1.

Mixed NoC: Hard routers and soft linksIn this NoC architecture, we embed hard

routers on the FPGA and connect them viathe soft FPGA interconnect. A key questionis: How does a new hard block connect to theprogrammable FPGA interconnect? We usethe same structure (multiplexer size) as a logicblock (LB), thereby guaranteeing the sameinterconnection flexibility. This setup ensuresthat a hard router will not cause any intercon-nection hot spots or present a difficult targetfor CAD tools. Figure 2 shows a detailedillustration of such an embedded router; weensure that the router area is a multiple oflogic blocks to simplify the layout. Afteraccounting for the programmable multi-plexers to the soft interconnect, mixed NoCsare on average 20� smaller, 5� faster, and9� more power-efficient than fully softNoCs.8

Table 1. Summary of mixed and hard FPGA NoCs at 65 nm.

Feature Mixed NoCs Hard NoCs

Description Hard routers, soft links Hard routers, hard links

Special feature Configurable topology Low-voltage (low-V) mode

Comparison to soft NoCs Area 20� smaller 23� smaller

Speed 5� faster 6� faster

Power 9� less power 11� less power (15� low-V)

Frequency 730 MHz 910 MHz

Critical path Soft interconnect Switch allocator in router

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RECONFIGURABLE COMPUTING

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82 IEEE MICRO

Although this NoC achieves a majorincrease in efficiency and performance, itremains highly configurable, which is a hall-mark of FPGAs, by virtue of the soft links.Figure 3 shows how different network topolo-gies can be configured from the soft links,including topologies that use only a subset ofthe available routers or two separate NoCs.Furthermore, mixed NoCs do not stress thesoft interconnect much; the maximum utiliza-tion of FPGA interconnect by soft NoC linksin a localized region is approximately 11 per-cent. However, the speed of this type of NoC

is limited by the soft interconnect, which isoften slower than the fast hard routers.

Hard NoC: Hard routers and hard linksThis NoC architecture involves hardening

both the routers and the links as shown inFigure 4. Routers are connected to otherrouters using dedicated hard links; however,routers still interface to the FPGA fabricthrough programmable multiplexers con-nected to the soft interconnect. The NoCtopology is no longer configurable, but thehard links save area (because they require no

FPGA

Logicblock

Router

Programmable (soft)interconnect

Router orfabric port

Figure 2. Floorplan of a hard router with soft links embedded in the FPGA fabric (drawn to

scale). A typical hard router (32-bit width, 5 ports, 2 virtual channels) occupies the area

equivalent to approximately 9 logic blocks, and it connects to the FPGA’s soft interconnect

through programmable multiplexers.

Mesh Ring Butterfly

Figure 3. Examples of different topologies that can be implemented using the soft links in a

mixed NoC. Any topology can be implemented using the FPGA’s programmable

interconnect, limited only by the number of ports available on the hard routers.

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multiplexers) and can run at higher speedscompared with soft links, allowing the NoCto achieve the router’s maximum frequency.After accounting for the wire drivers and theprogrammable multiplexers needed at therouter-to-FPGA-fabric ports, this NoC is onaverage 23� smaller, 6� faster, and con-sumes 11� less power than a soft NoC.

With hard routers and hard links, anNoC is almost completely separate from theFPGA fabric, connecting only throughrouter-to-fabric ports. This approach makesit easy to use a separate, lower-voltage powergrid for the NoC, letting us trade excess NoCspeed for power efficiency. We therefore pro-pose a low-power version of the hard NoCthat operates at a lower voltage. For example,65-nm Stratix III FPGAs use a supply voltageof 1.1 V, whereas our low-power NoC saves33 percent dynamic power by operating at0.9 V in the same process.9

Embedded NoCs versus currentinterconnect solutions

FPGA designers currently use soft busesto create the communication infrastructureof large systems (see the “CommunicationInfrastructure for FPGA Computing” sidebarfor more information). The resulting

hierarchical bus consists primarily of widepipelined multiplexers configured out ofFPGA logic blocks and a soft interconnect(as shown in Figure 5). We propose changingthe FPGA architecture to include anembedded (mixed or hard) NoC instead.Consequently, we must compare the effi-ciency of the soft bus-based interconnect tothe proposed embedded NoC. Previous NoCversus bus comparisons have shown thatNoCs become the more efficient intercon-nect only for large systems;10 however,because we compare a hard NoC to a softbus, we find the NoC exceeds bus efficiencyeven for small systems.

The communication infrastructure is usedto connect an application to DDRx memory,which is necessary for all sizeable FPGA sys-tems. We compare the efficiency of theapplication-tailored soft buses generated byQsys (Altera’s system integration tool) to ourembedded NoC, when used to connect toexternal memory. By varying the number ofmodules accessing memory, we emulate dif-ferent applications and study interconnectsof different sizes and interconnection capabil-ities. We also vary the physical distancebetween the traffic generators and the mem-ory they are trying to access, from “close” to“far,” meaning on opposite ends of the chip.

FPGA

Logicblock

Router

Dedicated (hard)interconnect

Routerport

Figure 4. Floorplan of a hard router with hard links embedded in the FPGA fabric (drawn to

scale). A typical hard router (32-bit width, 5 ports, 2 virtual channels) occupies the area

equivalent to 9 logic blocks. Hard links, or dedicated metal wires with repeaters, connect hard

routers in a fixed topology.

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84 IEEE MICRO

The system-level interconnect may span alarge distance for two reasons; either theFPGA is full and its modules are scatteredacross the chip, or I/Os on opposite ends of

the chip are connected to one another. Thisphysical remoteness makes generating theQsys bus-based interconnect that ties every-thing together more difficult.

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Communication Infrastructure for FPGA ComputingHigh-level synthesis lets designers use program-

ming languages similar to Java or C to code for

FPGAs instead of hardware description languages

like Verilog, which, in turn, facilitates reconfigura-

ble computing. Two examples are Maxeler’s Max-

Compiler and Altera’s OpenCL Compiler, which

have been used to accelerate applications related

to geosciences,1 financial analysis,2 video com-

pression,3 and information filtering4 while demon-

strating order-of-magnitude gains in performance

and power efficiency compared to multicore CPUs

and GPUs.

Figure A shows the anatomy of a typical com-

puting application implemented on an FPGA, such

as a Maxeler or Altera system. It consists of

application-tailored computing kernels, on-chip

memory, and at least two connections to external

devices—a host CPU through PCIe links and off-

chip memory through DDRx interfaces. These com-

ponents form the basic infrastructure necessary

for operation, and the customization of the appli-

cation kernels and the memory hierarchy allows

the implementation of different applications. The

application designer creates a custom communica-

tion infrastructure out of the FPGA’s low-level programmable logic

and interconnect to connect these diverse sets of blocks. This infra-

structure must at least be capable of buffering data, adapting width

and frequency, and distributing data across the chip. Its design is

challenging for many reasons.

First, this interconnect’s operating frequency must be high

enough to satisfy the stringent operating frequencies of each I/O

interface (satisfying a design’s timing constraints is called timing

closure). Second, this interconnect often spans the entire physical

dimension of the FPGA to connect I/O controllers and application

kernels on opposite ends of the chip, making timing closure more

difficult and necessitating the addition of pipeline registers. Third,

for a different FPGA device, this communication infrastructure

could require redesign because it targets different hardware;

thus, the whole application usually is not portable between devi-

ces without further hardware modifications. Additionally, to

implement all the required functionality, this interconnect

becomes power hungry and area intensive, because it is config-

ured out of the FPGA’s general-purpose logic blocks and intercon-

nect. The design of this communication infrastructure is a

hindrance to reconfigurable computing on FPGAs, because it

involves tedious and time-consuming low-level hardware design

and is not portable between devices.

References1. O. Lindtjorn et al., “Beyond Traditional Microprocessors for

Geoscience High-Performance Computing Applications,”

IEEE Micro, vol. 31, no. 2, 2011, pp. 41-49.

2. G.C.T. Chow et al., “A Mixed Precision Monte Carlo Meth-

odology for Reconfigurable Accelerator Systems,” Proc.

20th ACM/SIGDA Int’l Symp. Field Programmable Gate

Arrays (FPGA 12), 2012, pp. 57-66.

3. D. Chen and D. Singh, “Fractal Video Compression in

OpenCL: An Evaluation of CPUs, GPUs, and FPGAs

as Acceleration Platform,” Proc. 18th Asia and South

Pacific Design Automation Conf. (ASP-DAC 13), 2013,

pp. 297-304.

4. D. Chen and D. Singh, “Using OpenCL to Evaluate the Effi-

ciency of CPUs, GPUs and FPGAs for Information Filtering,”

Proc. 22nd Int’l Conf. Field Programmable Logic and Appli-

cations (FPL 12), 2012, pp. 5-12.

FPGA

DD

Rx

cont

rolle

r(s)

PCIe controller

Applicationkernels

Communication infrastructure

Host CPU

Mem

ory

DD

Rx controller(s)

Mem

ory

On-chipmemory

hierarchy

Figure A. Architecture of a typical reconfigurable computing system. An

FPGA is connected through PCIe to a host processor and through DDRx

controllers to external memory. “Communication infrastructure” refers to

the interconnect that connects the application kernels to external devices

and on-chip memory.

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Design effortTo highlight the design effort necessary to

implement different bus-based systems, Table2 lists the steps taken to meet timing con-straints using Qsys. A small system, with threemodules located physically close to externalmemory, does not meet timing with defaultsettings. Typically, designers first would switchon all optimization options in the CAD tools,causing a major increase in compile time toimprove timing closure. Turning on extraoptimization improved design frequency butstill fell short of the target by 6 MHz. We then

enabled pipelining at various points in thebus-based interconnect between modules andexternal memory. Only with three pipelinestages did we meet timing, and this resultcame at a 45 percent area penalty and 340 per-cent power increase. Placing the modulesphysically farther away from memory makesthe bus physically larger and therefore moredifficult to design and less efficient: more than2� the area and power. Furthermore, largersystems with nine modules are still more diffi-cult and time-consuming to design even withsophisticated tools like Qsys. Even after

Table 2. Design steps and interconnect overhead of implemented systems.

System size

Physical

proximity Design effort Frequency Area Power

Small (3 modules) Close — � 187 MHz 95 LBs 17 mW

Max tool effort (plus physical synthesis) � 194 MHz 95 LBs 17 mW

Auto interconnect pipelining (3 stages) � 227 MHz 139 LBs 75 mW

Far — � 92 MHz 96 LBs 48 mW



Large (9 modules) Far — � 70 MHz 249 LBs 49 mW



Manual interconnect pipelining (1 stage) � 216 MHz 801 LBs 307 mW

FPGA

Module1

200 MHz

Module2

200 MHz

DDR3 controller (64-bit 800 MHz)

Physical distance affects timing

closure

Bus-based interconnect

Pipelineregisters

Multiplexer/demultiplexer

Arbiter

200 MHz512 bits

aFIFO

FPGA

Module1

Modulen

Embedded hard NoC

DDR3 controller (64-bit 800 MHz)

910 MHz128 bits

Module2

Module n

250 MHz

Figure 5. Connecting multiple modules to DDR3 memory using a bus-based interconnect or

the proposed embedded NoC. We use random traffic generators for these modules to

emulate an application’s compute kernels or on-chip memory.

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86 IEEE MICRO

enabling the maximum interconnect pipelin-ing, we must identify the critical path andmanually insert an additional stage of pipelineregisters to reach 200 MHz. This timing clo-sure process is largely ad hoc and relies on trialand error and designer experience. Our prop-osition eliminates this time-consuming proc-ess; an embedded NoC is predesigned todistribute data over the entire FPGA chipwhile meeting the timing and bandwidthrequirements of interfaces such as DDR3.

AreaFigure 6 shows how the area and power of

bus-based interconnects and embeddedNoCs vary with the number of modules. Wecompare a Qsys-generated, 512-bit, soft busto a 16-node, 128-bit, hard NoC embeddedonto the FPGA, as shown in Figure 5. Ourprevious work8,9 details the methodology forfinding the area, speed, and power of hardNoCs; we follow the same methodology andbuild on it in this work. For example, wecompute hard NoC power for our bench-marks by first simulating the benchmarks tofind the total data bandwidth flowingthrough the NoC; we then multiply the totalbandwidth by our “Power per BW” metricthat we computed for hard NoCs.9

The plotted area of the hard NoC is inde-pendent of the design size up to 16 nodes,because we must prefabricate the entire NoConto the FPGA chip and always pay its com-plete area cost. Nevertheless, the NoC’s entirearea is less than that of the optimized bus-based interconnect for designs with more thanthree modules accessing DDR3 memory.Moreover, buses that are generated by Qsysbecome larger and more difficult to designwith more connected modules, consuming upto 6 percent of the logic blocks on largeFPGAs to connect to a single external mem-ory. Bus-based and NoC-based communica-tion can be combined into one system,maintaining the high configurability that’s cru-cial to FPGAs. For example, if more than 16modules access an external memory, two mod-ules may be combined using a small soft bus toshare one NoC fabric port. Additionally, por-tions of a design with low bandwidth can alsochoose to use a bus for communication.

The embedded NoC includes clock-crossing and data-width adapters at its fab-ric ports, letting us connect modules runningat any independent clock frequency. Thisapproach is common in commercial designsbecause IP modules could have any fre-quency within the limits of the FPGA, ratherthan matching the DDR3 fabric interface

0

2

4

6

8

10

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14

0

500

1,000

1,500

2,000

2,500

3,000

1 3 5 7 9 11 13 15 17

Are

a of

Str

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(%)

Qsys bus + clock crossing

Qsys bus

Are

a (e

qui

vale

nt lo

gic

blo

cks)

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Hard NoC

(a)

Applications: Packet processing Broadcast video

(c)

0

200

400

600

800

1,000

1,200

1 3 5 7 9 11 13 15 17

Dyn

amic

pow

er (

mW

)

Number of modules

Qsys bus + clock crossing

Qsys bus

Hard NoC

(b)

Figure 6. Comparison of area and power of Qsys bus-based interconnect

and embedded NoCs with a varying number of modules accessing external

memory. Example applications corresponding to the number of modules are

annotated.

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frequency of 200 MHz. Figure 6 plots thearea of Qsys buses when the connected mod-ules operate at 250 MHz and thus requireasynchronous FIFOs to connect to the bus.These FIFOs are as wide as the bus (512bits) and hence incur a large area overhead;in fact, the area required by a one-moduleQsys system with clock crossing is approxi-mately equal to the complete hard NoC area.

Each link of the hard NoC can carry theentire bandwidth of an 800-MHz, 64-bitDDR3 channel; the NoC is underutilized inour study. Consequently, it can support con-nectivity to multiple I/O interfaces at oncewith no additional area; this capability fur-ther widens its efficiency advantage overbuses for more complex systems. For exam-ple, an FPGA in a Maxeler system connectsto six DDR3 controllers.

Dynamic powerFigure 6 shows that NoC dynamic power

is also somewhat constant compared with thenumber of modules accessing one DDR3interface; this is true for two reasons. First, wealways move the same bandwidth on the NoCdivided equally among all accessing modules,so the interconnect itself always transports thesame total bandwidth. Second, we average thepower for our systems when their modules areplaced physically close and far from theDDR3 interface, meaning that the samebandwidth moves a similar average distancefor all systems. We use the same assumptionsfor Qsys buses. These buses, however, becomemore power hungry with larger systems,because the bus itself uses more resources—such as wider multiplexers and additional softinterconnect—when spanning a larger dis-tance to connect to a higher number of mod-ules. Furthermore, we increasingly need toadd power-hungry pipeline registers for largerQsys buses to meet the 200-MHz timingrequirement. In contrast, the embedded NoCrouters are unchanged when we increase thenumber of modules. As Figure 6 shows, theembedded NoC is consistently more powerefficient than tailored soft buses. The powergap widens further when we include clock-crossing FIFOs in a Qsys-generated bus;whereas, an embedded NoC already performsclock-crossing in its fabric ports.

LatencyThe latency of Qsys buses varies accord-

ing to the level of pipelining; in our systems,two or three pipeline stages typically arerequired. The average latency is therefore12.5 ns. The embedded NoC requires ahigher number of cycles; the average numberof hops for our 16-node NoC is 3.5, and thelatency per hop is three cycles in a lightlyloaded system, such as the single-DDR3 sys-tem we study, leading to a latency of 11.5 ns.The fast 910-MHz NoC clock puts NoClatency on par with buses despite the highernumber of cycles.

We have discussed the usage of NoCs forinterconnection to DDR3 memory, which isnaturally latency tolerant. Other I/O interfa-ces, such as PCIe, can also tolerate variablelatency, making the NoC suitable for con-necting to these important I/Os. However,the NoC can also be used for interconnect-ing application kernels to one another if theyfollow a latency-insensitive design (LID)methodology.11 Although LID is not suit-able for all applications, we believe it can notonly mitigate scalability limitations imposedby large silicon chips11 but also boost theproductivity of reconfigurable computing.Combining embedded NoCs and LID canallow application kernels to be portableand easily composed, without having to re-design for a different timing constraint eachtime a designer creates a new system ormoves between devices. This approachmakes hardware design more modular withthe communication within an applicationabstracted in the NoC. Additionally, it mir-rors how software design allows simple appli-cation composition using functions fromdifferent libraries, with communicationabstracted through shared memory. Ourfuture work will focus on the design toolsnecessary to target NoC-augmented FPGAswith LID.

H igh design effort remains a major bar-rier to reconfigurable computing with

FPGAs. A major hurdle is the design—usingthe low-level FPGA interconnect—of thecommunication infrastructure that tiestogether different parts of a computingapplication. We propose augmenting theFPGA with an embedded NoC to simplify

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88 IEEE MICRO

system-level interconnection while maintain-ing the FPGA’s configurability. A high-band-width NoC can be integrated onto a modernFPGA for a core area increase of only 1.4 per-cent. When compared with the application-tailored buses currently used for system inte-gration, embedded NoCs are more efficientin terms of area and power, even thoughthey are overprovisioned in capability andbandwidth. MICRO

AcknowledgmentsWe thank Daniel Becker, Natalie Enright

Jerger, Desh Singh, Dana How, and DavidLewis for their helpful discussion and feed-back. This work is funded by Altera,NSERC, and Vanier CGS.

....................................................................References

1. O. Lindtjorn et al., “Beyond Traditional

Microprocessors for Geoscience High-

Performance Computing Applications,”


2. G.C.T. Chow et al., “A Mixed Precision

Monte Carlo Methodology for Recon-

figurable Accelerator Systems,” Proc. 20th

ACM/SIGDA Int’l Symp. Field Program-

mable Gate Arrays (FPGA 12), 2012,

pp. 57-66.

3. D. Chen and D. Singh, “Fractal Video Com-

pression in OpenCL: An Evaluation of CPUs,

GPUs, and FPGAs as Acceleration Plat-

form,” Proc. 18th Asia and South Pacific

Design Automation Conf. (ASP-DAC 13),

2013, pp. 297-304.

4. D. Chen and D. Singh, “Using OpenCL to

Evaluate the Efficiency of CPUs, GPUs and

FPGAs for Information Filtering,” Proc. 22nd

Int’l Conf. Field Programmable Logic and

Applications (FPL 12), 2012, pp. 5-12.

5. W. Dally and B. Towles, “Route Packets,

Not Wires: On-Chip Interconnection

Networks,” Proc. 38th Design Automation

Conf. (DAC 01), 2001, pp. 684-689.

6. L. Benini and G. De Micheli, “Networks on

Chips: A New SoC Paradigm,” Computer,

vol. 35, no. 1, 2002, pp. 70-78.

7. D.U. Becker, “Efficient Microarchitecture for

Network-on-Chip Router,” PhD dissertation,

Dept. of Electrical Engineering, Stanford

University, 2012.

8. M.S. Abdelfattah and V. Betz, “Design

Tradeoffs for Hard and Soft FPGA-based

Networks-on-Chip,” Proc. Int’l Conf. Field-

Programmable Technology (FPT 12), 2012,

pp. 95-103.

9. M.S. Abdelfattah and V. Betz, “The Power

of Communication: Energy-Efficient NoCs

for FPGAs,” Proc. 23rd Int’l Conf. Field Pro-

grammable Logic and Applications (FPL 13),

2013, pp. 1-8.

10. C.A. Zeferino et al., “A Study on Communi-

cation Issues for Systems-on-Chip,” Proc.

15th Symp. Integrated Circuits and System

Design (ICSD 02), 2002, pp. 121-126.

11. L. Carloni and A. Sangiovanni-Vincentelli,

“Coping with Latency in SOC Design,”


Mohamed S. Abdelfattah is a PhD candi-date in the Department of Electrical andComputer Engineering at the University ofToronto. His research interests include newcommunication architectures and CAD forhigh-performance FPGAs. Abdelfattah hasan MSc in electrical and computer engineer-ing from the University of Stuttgart.

Vaughn Betz is an associate professor in theDepartment of Electrical and ComputerEngineering at the University of Toronto.His research interests include FPGA archi-tecture and CAD, and the use of reconfigur-able hardware to accelerate computation. Hehas a PhD in Electrical and Computer Engi-neering from the University of Toronto.

Direct questions and comments about thisarticle to Mohamed S. Abdelfattah, Univer-sity of Toronto, Electrical and ComputerEngineering, 10 King’s College Road, Tor-onto, ON, Canada, M5S 3G4; [email protected].

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