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The BaBar Silicon Vertex Tracker (SVT)

Claudio CampagnariUniversity of California

Santa Barbara

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Outline

• Requirements

• Detector Description

• Performance

• Radiation

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SVT Design Requirements (TDR)Performance Requirements• z resolution < 130 m

• Single vertex resolution < 80 m.

• Stand-alone tracking for PT < 100

MeV/c.

Performance Requirements• z resolution < 130 m

• Single vertex resolution < 80 m.

• Stand-alone tracking for PT < 100

MeV/c.

PEP-II Constraints• Permanent dipole (B1) magnets at +/- 20 cm from IP.

• Polar angle restriction: 17.20 < < 1500.• Must be clam-shelled into place after installation of B1 magnets

• Bunch crossing period: 4.2 ns (nearly continuous interactions).

• Radiation exposure at innermost layer (nominal background level):• Average: 33 kRad/year.• In beam plane: 240 kRad/year.

• SVT is designed to function in up to 10 X nominal background.

PEP-II Constraints• Permanent dipole (B1) magnets at +/- 20 cm from IP.

• Polar angle restriction: 17.20 < < 1500.• Must be clam-shelled into place after installation of B1 magnets

• Bunch crossing period: 4.2 ns (nearly continuous interactions).

• Radiation exposure at innermost layer (nominal background level):• Average: 33 kRad/year.• In beam plane: 240 kRad/year.

• SVT is designed to function in up to 10 X nominal background.

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SVT characteristics• Five layers, double sided (R and z)

– Barrel design, L4 and 5 not cylindrical– 340 wafers, 6 different types– Low mass Kevlar-Carbon Fiber support ribs

• Upilex fanouts to route signal to ends• Double-sided AlN HDI (104 of these)

– Outside tracking volume– Mounted on Carbon Fiber cones (on B1

magnets)• Atom chips

– 1156 chips, 140K channels

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Space Frame and Support Cones…mounted on B1

magnets

6Layer 1,2,(3): vertexingLayer (3),4,5: tracking

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SVT Modules

Z-SideZ-Side

Phi-SidePhi-Side

Si Wafers Carbon/Kevlar fiberSupport ribs

High DensityInterconnect

(mechanical model) Micro-bondsMicro-bondsFlexible Upilex Fanout

Fanout Properties:• < 0.03 % X0

• 0.52 pF/cm

Fanout Properties:• < 0.03 % X0

• 0.52 pF/cm

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SVT High Density Interconnect

AToMChips

UpilexFanout

MountingButtons

BergConnector

Flexible Tail (testing version)Functions:

• Mounting and cooling for readout ICs.

• Mechanical mounting point for module.

Functions:

• Mounting and cooling for readout ICs.

• Mechanical mounting point for module.

Features:• AlN substrate.• Double sided.• Thermistor for temp. monitor.• 3 different models.

Features:• AlN substrate.• Double sided.• Thermistor for temp. monitor.• 3 different models.

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Silicon Wafers

Features•Manufactured at Micron.•300 m thick.•6 different wafer designs.•n- bulk, 4-8 kcm.•AC coupling to strip implants.•Polysilicon Bias resistors on wafer, 5 M

Features•Manufactured at Micron.•300 m thick.•6 different wafer designs.•n- bulk, 4-8 kcm.•AC coupling to strip implants.•Polysilicon Bias resistors on wafer, 5 M

Bulk Properties•Bias current: 0.1 to 2.0 A

•Bulk current: 0.1 to 2.0 A

•Depletion voltage: 10 to 45 V

Bulk Properties•Bias current: 0.1 to 2.0 A

•Bulk current: 0.1 to 2.0 A

•Depletion voltage: 10 to 45 V

Strip Propertiesn-side n-side n-side p-side

•Strip Pitch: 50 m55 m 105 m 50 m

•Inter-strip C: 1.1 pF/cm 1.0 pF/cm 1.0 pF/cm 1.1 pF/cm

•AC decoupling C: 20 pF/cm 22 pF/cm 34 pF/cm 43 pF/cm

•Implant-to-back C: 0.19 pF/cm 0.36 pF/cm 0.17 pF/cm

•Bias R: 4 to 8 M 4 to 8 M 4 to 8 M 4 to 8 M

Strip Propertiesn-side n-side n-side p-side

•Strip Pitch: 50 m55 m 105 m 50 m

•Inter-strip C: 1.1 pF/cm 1.0 pF/cm 1.0 pF/cm 1.1 pF/cm

•AC decoupling C: 20 pF/cm 22 pF/cm 34 pF/cm 43 pF/cm

•Implant-to-back C: 0.19 pF/cm 0.36 pF/cm 0.17 pF/cm

•Bias R: 4 to 8 M 4 to 8 M 4 to 8 M 4 to 8 M

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Silicon Wafers

Bias ring p+ Implant

Al

p+ strip side

P-stop n+ Implant

Polysiliconbias resistor

Polysiliconbias resistor

Edge guard ring

Edge guard ring

n+ strip side

50 m

55 m

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The AToM Chip

Features:•128 Channels per chip•Rad-Hard CMOS process (Honeywell)•Simultaneous

– Acquisition– Digitization– Readout

•Sparsified readout•Time Over Threshold (TOT) readout•Internal charge injection

Features:•128 Channels per chip•Rad-Hard CMOS process (Honeywell)•Simultaneous

– Acquisition– Digitization– Readout

•Sparsified readout•Time Over Threshold (TOT) readout•Internal charge injection

Custom Si readout ICAToM = A Time Over threshold Machine

Custom Si readout ICAToM = A Time Over threshold Machine 5.7 mm

8.3 m

m

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The AToM Chip

CAL DAC

Shaper

ThreshDAC

CompPREAMP

TOT CounterTime Stamp

Event TimeEvent Number

Revolving Buffer

193 Bins

Si

Buffer

Buffer

Chan # Sp

ars

ifica

tion

Re

ad

ou

t Bu

ffer

CINJ

CAC

SerialData Out

Amp, Shape, Discr, Calib•5-bit CAL DAC (0.5 fC/count)•5-bit Thr DAC (0.05 fC/count)•Shaping time 100 - 400 ns•Typical threshold 0.6-0.9 fC

Amp, Shape, Discr, Calib•5-bit CAL DAC (0.5 fC/count)•5-bit Thr DAC (0.05 fC/count)•Shaping time 100 - 400 ns•Typical threshold 0.6-0.9 fC

Trigger Latency Buffer•15 MHz Sample rate•Total storage = 12.7 us

Trigger Latency Buffer•15 MHz Sample rate•Total storage = 12.7 us

TOT, Tstamp, Buffering•4 bits TOT (logarithmic)•5 bits Hit Tstamp

(67 ns/count)•4 buffers / channel

TOT, Tstamp, Buffering•4 bits TOT (logarithmic)•5 bits Hit Tstamp

(67 ns/count)•4 buffers / channel

15 MHz

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Performance

• Calibration, Noise• Occupancy• Efficiency• Intrinsic Resolution

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Calibration• Noise, gain, pedestals, bad

channels obtained from scanning threshold with and without charge injection and counting hits– 600K errfun fits, 150K linear fits– once a day; takes ~ 2 minutes

• Very stable• Downloadable chip parameters

have not changed between Oct 1999 and ~ 2004 – needed to change because of rad

damage

Threshold

Hits

Offset

Noise

Qinj CountsO

ffset

Cou

nts

Threshold DACOffset

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Alignment: a curiosity• SVT tied to machine elements, not to DCH• SVT is always moving w.r.t. BaBar due to e.g.

thermal excursions.• Position of SVT as rigid body is monitored

and fed back to reconstruction ~ every hour

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NoiseLayer ENC Layer ENC

1 1200 1z 880

2 1240 2z 970

3 1440 3z 1180

4 1350 4z 1210

5 1600 5z 1200

Layer ENC Layer ENC

1 1200 1z 880

2 1240 2z 970

3 1440 3z 1180

4 1350 4z 1210

5 1600 5z 1200

1 MIP at normal incidence, about 23,000 electrons

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Cluster efficiency

(SW + HW)

Excluding malfunctioning readout sections

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Resolution

Blue: dataRed: MC

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Standalone reconstruction of low PT tracks

Reconstruction of s fromD* D s

is (mostly) with SVT alone

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Most of the detector is working• Redundancy built in, e.g., 2 data and control paths• Chips are only active electronics that is not accessible • Layer 1 perfect• 4/208 sections not working• Problems are from

• shorts on hybrids• elec. probems on wafers

short

Both noisy

2 chips masked short

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Radiation

• Monitored by 12 diodes at ~ radius of layer 1• Diodes can abort beam• Operation tricky due to heavy radiation damage• Now also use diamonds

SVTRAD System

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Measured absorbed Dose

midplane

non-midplane

Few MRad in the horizontal planeMostly from showers from off-momentum beam particlesNot from Physics

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Consequences of high doses

• Bulk damage to Si– increase ILEAK increase in noise

– type inversion

• Damage to chips– originally tested to 5 MRad with Co

source

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Bulk Damage

from Moll

NIEL scaling: high energy electron causesignificant damage (~1/10 of hadrons)

Not appreciated by us originally

~ D

am

age e

ffect

iven

ess

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• C-2 vs V curve show inversion• Results in ~ agreement with NIEL scaling hypothesis• Charge-collection-efficiency after local type inversion measured: OK

• C-2 vs V curve show inversion• Results in ~ agreement with NIEL scaling hypothesis• Charge-collection-efficiency after local type inversion measured: OK

Tests at Elettra (Trieste)

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Expected Atom Chip Damage

Radiation damage on AToM chip• studied using Co60 sources at LBL and SLAC, up to 5 MRad.• No digital failures (if chip power on)• Gain loss 4.2% / MRad• Noise increase: 19%/MRad

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HDI Card in horizontal plane

Th

resh

old

off

set

(cou

nts

)

Channel

Unexpected Phenomenon: Pedestal Shift

• Pedestal (Threshold offset) started to increase• Behavior associated with AToM chip location, not with

strip location• Remember: we have 1 pedestal value per chip!!!

Chip 4

20 threshold DACs = 1fC

Ped

est

al

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Pedestal Shift (cont.)• Sets in at an integrated radiation dose of 1 Mrad• But then it recovers. • Effect reproduced at Elettra• Ride out the storm by adjusting thresholds as

well as we can

Effect reproduced @ Elettra

Channel

Del

ta T

hre

shol

d (

cou

nts

)

narrow e- beam AToM Chip

Pedestal recovers

Th

resh

old

off

set

(cou

nts

)

Integrated Radiation

1 Mrad

2 Mrad

Groups of 8 channels

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Unexpected Phenomenon:Leakage Current Increase

• Since May 2004 an anomalous increase in the bias current for some modules has been observed

• Only Layer-4 modules: not a simple radiation damage effect

• No geometrical correlation • Consequences:

increasing occupancies• Coincides with beginning of

"trickle injection" operation– beam always on!!!!!

300uA

10uA

Apr May Jun

I Lea

k (

A)

Days in 2004

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I Lea

k (A

)

Time (hrs)

Leakage Current Increase

-20V

-20V

+20V

+20V

E

Nside

Pside

Nside

Pside

VL5-L4

=+40V

Hypothesis:

Accumulation of static charge on the silicon surface. The charge is beam-induced drifts because of the field between the facing sides of different layers.Causes increase in electric field at junctionedge, inducing a soft junction breakdown.

By varying the potential drop across the air between the layers we can control the effect

1800 0000 0600 1200Solution: change relative voltages, L4 vs L5

Also, increase humidity of air

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Conclusions

• BaBar SVT has been working well for about 7 years now– Installed and cabled in April 99– Taking physics quality data since June 99

• There have been a few surprises along the way, but we have managed to survive