FJectronic Engineering

TIssue 432 The Industry Newspaper For Engineers And Technical Management

The Acid Test

Monday, May 4, 1987

Using an EPLD vendor's application, the same circuit was built with a Logic Cell Array.The comparison provides real insight to the differences between these two technologies.

By Steven K. KnappField Applications Engineer

XiJinx Inc.

A s with a processor, a PLD's ar­chitecture determines its func­tional logic density and its per­

formance.Among processors, general-purpose

microprocessors and application-ori­ented devices like digital signal pro­cessors share many similar internallogic structures and functions. DSPshave a more rigid architecture, de­signed for particular applications,while general-purpose microproces­sors address a much wider set of appli­cations. The same situation exists inthe world of PLDs.

Until recently, the sum-of-products(SOP, also known as AND-OR) struc­ture was the only one available forPLDs. Its simple, fixed architecture fitsa variety of low-density, high-speed ap­plications. These include fast, wide log­ic functions found in decoders, multi­plexers and counters.

Some recently introduced high-den­sity PLDs are based on extensions ofthe conventional AND-OR architec­ture. Examples include the MMI64R32 MegaPAL and the AlteraEP1800 Erasable Programmable Log­ic Device (EPLD).

Like a DSP processor, the sum-of­products architecture of these devicesefficiently meets certain needs. Howev­er, this architecture is not suitable forhigher-density, register-intensive ran­dom logic structures commonly foundin logic designs.

Logic Cell ArrayThe Programmable Gate Array dif­

fers vastly from the conventional sum-

of-products architecture. Its flexible,register- and I/O-rich, array-style ar­chitecture addresses a wider set of com­mon logic design problems.

Its Logic Cell Array architecture con­sists of three basic programmable ele­ments: inpuUoutput blocks, configura­ble logic blocks and programmableinterconnects.

Each I/O block can be individuallyconfigured as a direct or registered in­put, a direct or three-state output or asa bidirectional I/O.

The configurable logic blocks con­tain combinatorial logic plus storageelements. The combinatorial logicwithin each block implements anypossible single function of four vari­ables, or any two functions of up tothree variables. The storage elementis configurable as an edge-triggeredflip-flop, or as a level-sensitive latch,both with asynchronous SET and RE­SET inputs. The programmable inter­connect allows each of the storageelements to be clocked either synchro­nously or asynchronously.

Three levels of programmable inter­connect resources provide the intercon­nection between blocks:

• Direct interconnect allows fastconnections between adjacent blocks.

• General-purpose signals travelthrough an array of switching matricesthat yield an efficient means of con­necting scattered random logic.

• Long metal lines that traverse thechip distribute clock or other signalswith high fan-out or requirements forminimum skew.

The best way to illustrate the differ­ence between the Logic Cell Array andthe more conventional AND-OR archi­tectures is through a design example.

An X-Y position controller designwas originally developed by Altera as

an application example for its EP1800.The design is fairly simple, and illus­trates the capability of programmablelogic to address the problems faced bylogic designers. The example can beused to demonstrate the capabilities ofboth the Altera EPLD, and the XilinxLogic Cell Array.

X-Y position controllers are em­ployed in a variety of design applica­tions to control motors for printers,plotters, robotics, and numerical con­trollers. The controller compares thedesired location loaded from an exter­nal processor with the present motorposition stored within the PLD. Basedon the results of the comparison, thecontroller drives two four-phase step­per motors (an X- and a V-position mo­tor) to its desired position.

In this design, X- and V-position datais loaded into the device from an exter­nal microprocessor. The 1,800-gateEPLD has no input storage elements,so the data must be held valid by someexternal device until both motors reachtheir final position. Since the Logic CellArray has input flip-flops which holdthe X- and the V-position data, it offersa simpler interface to the processor.

The desired position data is com­pared against the present positiondata. The result of the comparisondrives the 7-bit up/down counterswhich, in turn, drive the state-machinemotor control. The stepper motors usedin the application have 7.5 degree full­step increments with optional 3.75 de­gree half-step increments available. A7-bit binary up-down counter is re­quired to keep track of the 96 motorsteps required to rotate each motor afull 360 degrees.

In the EPLD designs, seven macro­cells are used to implement the binaryup/down counter for each half of the

~:XILINX Xilinx, Inc., 2069 Hamilton Avenue, San Jose, CA 9512~ • (408) 559-n78

Technology Update: PROGRAMWlABtE LOGIC

Clockwise-X

position controller. Because of the low­frequency clock (500 kHz), this samecounter requires only seven Logic CellArray logic blocks. If this were a high­speed counter, a few additional blockswould perform some level of carry-look­ahead.

Ifthe desired position is greater thanthe present position, the state-ma­chine-based motor control drives thestepper motor clockwise. If the positionis less, the controller drives the motorcounter-clockwise.

Four EPLD macrocells are requiredto implement the state-machine foreach half of the position controller,while seven Logic Cell Array logicblocks are required to implement thesame function.

To signal the processor that the en­tire operation is complete, an opendrain interrupt signal is generatedwhen both the X- and the Y-positionmotor have reached their final location.This also signals the processor that fur­ther motor action may be taken. A mas­ter RESET signal resets the presentposition to zero.

Resource RequirementsBased on the requirements of the

design, the X-Y position controller ex­ample requires 47 of the 48 macrocellsin the 1,800-gate EPLD and all of its64 I/O pins. A number of the I/O pinsare used simply because a register ishard-connected to the pin. The two 7­bit counters, for example, use 14 I/Opins because they cannot be buried.The X-Y controller design uses 98 per­cent of the macrocells and 100 percentof its I/O pins.

The same design (plus the inputdata registers) fits in 49 configurablelogic blocks and 27 input/outputblocks in a Logic Cell Array (theMASTER RESET input uses the LogicCell Array's dedicated master r~set

pin). Fewer I/O pins are required,since the 7-bit up/down counters andthe state-machines were buried in theLogic Cell Array design.

The X-Y controller design would oc­cupy 77 percent of the 1,200-gateXC2064's logic blocks and 47 percentof its I/O pins. Or if the 1,800-gate

State­Machine

X-Side

CWHalf-ST

ccw7·Bit

Compare

Open-DrainX-Clock Interrupt

Done-X

Half-Step-X

ClockGenerator

7-BitUp/DownCounter

MasterClock

X-SideDataLatch

x-v POSITION CONTROLLER

AddressDecoder

Latch-X-Data

Four EPLD macros are needed for each of the state­machines in the circuit, while seven Logic Cell Arraylogic blocks are required for the same function.

The schematic above Illustrates the X-axis half of the position controller used as the designexample. The other half is identical to this circuit, and drives the Y axis instead of the X.

 

Technology Update: PROGRAMIlllABLE LOGIC

Shown above Is data on several types of hlgh-denslty EPLDs. Though the MegaPAL devicesoffer the most gates, they are of bipolar, fuse-based desIgn, and so are not reprogrammable.

COMPARISON OF HIGH-DENSITY PLDS_PAL _PAL EPLD EPLD LCA LCA

Claimed Gate 1.500 5.000 1.200 1.800 1.200 1.800DensityAtcMecture AND-OR AND-OR AND-QR AND-OR Array ArrayDeveloped By MMI MMI AIIera AIIera Xilinx XilinxInputs (max.) 32 64 36 64 58 74Outputs (max.) 16 32 24 48 58 74Storage Elements 16 32 28 48 64 100Elements 0 0 12 0 58 74Speed For16-lnge AND 40 50 50 50 45 45~. through-

• fastest)Register-To-Register Clock 16 16 20 23.2 58.8 58.8Frequency (Max. MHz)Quiescent 1.4 3.25 0.G15 0.001 0.025 0.025Power (W)Packages 40 DIP 84 PLCC 40 DIP 68 CJCC 48 DIP 68 PLCC

44 PLCC 88 PGA 44 CJCC 68 PLCC 68 PLCC 84 PLCC44 PLCC 68 PGA 68 PGA

Process Bipolar Bipolar CMOS CMOS CMOS CMOSTechnology Fuse Fuse EPROM EPROM SRAM SRAM

Logic Cell Array were used, the X-Ycontroller would occupy just 49 per­cent of the logic blocks and 36 percentof its 110. The remaining logic and 110blocks can be used to build chip selectlogic to make a clean interface to themicroprocessor.

The architectural differences be­tween the two technologies allow a de­sign which requires an entire 1 ,BOO­gate EPLD to fit in just a portion of a1,200-gate Logic Cell Array. The EPLDcan perform anyone of the requiredtasks quite well. The sum-of-productsarchitecture allows EPLDs to imple­ment fast counters, decoders, and mul­tiplexers in a single pass. Combiningthese elements into a larger, more com­plex system with additional passesthrough the array however, hurts bothperformance and density.

The flexible Logic Cell Array ar­chitecture allows entire complex sys­tems to be implemented efficientlyand quickly. Given the same I,BOOgates of logic, an I,BOO-gate LogicCell Array could implement an X-Y­Z position controller in the same den­sity used to implement an X-Y con­troller in an EPLD.

ConclusionThe benefits of programmable log­

ic devices within any design are gen­erally undeniable. Both devicesshown in the design example (theEPIBOO EPLD, and the XC2064 Log­ic Cell Array) replace many SSIIMSIcomponents.

However, not all PLDs are createdequal. A designer should contem­plate his system needs and goalswhen deciding which PLD to use.Like making the correct choice of asystem processor, the correct PLDchoice will have an impact on thefinal system performance.

Some guidelines and cautionarynotes are necessary for designersnew to the PLD approach. These are:

• Be wary of PLD gates counts. Asmentioned before, not all PLDs arecreated equal. Equivalent gatecounting is used by many manufac­turers to compare their devicesagainst a competitor's. Two devices

with approximately equal gatecounts will differ on functional den­sity within a system because of dif­ferences in architecture. A betterway to determine density is to countthe types and amounts of various re­sources on the chip, and comparethose with the needs of your appli­cation.

• Understand which PLD architec­ture best suits your application. Thesum-of-products (AND-OR) architec­ture is well suited to applications thatrequire ANDing of a large number ofinputs, like those found in address de­coders and some counters. The inter­connect structure of an AND-OR PLDmakes single-pass logic functionsquick and efficient. However, the com­plex random logic requirements ofhigher-density logic designs stretchesthe limits of conventional AND-ORdevices because of the feedback re-

quirements.• Determine your 110 and register

requirements. In most AND-ORPLDs, outputs are hard-connectors tothe registers within the device. There­fore, each register either uses orwastes an 110 pin and vice versa. Inthe Logic Cell Array, 110 arid registersare separated by programmable inter­connects. Therefore, entire registerresources like counters and shift reg­isters can be buried without using orwasting 110 pins.

Major enhancements in high-densityPLDs will stem from architectural in­novations rather than process-relateddevelopments. Regardless ofwhich pro­duction process is used, all PLD manu­facturers are searching for the optimalmix of high performance, high density,and production cost to best meet de­signer's logic needs. •