the abstract simulator
DESCRIPTION
The Abstract simulator. Simulator/Simulation Concepts. Simulator: responsible for executing a model’s dynamics (resented as instructions) in a given formalism. Abstract simulator: a characterization of what needs to be done in executing a model’s instructions atomic simulator - PowerPoint PPT PresentationTRANSCRIPT
The Abstract simulator
Simulator/Simulation Concepts
Simulator: responsible for executing a model’s dynamics (resented as instructions) in a given formalism.
Abstract simulator: a characterization of what needs to be done in executing a model’s instructions
– atomic simulator– coupled simulator
Simulation engines: enforce particular realizations of abstract simulator
Simulations can be executed as: – Sequential– Parallel– Distributed (sequential/parallel)– Real-Time
– Simulation performance : event list management• event list: insert, delete, location
• search time: not constant (solution : priority queue implementation heap)
Time Event routine
t1 E1
: :
< Event list >
Transition: event generationuntil event list empty
Standard DES mechanisms
(i) Concept : separation of control (scheduling) algorithm from data(model)
ABC
AB C
A B
User’s specC:ABC
C:AB S:C
S:A S:B
System’s simulation algorithm
request
Ack
Passive agent (data)server
Active agent (control)client
S : C : simulator for model C (simulation algorithm)C: AB : Coordinator for model AB (simulation algorithm)
(ii) Hierarchical scheduling No global event list
Abstract simulation : Hierarchical simulation (scheduling) algorithm
(iii) Two classes of simulations simulator class Associated with atomic DEVS (int, ext, ta, ) invoke
coordinator class Associated with coupled DEVS Event routing Hierarchical scheduling
GEN BUFFER PROCout outin in out out
done
< GEN-BUF-PROC model >
<BUF-PROC model>
Processors: two types of simulation entities
Simulation entities example
P
EF
Salida Entrada
SalidaEntrada
Result
Salida
EF-P
TRANSD
GENR
Resuelto
Llegado
Salida Parar
Salida
Message passing
*
* done doney
y
Coordinator
S imu lator S imu lator
done
O utputFunction()InternalFunction()
x
ExternalFunction()
x
x done
Coordinator
S imu lator S imu lator
done
ExternalFunction()
External Events
Internal Events
C: GENBUFPROCGENBUFPROC
C: BUFPROCBUFPROC
S : GENGEN
S : PROCPROC
S : BUFBUF
(x, t) : external input event arrival at time t (*, t) : internally-generated event at time t that notifies the scheduled time is completely elapsed (done, tN) : synchronization event generated at time tN that notifies the next scheduled time is tN
(x, t)(*, t)
(done, tN) (done, tN)
(done, tN) (done, tN)
(x, t)(*, t)
(x, t)(*, t)
(x, t)(*, t)
Types of messages involved and their interaction
Simulator for AM
(x, t)
(*, t)(done, tN)
When receive (x,t), invokeext and ta settingWhen receive (*,t), invokeint , and ta setting
Wait
M:ext M: M:int
ta
(x, t) (*, t)
(done, tN)
Coordinatorfor CM
(x, t)(*, t) (done, tN)
(done, tN)
Wait
Route (x,t)wait till done
Route(*,t)imminent(i*)component
schedule
(x, t) (*, t)
(done, tN)
Wait i* done and(x,t) from i* done
Minimum tN
SELECTneeded
Simulator and Coordinator activities
Coordinator
(x, t)
(*, t)(done, tN)
tNtL
Wait
Route (x,t)wait till done
Route(*,t)imminent(i*)component
schedule
(x, t)
(*, t)
(done, tN)
Wait i* done and(x,t) from i* done
When receive (x,t)if tL t tN then send (x,t) to connected component(s) wait all component(s) done tL := t tN := min{tNi | i: component} send (done, tN ) to upper level coordinatorelse error
When receive (*,t)if t = tN then find component(s) with tN select one i* send (*,t) to i* wait response: (yi, port) translate yi* to x send x to its influencees wait i* and its influencees done tL := t tN := min{tNi | i: i* + its influencees } send (done, tN ) to upper level coordinatorelse error
Coordinator activities
GEN BUF PROC
outoutout
inin
done
1 2 3 4 5 6 7 8
GEN
ta(BUF) : 2 1 3 2 1ta(PROC) : 1 2 1 3 2
Root
C : G+B+P
C : B+P
S : B S : P
S : G
BUF+PROC
GEN+BUF+PROC
G B P
BG
B P
G P
SELECT
Coordinator: example
S : GEN S : BUF S : PROC C : B+P C : G+B+P ROOT t
(done, tN=1) 01 2 3
3 2 1(*, 1)(s)int(s) (6) ext(s) (5) Route: (4) Route:ta = 1 ta = 2 S:BUF C:B+P
schedule tN=2 tN=3
t = 1
(done, 2) 1 2 3
(*, 2) 3 2 1(s)int(s) ext(s)ta = 2 ta = 1
t = 2
schedule tN=4 tN=3
(done, 3) 1 2 3
3 2 1(S)int(s) ext(s)ta = 1 ta =1
schedule tN=4 tN=4
(done, 4) 1 2 3
tN=4
t = 3(*, 3)
t = 43 2 1(s)int(s) ext(s)ta = 2 ta = 2
(*, 4)
schedule tN=4 tN=4
(done, 4) 1 2 3
tN=6
Coordinator: example (contd.)
tN=3
tN=3
1. Modeler has no responsibility in time control No worry about execution sequence (No explicit initial state)
2. Separation of characteristic functions in modeling simplicity, reusability
3. Close under coupling operation
BUF
FIFO(First-in, First-out)
LIFO(Last-in, First-out)
insert
deleteinsertdelete
FIFO LIFO
Example of 2 : Buffer
ext :X Q Sint : S S : S Yta : S R+
0,
reusable
Note on abstract simulator
Mensaje I / 00:00:00:000 / Root(00) para top(01)Mensaje I / 00:00:00:000 / top(01) para gen(02)Mensaje D / 00:00:00:000 / gen(02) / 00:00:00:000 para top(01)Mensaje D / 00:00:00:000 / top(01) / 00:00:00:000 para Root(00)Mensaje * / 00:00:00:000 / Root(00) para top(01)Mensaje * / 00:00:00:000 / top(01) para gen(02)Mensaje Y / 00:00:00:000 / gen(02) / out / 0.000 para top(01)Mensaje D / 00:00:00:000 / gen(02) / 00:00:03:324 para top(01)Mensaje Y / 00:00:00:000 / top(01) / out / 0.000 para Root(00)Mensaje D / 00:00:00:000 / top(01) / 00:00:03:324 para Root(00)Mensaje * / 00:00:03:324 / Root(00) para top(01)Mensaje * / 00:00:03:324 / top(01) para gen(02)Mensaje Y / 00:00:03:324 / gen(02) / out / 1.000 para top(01)Mensaje D / 00:00:03:324 / gen(02) / 00:00:02:308 para top(01)Mensaje Y / 00:00:03:324 / top(01) / out / 1.000 para Root(00)Mensaje D / 00:00:03:324 / top(01) / 00:00:02:308 para Root(00)Mensaje * / 00:00:05:632 / Root(00) para top(01)
Generator
CD++ - Simulation