texas a&m university department of electrical and computer

Texas A&M University

Department of Electrical and Computer Engineering

ELEN 622 Active Network Synthesis, Fall 2016:

Homework #5Due on October 24, 2016

Dr. Edgar Sanchez Sinencio

Akshaya Rangarajan, Adriana C. Sanabria Borbon

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Akshaya Rangarajan, Adriana C. Sanabria Borbon ELEN 622: Homework #5

Problem 1

Based on the S-1R and S-2R architectures for Switched-R based filters do as follows:

a) For a set value of capacitance, derive the constraint that makes the time constants of the S1R and S2R

topologies equal at the center of the frequency tuning range.

b) Design a second order low-pass filter based on both topologies with Q=2, DC gain of 1 and ω0 = 10MHz

at the center of the frequency tuning range. Use the same capacitance values in both filters, and for the

S2R architecture choose an X ratio that yields a tuning range of 66square wave CLK signal at 200MHz.

Report the AC response of the filters at duty cycle 0.25, 0.5 and 0.75. Hint: Since this is a switched

system you won’t be able to use the standard AC analysis; you will have to find another way to estimate

it.

c) Simulate the THD (1MHz input signal with 1V amplitude) of both filters at the center frequency. For

the S2R vary the X ratio from 2 to 10 and compare the results.

P.S. If you face trouble computing the THD on Simulink you can export the transient results and do it on

MATLAB.

Solution

a) Let us consider the S2R first order filter of Fig. 1. Define x = R1−2R/R1−2R and the duty cycle D.

Figure 1: S2R first order filter

The time constant of the S1R filter is:

τ =R1−1RC

D(1)

and the time constant of the equivalent S2R is:

τ =xR1−2RC

1 + (x− 1)D(2)

Making the time constants of S1R and S2R first order filters equal and consider the same capacitance,

we can derive the following relations:

R1−2R =

(x+ 1

1

)R1−1R, R2−2R = (x+ 1)R1−1R (3)

Problem 1 continued on next page. . . 2


Figure 2: Active-RC low pass second order filter

b) The transfer function of the Active-RC low pass second order filter (Fig. 2) equivalent circuit is:

H(s)1

R1R3C1C2

s2 + s 1R4C2

+ 1R2R3C1C2

(4)

then, to implement the S-1R biquad each resistor is replaced by its equivalent:

Rieq =Ri

D(5)

Assuming the same duty cycle for all resistors D, the transfer function becomes:

H(s)D2

R1R3C1C2

s2 + s DR4C2

+ D2

R2R3C1C2

(6)

Therefore,

Ho(s) =R2

R1ωo =

√D2

R2R3C1C2Q = R4

√C2

C1R2R3(7)

In order to met the specs ωo = 2∗π ∗10∗106 and Q = 2 and assuming C1 = C2 = 1pF and R2 = R3 = R,

then

R =D

C1ωo= 7.95kΩ, R4 = 2 ∗R2 = 15.91kΩ, R1 = R2 = 7.95kΩ (8)

The macromodel of the S1R low pass second order filter is shown in Fig. 3.

Figure 3: Model of the 2nd order S-1R low pass filter in Simulink



Figure 4: Frequency response S1R

The frequency response was plotted using the tool Frequency response estimation of Simulink. The

response of the S1R filter varying D=0.25, 0.5 and 0.75 is:

The measured Q is approx 6dB =2 in magnitude and the cutoff frequency is changing as shown in Tab.

2.

Duty Cycle D Cut-off Frequency[MHz]

0.25 5

0.5 10

0.75 15

Table 1: fo measurements for different D

This result in consistent with the tuning rang expression:

∆f1R(%) =Dmax/min − 0.5

0.5× 100% (9)

The tuning range of the S2R filter is given by:

∆f2R(%) = 2(x− 1)(Dmax/min − 0.5)

1 + (x− 1)0.5× 100% (10)

Then in order to have a 66% tuning range x = 4.88.

The design procedure for the S2R filter is based in the relations extracted in the literal a) and the

component values of the S1R filter,



R1−2R = ((x+ 1)/x) ∗R1−1R = 9.58kΩ (11)

R2−2R = (x+ 1) ∗R1−1R = 46.79kΩ (12)

R3−2R = ((x+ 1)/x) ∗R3−1R = 9.58kΩ (13)

R4−2R = (x+ 1) ∗R4−1R = 93.58kΩ (14)

And the constant factors are k1 = 1, k2 = 1, k3 = 2, k4 = 2. This factor in the second integrator is

setting the Q.

Fig 5 shows the macromodel of the S2R switched-R second order filter using Simulink.

Figure 5: Model of the 2nd order S-2R low pass filter in simulink

The frequency response estimation is shown in the Fig. 6. And the measured cutoff frequencies are,as

predicted by the equations:

Duty Cycle D Cut-off Frequency[MHz]

0.25 6.667

0.5 10

0.75 13.33

Table 2: fo measurements for different D

We can evidence that the tuning range of the S2R is more narrow than the tuning range of the S1R.



Figure 6: Frequency response S2R

c) Fig. 7 and 8 respectively, show the output spectrum for the S1R and S2R filters designed.

Figure 7: Output Spectrum S1R

Then, Fig. 9 shows the comparison of the output spectrum changing x. In this plot we can see the

spectrum mainly dominated by the fundamental tone at the input frequency and high tones at the

frequency of the clock and its harmonics. We can observe how, as smaller x better is the attenuation of

the clock harmonics. In conclusion we proved that the smaller value of x leads to a better attenuation of

the higher order harmonics but at expenses of a more narrow tuning range.

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Problem 2

Use Simulink, Verilog-A, or any modeling language to build a macromodel for a 4-phase ring-oscillator based

second order filter with ω0 = 20 MHz and Q=0.7 based on the architecture presented in [1].

i) Provide a plot for the simulated transfer function over the frequency range fin=1-50MHz.

ii) Show how the filter output changes in time and frequency domains as you change the number of phases

M=1, 2 and 4.

References:

[1] B. Drost, et al., ”Analog Filter Design Using Ring Oscillator Integrators, IEEE JSSC, Dec. 2012, pp.3120-

3129.

[2] Zhu, Junheng. ”Ring Oscillator Integrator Based Analog Filter: System Level Design and Modeling

Using Verilog-AMS.” (2014).

SolutionThe 4-phase ring oscillator ring oscillator based VCO can be implemented using a biquad structure as shown

in the following block diagram:

Figure 10: Block diagram of the second order VCO based filter

Here CCOi is a current controlled ring oscillator. For a 4 phase implementation, a 4 phase ring oscillator

can be used. Each (phase shifted) output is fed into a phase detector and compared with a reference pulse.

Each output is integrated by one charge pump, and the outputs of all charge pumps are added and fed back

to the input. This is depicted below for a first order low pass filter.


The transfer function of the ring oscillator based filter is as follows:

H(s) =

(1

Kcpf

)1

s2

KCCO1KCCO2KPD1KPD2KCP1KCP2+ KCP2s

KCCOKPD1KCP1KCPF+ 1

(15)

we require ω = 2 ∗ π ∗ 20Mrad/s and Q = 0.7.



Substituting the above values in the transfer function:

ωo =√KCCO1KCCO2KPD1KPD2KCP1KCP2 (16)

BW =KCP2

KCCO1KPD1KCP1KCPF(17)

Using the above equations, we obtain the values of the gain factors. Assuming Kcco1 = Kcco2 and Kpd1 =

Kpd2,Kcp1 = Kcpf

We obtain, Kvco = 281MHz/V (Kvco is the sensitivity after the current is converted to voltage by the

resistor), KCP = 0.7 and KPD = 2/π.

Single phase

First, a simple block diagram was implemented using Simulink as shown below:


Figure 13: Transient response of the VCO based filter model at ω = ωo

We can observe in 15 that fo = 20MHz and Q = 0.7, also it has some DC gain factor as shown in the

transfer function that leads to a 3dB gain.



Figure 14: Transient response of the VCO based filter model at ω << ωo

Figure 15: Frequency response of the VCO based filter model

Two Phases

In order to determine how Kcco, Kcp and Kpd change with multi-phase operation, a simple Simulink block

diagram was constructed for 2-phase and 4-phase as shown below:

The transient response is shown for DC and at ωo in Fig. 17 and 18.

The bode plot is shown in Fig. 19. The results looks consistent with the single phase.



Figure 16: Block diagram of the two phases VCO based filter


Four phases

Now the block diagram of the four phases implementation is shown in 20. It was implemented as only one

VCO with the multiphase implemented as delays and 4 different PD and CP gain blocks.

The transient response is shown for two cases low frequency and cutoff frequency in order to verify the

amplitude and then confirm if the filter has the adequate performance.

It can be seen from all the above plots that Q and meet the required specifications.



Figure 20: Block diagram of the four phases VCO based filter




In order to have a more realistic model of the VCO based filter, we implemented each block in Simulink

as follows: The VCO is already included in the Simulink toolbox, Fig. 24 shows the simulation for a ramp

input.

Figure 24: VCO simulation

The phase detector was implemented as shown in Fig 25, that corresponds to a PFD. Finally the charge

pump was simulated as Fig. 26 setting the value of the currents as a constant, ans switches are controling

the polarity of the constants been added.

Figure 25: Phase detector implementation

Figure 26: Charge pump implementation



using this blocks in closed loop, we did the implementation in Simulink of the one, two and four phases VCO

based second order filters, as shown in Fig. 27, 29 and 31, respectively.

Figure 27: Single phase VCO based filter implementation

Figure 28: Transient response of the single phase VCO based filter implementation

The transient response is shown for the three cases in Fig. 28, 30 and 32. We can observe some error in the

amplitude, it means the filter is not setted at the proper cutoff frequency. It can be caused by errors in the

implementation of the sublocks or the addition of the output phases. Therefore, we were unable to tune the

filter parameters in the implementation involving VCO, Phase detector and charge pump Simulink models.

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Figure 29: Two phases VCO based filter implementation


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Figure 31: Four phases VCO based filter implementation


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Problem 3

Design a two integrator loop filter using switched-capacitor implementation. Make fo = 1Mhz and Q = 2,

H(0) = 1, discuss the tradeoffs for the clock frequency.

i) Use Simulink for the system level simulation. Show results.

ii) Using switched capacitor but ideal Op Amps in Cadence. Compare both results in ii and i.

iii) What would be the GB value of the most critical Op Amp for f0/fs = 1/8.

Reference.

1. Simulating Switched-Capacitor Filters with SpectreRF - The Designer’s ... www.designers-guide.org/analysis/sc-

filters.pdf

2. A SIMULINK-BASED APPROACH FOR FAST AND PRECISE SIMULATION OF SWITCHED-

CAPACITOR, SWITCHED-CURRENT AND CONTINUOUS-TIME EA MODULATORS Javier Moreno-

Reina, Jost2 M. de la Rosa, Fernando Medeiro, Rafael Romay, Rocio del Rio, Bel& PkrezVerdu and Angel

Rodriguez- Vazquez

SolutionThe required transfer function in s domain is as follows:

H(s) =ω2

s2 +(

ωQ

)s+ ω2

(18)

The design specifications are: ω = 2π1Mrad/s and Q = 2.

Trade-offs for clock frequency:

Pros of a higher clock frequency:

i) A higher clock frequency (a higher sampling rate) allows us to use an easier mathematical transformation

which is easier to visualize and implement as shown by equations 1 and 2. A higher clock frequency

gives a transfer function of a discrete integrator.

ii) It also leads to smaller capacitor values which leads to a reduction in area.

iii) A higher sampling rate has less quantization noise/error

Cons of a higher clock frequency:

1. On the other hand, a higher clock frequency demands a higher GBW for the OPAMP

2. This in turn increases the power consumption as higher GBW corresponds to higher power

3. More power is consumed in the clock, as a higher clock frequency consumes more dynamic power due

to higher switching rate.

4. Higher clock frequencies are problematic in real implementation of switches.

Applying bilinear transformation to the above transfer function, we obtain the transfer function in Z domain.

The transformation is shown below. Here T is the sampling time.

s =2

T

1 − z−1

1 + z−1(19)

For high sampling rates, the above equation can be modified to:

s =1

T

1 − z−1

z−1(20)



Applying the transformation, we obtain:

H (z) =ω2

( 1T

1−z−1

z−1 )2

+(

ωQ

)1T

1−z−1

z−1 + ω2(21)

Multiplying throughout by z−2:

H (z) =ω2z−2

( 1T 1 − z−1)2 +

(ωQ

)z−1

T (1 − z−1) + ω2z−2(22)

The following topology was chosen to implement the above transfer function:

Figure 33: Block diagram of the SC filter

Writing the transfer function of the block diagram:

H (z) =K1 ∗K5 ∗ z−2

(1 − z−1)2

+K6z−1 (1 − z−1) +K5 ∗K4z−2(23)

We can easily observe the similarity between Eqns. 22 and 23. Equating the equations, we determine the

values of K1, K4, K5 and K6 as follows:

K5 = ω2T 2 K6 =ωT

QK1 = 1 K4 = 1 (24)

Here the Ks are the capacitor ratios in the switched capacitor implementation. The implementation was

done with two sampling rates; Ts = 125ns and Ts = 20ns.

1. Case 1:

Ts = 125ns, K5 = 0.6169, K6 = 0.3927

Thus, Q and ω requirements are met as shown in the bode plot.

2. Case 2:

K5 = 0.0158, K6 = 0.0628

Cadence Implementation: The following topology was used to implement in Cadence:

The component values are: C1 = 10pF, C2 = 10pF and K5 and K6 are as mentioned previously.

The simulations in cadence use non overlaping clocks to have well defined the state of the switches, however

it comes with some glitches. The results of the transient simulation in cadence are shown in Fig. 39 and 40.

In comparison the transient response simulated in Simulink and Cadence looks similar, both met the specs

of frequency and Q but in the cadence one we can observe the glitches cause by the clock signals.



Figure 34: Frequency response of the SC filter

Figure 35: Transient response of the SC filter



Figure 36: Frequency response of the SC filter




In order to find the GBW of the most critical OPAMP, first we calculate the GBW of both OPAMPS:

Lets define:

GB > 10/(aTs) (25)

a =CftotCintot

(26)

For OPAMP1(lossless integrator):

phase φ1 φ2Cftot[pF] 10 10

Cintot[pF] 10+10+10 10

a 1/3 1

GB 30*Fs 10*Fs

GB[MHz] >240 >80

For OPAMP2(lossy integrator):

phase φ1 φ2Cftot[pF] 10+3.927 10

Cintot[pF] 10+3.927+6.619 10

a >0.677 1

GB 15*Fs 10*Fs

GB[MHz] >120 >80

After comparing the requirements for the two OPAMPs at both operation phases then the OPAMP with

the most critical GBW requirement is the one implementing the lossless integrator and its GB must higher

than 240 MHz.

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