temperature-aware and low-power design and synthesis of...
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Temperature-Aware and Low-Power Design and Synthesis ofIntegrated Circuits and Systems
Robert P Dick
httprobertdickorgtalpL477 Tech
847ndash467ndash2298Department of Electrical Engineering and Computer Science
Northwestern University
35 40 45 50 55 60 65 70 75 80 85 90
-8 -6 -4 -2 0 2 4 6 8
-8
-6
-4
-2
0
2
4
6
8
35 40 45 50 55 60 65 70 75 80 85 90
Temperature (degC)
Position (mm)
Temperature (degC)
Source(S)
Optionalsecond
gate (G2) Drain(D)
(G)Gate
Insulator
Island
Junctions
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
2 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Definitions
Temperature Average kinetic energy of particle
Heat Transfer of this energy
Heat always flows from regions of higher temperature to regionsof lower temperature
Particles move
What happens to a moving particle in a lattice
3 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Acoustic phonons
Lattice structure
Transverse and longitudinal waves
Electronndashphonon interactions
Effect of carrier energy increasing beyond optic phonon energy
4 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Optic phonons
Minimum frequency regardless of wavelength
Only occur in lattices with more than one atom per unit cell
Optic phonons out of phase from primitive cell to primitive cell
Positive and negative ions swing against each other
Low group velocity
Interact with electrons
Importance in nanoscale structure modeling
5 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Nanostructure heat transfer
Boundary scattering and superlattices
Quantum effects when phonon spectra of materials do not match
Splitting
6 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do wires get hot
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves
What happens to the energy of these electrons
What happens when wires start very very cool
What is electrical resistance
What is thermal resistance
7 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
2 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Definitions
Temperature Average kinetic energy of particle
Heat Transfer of this energy
Heat always flows from regions of higher temperature to regionsof lower temperature
Particles move
What happens to a moving particle in a lattice
3 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Acoustic phonons
Lattice structure
Transverse and longitudinal waves
Electronndashphonon interactions
Effect of carrier energy increasing beyond optic phonon energy
4 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Optic phonons
Minimum frequency regardless of wavelength
Only occur in lattices with more than one atom per unit cell
Optic phonons out of phase from primitive cell to primitive cell
Positive and negative ions swing against each other
Low group velocity
Interact with electrons
Importance in nanoscale structure modeling
5 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Nanostructure heat transfer
Boundary scattering and superlattices
Quantum effects when phonon spectra of materials do not match
Splitting
6 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do wires get hot
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves
What happens to the energy of these electrons
What happens when wires start very very cool
What is electrical resistance
What is thermal resistance
7 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Definitions
Temperature Average kinetic energy of particle
Heat Transfer of this energy
Heat always flows from regions of higher temperature to regionsof lower temperature
Particles move
What happens to a moving particle in a lattice
3 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Acoustic phonons
Lattice structure
Transverse and longitudinal waves
Electronndashphonon interactions
Effect of carrier energy increasing beyond optic phonon energy
4 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Optic phonons
Minimum frequency regardless of wavelength
Only occur in lattices with more than one atom per unit cell
Optic phonons out of phase from primitive cell to primitive cell
Positive and negative ions swing against each other
Low group velocity
Interact with electrons
Importance in nanoscale structure modeling
5 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Nanostructure heat transfer
Boundary scattering and superlattices
Quantum effects when phonon spectra of materials do not match
Splitting
6 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do wires get hot
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves
What happens to the energy of these electrons
What happens when wires start very very cool
What is electrical resistance
What is thermal resistance
7 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Acoustic phonons
Lattice structure
Transverse and longitudinal waves
Electronndashphonon interactions
Effect of carrier energy increasing beyond optic phonon energy
4 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Optic phonons
Minimum frequency regardless of wavelength
Only occur in lattices with more than one atom per unit cell
Optic phonons out of phase from primitive cell to primitive cell
Positive and negative ions swing against each other
Low group velocity
Interact with electrons
Importance in nanoscale structure modeling
5 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Nanostructure heat transfer
Boundary scattering and superlattices
Quantum effects when phonon spectra of materials do not match
Splitting
6 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do wires get hot
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves
What happens to the energy of these electrons
What happens when wires start very very cool
What is electrical resistance
What is thermal resistance
7 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Optic phonons
Minimum frequency regardless of wavelength
Only occur in lattices with more than one atom per unit cell
Optic phonons out of phase from primitive cell to primitive cell
Positive and negative ions swing against each other
Low group velocity
Interact with electrons
Importance in nanoscale structure modeling
5 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Nanostructure heat transfer
Boundary scattering and superlattices
Quantum effects when phonon spectra of materials do not match
Splitting
6 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do wires get hot
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves
What happens to the energy of these electrons
What happens when wires start very very cool
What is electrical resistance
What is thermal resistance
7 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Nanostructure heat transfer
Boundary scattering and superlattices
Quantum effects when phonon spectra of materials do not match
Splitting
6 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do wires get hot
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves
What happens to the energy of these electrons
What happens when wires start very very cool
What is electrical resistance
What is thermal resistance
7 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Why do wires get hot
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves
What happens to the energy of these electrons
What happens when wires start very very cool
What is electrical resistance
What is thermal resistance
7 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Why do transistors get hot
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from
Where do the electrons come from
Intrinsic carriersDopants
What happens as the semiconductor heats up
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
8 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Outline
1 What is temperature
2 Power consumption modeling
9 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels eg RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 ndash very important
10 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C middot VDD2 middot f middot A
dagger PSHORT =b
12(VDD minus 2 middot VT )3 middot f middot A middot t
PLEAK = VDD middot (ISUB + IGATE + IJUNCTION + IGIDL)
C total switched capacitance VDD high voltage
f switching frequency A switching activity
b MOS transistor gain VT threshold voltage
t risefall time of inputs
dagger PSHORT usually le 10 of PSWITCH
Smaller as VDD rarr VT
11 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Adiabatic charging
Voltage step function implies E = CVCAP22
Instead vary voltage to hold current constantE = CVCAP
2 middot RCt
Lower energy if T gt 2RC
Impractical when leakage significant
12 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Wiring power consumption
In the past transistor power wiring power
Process scaling rArr ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
13 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Leakage
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
14 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(1minus e
minusVDSvT
)e
(VGSminusVth)
nvT
where As is a technology-dependent constant
Vth is the threshold voltage
L and W are the device effective channel length and width
VGS is the gate-to-source voltage
n is the subthreshold swing coefficient for the transistor
VDS is the drain-to-source voltage and
vT is the thermal voltage
A Chandrakasan WJ Bowhill and F Fox Design of High-Performance
Microprocessor Circuits IEEE Press 2001
15 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Simplified subthreshold leakage current
VDS vT and vT = kTq q is the charge of an electron Therefore
equation can be simplified to
Isubthreshold = AsW
L
(kT
q
)2
eq(VGSminusVth)
nkT (1)
16 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Exponential
20 40 60 80 100 12005
1
15
2
25
3
35
4
45
5
55
Temperature (Co)
Nor
mal
ized
leak
age
valu
e
C7552 HSPICEC7552 Linear ModelC7552 PWL3SRAM HSPICESRAM Linear ModelSRAM PWL3
17 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Piece-wise linear error
PWL1 PWL2 PWL3 PWL4 PWL5 PWL10 PWL150
1
2
3
4
5
6
Pieceminuswise linear leakage model name
Leak
age
mod
el e
rror
(
)
C7552 Worst
2Mx32 SRAM Worst
C7552 Avg
2Mx32 SRAM Avg
18 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Gate leakage
Caused by tunneling between gate and other terminals
Igate = WLAJ
(Toxr
Tox
)nt VgVaux
T 2ox
eminusBTox (aminusb|Vox |)(1+c|Vox |)
where AJ B a b and c are technology-dependent constants
nt is a fitting parameter with a default value of one
Vox is the voltage across gate dielectric
Tox is gate dielectric thickness
Toxr is the reference oxide thickness
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states and
Vg is the gate voltage
K M Cao W C Lee W Liu X Jin P Su S K H Fung J X An B Yu and
C Hu BSIM4 gate leakage model including source-drain partition In IEDM
Technology Dig pages 815ndash818 December 2000
19 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Temperature-aware leakage estimation
power estimation at reference temperature(using PrimerPower HSPICE etc)
leakage power dynamic power
chip-package thermal analysis
leakage power analysis
until leakage power
amp temperatureprofiles converge
detailed IC power profile
detailed IC thermal profile
20 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Design level power savings
System level
Behavior level
Registerminustransfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10minus20X
2minus5X
20 minus 50
seconds minus minutes
minutes minus hours
hours minus daysIn
crea
sing
pow
er s
avin
gs
Dec
reas
ing
desi
gn it
erat
ion
times
From Anand Raghunathan
21 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method V 2 dependence
As VDD reduced VT must also be reduced
Sub-threshold leakage becomes significant
What happens if PLEAK gt PSWITCH
Options to reduce leakage (both expensive)
Liquid nitrogen ndash diode leakageSilicon-on-insulator (SOI) ndash ISUB
22 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-
What is temperaturePower consumption modeling
Reading assignment
G Chen R Yang and X Chen Nanoscale heat transfer andthermal-electric energy conversion J Phys IV France125499ndash504 2005
An article relevant to your chosen mini-project topic
23 Robert P Dick Temperature-Aware and Low-Power Design and Synthesis
- What is temperature
- Power consumption modeling
-