technology scaling impact of variation on clock skew and

Technology Scaling Impact of Variation onClock Skew and Interconnect Delay

by

Vikas Mehrotraand

Duane Boning

Microsystems Technology LaboratoriesDepartment of Electrical Engineering and Computer Science

Massachusetts Institute of TechnologyCambridge, MA 02139

International Interconnect Technology ConferenceJune 5, 2001

Technology Scaling Impact of Variation on Clock Skew and Interconnect Delay

V. Mehrotra et al. MTL-MIT2

Motivation

❏ As technology scales, tighter design constraints placeincreased importance on understanding variation

❏ Conventional approaches often represent parametervariations as independent random variables

❏ Not always effective because

• Performance estimate may be too pessimistic• Interconnect variation is deterministic

❏ Need to model variation

❏ New approach: Exploit spatial information to modelsystematic component of variation

❏ Impact: More aggressive design



Systematic Variation Modeling

❏ Separate total variation (initially assumed random) into systematicand random components with variation decomposition

❏ Systematic component based on spatial location within the die

X: µ σ2, x

x

x

x xx

xx

x

x

RandomSampling:

x

x

x

x xx

xx

x

x

VariationDecomposition:

Narrower DistributionsBased on Location Within Die



Outline

❏ Motivation

❏ Sources of Variation

• Interconnect• Devices

❏ Case Studies

• Clock Skew in H-Tree• Variation Impact in Optimally Buffered Interconnect

Technology Scaling Impact: Case Studies Scaled to 50 nm

❏ Conclusions and Future Work



Interconnect Variation Sources

❏ Metal thickness• Main source: Metal chemical mechanical polishing (CMP)• Assumption: Mostly systematic

❏ Inter-layer dielectric (ILD) thickness• Main source: Dielectric (oxide) CMP• Assumptions:

(1) Mostly systematic(2) Relatively small compared to metal thickness variation for

metal damascene CMP process

❏ Metal linewidth and linespace• Main sources: Lithography and etch effects• Assumptions:

(1) Comparable systematic and random components(2) Relatively small compared to metal thickness variation for

clock lines and very wide global lines



Device and VDD Variation

❏ Consider the following major device variation sourcesthat directly impact the device and signal delay:

• Leff (poly CD) variation• Threshold voltage, Vt• Gate oxide thickness, tox

❏ Study relative impact of device and power supply (VDD)variation compared to interconnect variation

❏ Assumptions:

• Vt, tox, VDD variations are random sources• Poly CD variation has comparable systematic and random

components



Outline

❏ Motivation



❏ Case Studies






Case Study 1: Clock Skew in H-Tree

❏ 1 GHz clock tree(P. Hofstee et al., ISSCC 2000)

❏ 0.18 m technology

❏ Chip size: 17 mm x 17 mm

❏ 6 level metal with copperinterconnect technology

❏ Clock tree on top 2 metal levels

❏ Almost symmetric H-Tree

❏ Ideally low skew

❏ Consider both interconnect anddevice variation

µ

Clock Driver

Latch

Intermediate Buffers (Repeaters)Courtesy of IBM Austin Research Lab



Interconnect Scaling

❏ Clock tree scaled to 50 nm generation based on 1999SIA Roadmap scaling projections

❏ By 50 nm generation, note that:

• Interconnect pitch shrinks to one-fourth• Chip size doubles• Global clock frequency triples

Clock Tree Interconnect Parameters

Technology / Parameter 180 nm 50 nm

LW, LS 1X 0.25X

Aspect Ratio 2 2.6

Dielectric Constant 3.5 1.4

Chip Size 17 mm x 17 mm 34 mm x 34 mm

Global Clock Frequency 1 GHz 3 GHz



Device and Power Supply Variation

❏ Variation tolerances are not expected to scale withtechnology (S. Nassif, “Design for Variability in DSMTechnologies,” ISQED 2000)

Device and VDD Parameters and Worst-Case Variation Tolerances

Technology 180 nm 50 nm

Parameter NominalVariation

(%)Nominal

Variation(%)

Leff (nm) 180 20 50 40

tox (nm) 2.2 10 0.7 20

Vt (V) 0.40 10 0.25 15

VDD (V) 1.8 10 0.9 10



Modeling the Impact of Variation

❏ Simulate the impact on clock skew for 4 cases:

• Interconnect (case 1 and 2)• Devices (case 3 and 4)

❏ Interconnect:

• Case 1: No interconnect variation• Case 2: Systematic metal thickness variation using CMP models

❏ Devices and VDD:

• Case 3: Device and VDD variation assumed to be random• Case 4: Vt, tox, VDD variation assumed random

poly CD variation assumed to have systematic andrandom components

❏ Cases 2 and 4 are referred to here as the tightertolerance design method



Clock Skew for H-TreeClock Skew With Interconnect, Device, and VDD Variation

Variation Source Skew (psec) Skew (% of clock period)

None 45.53 4.55

Cu CMP(systematic model)

36.85 3.69

Devices & VDD 116.58 11.66

Devices & VDD

(tighter Leff tolerance)

96.96 9.70

Total Skew (worst-case device & VDD tolerances)

162.11 16.21

Total Skew (systematic modelfor metal thickness & tighter

Leff tolerance)

133.81 13.38

Skew Reduction(tighter tolerance)

28.30 2.83



Technology Scaling Impact on Clock Skew

Variation Source 180nm 50nm 180nm 50nm

None 45.53 22.12 4.55 6.62

Cu CMP(systematic model)

36.85 14.83 3.69 4.44

Devices & VDD 116.58 71.28 11.66 21.34

Devices & VDD

(tighter Leff tolerance)

96.96 53.40 9.70 15.59

Total Skew (worst-case device & VDD tolerances)

162.11 93.40 16.21 27.96

Total Skew (systematic modelfor metal thickness & tighter Leff

tolerance)

133.81 68.23 13.38 20.43

Skew Reduction(tighter tolerance)

28.30 25.17 2.83 7.53

Units psec % of clock period



Outline

❏ Motivation



❏ Case Studies






Case Study 2: Optimally Buffered Interconnect

❏ Insert intermediate buffers (repeaters) when routing long distances across

chip to reduce delay

❏ Total path delay:

where

Rtr = driver resistanceCL = load capacitanceR, C = lumped interconnect resistance and capacitanceN = number of interconnect sections

......1 2 N-1 N O

utpu

t

Inpu

t

Delay0.4RC( )

N---------------------- 0.7 Rtr C RCL Rtr CL+ +( )+=



Optimal Buffer Number and Size

❏ From H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, 1990

❏ Let h = optimal buffer size (represent driver as an intermediate buffer)

❏ Then Rtr = R0/h and CL = hC0

❏ Propagation Delay:

❏ Compute Nopt and hopt by setting and

❏ Optimal buffer number:

❏ Optimal buffer size:

T pd0.4RC

N------------------ 0.7

R0C

h------------- RC0h R0C0N+ +

+=

∂T pd∂N

--------------- 0=∂T pd

∂h--------------- 0=

Nopt0.4RC( )

0.7R0C0-------------------------=

hopt

R0C

RC0-------------=



Maximum Interconnect Length❏ Given a clock frequency constraint, compute maximum interconnect length,

Lmax, with optimal buffering such that delay is less than one clock cycle

50 100 150 200 2500

10

20

30

40

50

60

Technology Generation (nm)

Deg

rad

atio

n in

Lm

ax (

%)

Global Interconnect

LS=1XLS=2XLS=3X

TighterTolerances

Worst-CaseTolerances

❏ Study the effects ofmetal thickness, metallinewidth, and devicevariation

❏ Lmax degradation

increases as technologyscales to 50 nm

❏ Using worst-casevariation tolerancesresults in larger rate ofincrease in degradation



Lmax Degradation for Local Interconnect

❏ Greater variation impact on Lmax degradation for local interconnectthan for global interconnect

50 100 150 200 2500

10

20

30

40

50

60


Deg

rad

atio

n in

Lm

ax (

%)

Local Interconnect

LS=1XLS=2XLS=3X

Worst-CaseTolerances

TighterTolerances



Lmax Degradation Components (Global)

❏ Device variation accounts for most of the degradation in Lmax forglobal interconnect even as technology scales

50 100 150 200 2500

10

20

30

40

50

60


Deg

rad

atio

n in

Lm

ax (

%)

Global Interconnect

Metal ThicknessLinewidth Device Total



Lmax Degradation Components (Local)

❏ Lmax degradation affected by linewidth and metal thickness variationin addition to device variation

❏ Increased importance of interconnect as technology scales

50 100 150 200 2500

10

20

30

40

50

60


Deg

rad

atio

n in

Lm

ax (

%)

Local Interconnect

Metal ThicknessLinewidth Device Total



Conclusions

❏ Systematic variation modeling can enable moreaggressive design

• Reduction in maximum clock skew of 28 psec in 1 GHz H-treedue to tighter interconnect and device tolerances

• Tighter design tolerance in buffered interconnect of up to 10%

❏ Technology scaling increases importance of systematicvariation modeling

• Estimated clock skew reduction with tighter design toleranceaccounts for 7.5% of clock cycle in 50 nm generation comparedto 2.5% in 250 nm

• Over-estimate of Lmax degradation in the 50 nm generationincreases to over 20% compared to 7-10% in 250 nm

❏ Random device variations still need to be considered• Device and VDD variations account for approx. 75% of total skew



Future Work

❏ Extensions to methodology

• Systematic variation models for:

(1) poly CD device variation

(2) metal linewidth variation

❏ Test circuits to calibrate circuit performance simulationresults with experimental observations



Acknowledgments

The authors would like to thank:

❏ Sani Nassif, IBM

❏ IBM Austin Research Lab

❏ PDF Solutions

❏ MARCO and DARPA Research Focus Centeron Interconnect

technology scaling impact of variation on clock skew and

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