Technology Challenges and Directions of SRAM

& eDRAM Cell Scaling in Sub-20nm

Generations

Jai-hoon Sim

SK hynix, Icheon, Korea

March 6th, 2013

2

Outline

1. Nobody is perfect: Main memory & cache memory in the

dilemma in sub-20nm era.

2. SRAM Scaling: Diet or Die. 6T SRAM cell scaling crisis & RDF

problem.

3. DRAM Scaling: Divide and Rule. Unfinished 1T1C DRAM cell

scaling and its technical direction.

4. eDRAM Story: Float like a DRAM & sting like a SRAM. Does

logic based DRAM process work?

5. All for one. Reshaping DRAM with logic technology elements.

6. Conclusion.

3

Memory Hierarchy

Density

Access S

peed

Higher Speed

(< few nS)

Better Endurance

(>1x1016 cycles)

Lower Speed

Bigger Size

L1$

SRAM

Main Memory

L2$

L3$

DRAM

Storage Class Memory

PcRAM

ReRAM

eDRAM

NAND

Working

Memory

Stt-RAM

4

• 1T-1C cell.

• Destructive read and Write-back needed.

• Leakage-Performance compromised

process technology.

• Smaller than SRAM and faster than

DRAM.

• 1T-1C cell.

• Destructive read and Write-back needed.

• Leakage control driven process technology.

• Not always fast.

• Smallest cell and lowest cost per bit.

• 6T cell.

• Non-destructive read.

• Performance driven process

technology.

• Always very fast.

Technologies for Cache & Main Memories

SRAM

DRAM

eDRAM Speed

Standby

Power Density

5

eDRAM Concept: Performance Gap Filler

Random Access Speed

Ce

ll S

ize

DRAM

SRAM

20-30X

50-100X

eDRAM

• Is there any high density & high speed memory solution that could be 100%

integrated into logic SoC?

6

6T-SRAM Cell Operation

VDD

VSS

WL

BL

BL

SN

Time

WL

BL

WL

BL

PU

PD

PG SN

VDD

VSS

SN

SN

Read

Write PG

PDRead Margin:

PU

PGWrite Margin:

DVBL

Icell

7

DRAM’s Charge Sharing DVBL

CS CBL

VS VBL

BLBSDDBDDS VCCV2

1CVC

VDD

1/2VDD

VSS

WL

BL

BL

SN

Time

Cell select

Charge Sharing Write-back

VBBW

VPP

DDSBBLBLBL V

2

1

C/C1

1VVV

D

Initial Charge After Charge Sharing

D

S

RETLDD

SB

BLC

tIV

2

1

C/C1

1V if cell leakage included

BLVD

Td

8

DRAM Scalability Metrics

D

S

RETLDD

SB

BLC

tIV

2

1

C/C1

1V

+

- DVBL(OFF)

- +

CB

CS

CB

Cell

• Cell CS.

• Parasitic BL CB.

• Cell leakage current.

• BL offset voltage.

• Cell ION current.

• WL & BL resistance.

BL

BL

WL

Speed

Sensing

9

DRAM’s Bitline Offset Voltage

2LER2

GOX

2

RDF

2

WKF

2

VTH

SA_TH

B

B

SA_n

SA_n

B

B

SA_n

B)OFF(BL Vnoise

R

R

C

CKC5.0V D

D

D

D

D

BL BL

fN Slope= K

time

caused by AC effect

(RC mismatches) caused by DC effect

(VTH mismatch)

• Bitline pitch & cell architecture are critical to DVTH_SA.

• Offset voltage caused by RC effect increases as pull-down speed becomes

faster. KeDRAM ~ 10xKDRAM. [K. Itoh, VLSI memory chip design, Springer, 2001.]

Data pattern dependent

10

6T-SRAM Cell

VSS VDD

WL

BL

BLB

WL

VDD VSS

PU

PU PD

PG

PG

PD CPP

M1 Pitch

Contact

Gate

Active

Unit Cell

2x C

PP

= 5x M1 Pitch

N-Well

VSS VDD

VDD VSS

WL

WL

BL

BL

11

Contacted Poly Pitch (CPP)

n+ n+

Gate

Poly

CT CT

CPP

Design Rule F [nm]

CP

P, L

G,

(CP

P-L

G)/

2 [

nm

]

CPP

(CPP-LG)/2

LG

(CPP-LG)/2

• Gate length LG shrunk only 5nm during past 4 technology generations (65nm to 22nm).

• CPP scaling is mostly driven by Spacer & CT scaling and scaled by 30% every 2 years [ same as design rule F].

(CPP - LG)/2 = CT/2 + Spacer

12

SRAM Cell Scaling Trend

(CPP – LG)/2 [nm]

SR

AM

Cell S

ize [m

m2]

• SRAM cell size correlates well with (CPP – LG)/2 until 22nm generation.

• For SRAM cell size = 0.01Xmm2, the CT/2 + Spacer = 8.0nm (equivalent to F = 5nm).

22nm

32nm

45nm

65nm

90nm

130nm

A: no LG shrink (same as @22nm)

B: LG shrunk by 20% every generation

C: LG shrunk by 30% every generation

2GG L)L-(CPP10SizeCell LG/(C

PP

– L

G) R

atio

[nm

/nm

]

• As (CPP-LG)/2 approaches LG at

22nm generation, LG effect is no

more negligible in cell size scaling.

• LG should be shrunk by 20~30%

in 15nm generation to keep

current cell size scaling trend.

A

B

C

13

VTH Impact on SRAM Scaling

[K. Kuhn, et al, Intel Tech. J., June 2008.]

nMOS Vt p

MO

S V

t nMOS Vt

pM

OS

Vt

THVPass

[H. Yamauchi, J. STS, Mar. 2009.]

Icell Icell

LW/1

THV

180nm

130nm 90nm

65nm

45nm

32nm

14

DRAM’s Scaling Analysis (1): IL=0 Case

)C/C1(V2V SB)OFF(BLMIN_DD D

• For decreasing CS value, CB or DVBL(OFF) should be reduced in order to keep same

MAT size (# of cells per bitline kept same) under same VDD_MIN condition.

• Maximum CB/CS value could be simply determined by target VDD_MIN and DVBL(OFF) .

When cell leak current = 0, eqn. (1)

can be simplified as

CB/CS Ratio

VD

D_M

IN [

V]

SB

S

RETLDD

BLC/C1

C

tIV5.0

V

D (1)

DVBL(OFF) : bitline offset voltage including sense

amplifier device mismatch and other electrical

mismatches.

15

DRAM’s Scaling Direction

DVBL(OFF)

Scaling IL Scaling

CB

CS

Prohibited

Region

①

②

①

②

If CS should be reduced w/o cell innovation,

DVBL(OFF) & IL should be improved:

• Improve SA’s mismatches – DVTH

& D.

• Improve DCB & DRB.

• Junction engineering.

Decreasing CB as CS scales downs:

• New cell innovation, Buried WL.

• New materials for BL: Low-K

Dielectric, Air Gap, etc.

CB scaling is strongly dependent on

cell innovation but is a weak function

of direct cell size shrink.

16

Cell Capacitor Scaling (1)

30

40

4

3

5

10

20

2000 2002 2004 2006 2008 2010 2012 2014 Year

50

7

EOT [Å]

[Source : ITRS 2000~2010]

SIS or MIS, Concave or Cylinder

Al2O3

MIM, Cylinder

HfO2 & Al2O3

ZrO2 & Al2O3

High-k

Ultra high-k

MIM, Pillar

17

Cell Capacitor Scaling (2)

70nm 60nm 50nm 40nm 30nm 20nm 10nm

100

80

60

40

20

0

[DRAM Technology Node]

Aspect Ratio

A/R ▶

6

5

4

3

2

1

Cs [A.U.]

Expected Cs

Cylinder Cap.

3Å

4Å

Pillar Cap.

[S. Cha, IEDM, 2011]

18

Bitline Capacitance Scaling

Reduce BL length: 4F(8F2) 2F(6F2)

Reduce BL-WL cap: Buried WL

[T. Schloesser et al., IEDM 2008.]

8F2 6F2

BL BL

19

Bitline Capacitance Scaling (3)

Design Rule [nm]

CB/C

S R

ati

o

Nu

mb

er o

f Ce

lls/B

L

3D Capacitor

COB

6F2

+

Buried WL

4F2

6F2 8F2 > 8F2

20

eDRAM Technology Trend

“eDRAM cell = Fast as SRAM cell but small as DRAM cell”

Technologywise:

It should be logic technology based.

• Logic design rule.

• Logic cell passgate transistor.

• Silicided cell junctions.

• Logic transistors for bitline SA & periphery circuits.

• Low-K/Cu BEOL for bitline and BEOL layers.

• 3D Cell capacitor module process.

Designwise:

fast DRAM design with logic VDD range.

• Reduce bitline length (16-64 cells/BL).

• Improve low VDD margin: VDD or GND bitline sensing.

100-1000x leakage current.

Shorter retention time.

Fast cell read/write access.

Fast signal development.

6-7x bigger cell size.

but still 3-4x smaller than SRAM.

Non-self-aligned cell process.

21

DRAM vs. eDRAM

DRAM eDRAM

Process

Technology 3 metal DRAM process > 5 metal logic process

Cell Size ~ 6F2/cell ~ 30-50F2/cell

GOX 5-6nm 2.5-3.5nm

Bitline W M1 (Cu) – CUB; W – COB

Bitline length > 512 cells/BL 16-32 cells/BL

Metal Layers 1(M0) + 3 layers 5-6 layers

Cell capacitor Cylinder Cylinder

VPP 3.0V < 2.0V

VDD 1.2-1.5V 0.9-1.0V

Storage junction -- Silicided

Leakage current < 1fF/cell@95C ~ 1pA/cell@115C

Refresh time 64mS@95C < few mS

BL sensing 1/2VDD sensing VDD or GND sensing

Read Speed tRCD+tCL=23nS, tRAS+tRP=45nS 3-10nS

22

ML eDRAM Technology: CUB

[[1] Y. Yamagata, CICC, 2006. [2] K. Tu, IEDM, 2011.]

Bottom Electrode (BE)

Hi-K Dielectric

Top Electrode (TE)

BL (M1)

STI

Stacked

Contact

TE Hole Open

GC Stacked Contact

Capacitor n+ n+

[Y. Yamagata, CICC, 2006.]

Logic FEOL

eDRAM Capacitor

Process

23

Capacitor Under Bitline (CUB) & DT eDRAM

Contact

Gate

Active

BL

WLi+1 WLi WLi+2 WLi+3

BLi

BLi

BLi+1

CPP_PG CPP_ISO

• Cell height is determined by isolation pitch & GC-AA overlay. Height ~ 4F.

• Cell width is limited by CPP and poly pitch. Width ~ 8F.

• Cell PG device gate length and width limited by retention leakage and

operation speed, respectively. PG device Lg = 2F~3F, W = 2F~3F.

ISO

Pit

ch

Cell Size ~ 32F2.

24

ML eDRAM Technology: COB+Deep CT

• BL (Tungsten) dedicated metal process equipment required.

• CBL and RBL decoupled with cell capacitance: Good for eDRAM’s low voltage and

high speed operation. But cell capacitor height limited by M1 contact’s aspect

ratio. For logic part, M1C limits logic’s high speed & low voltage performance.

BL (W)

STI

Triple

Stacked

Contact

GC

n+ n+

Capacitor

BLC

M1 (Cu)

[Y. Yamagata, CICC, 2006.]

25

Capacitor Over Bitline (COB) eDRAM

Contact

Gate

Active

BL

WLi+1 WLi WLi+2 WLi+3 WLi+4

BLi

BLi

BLi+1

BLi+1

• Cell height ~ 4F, cell width ~ 10F.

• AA space, BL width and BL-SN spacing are the critical rules.

Cell Size ~ 40F2.

26

Design Rule F [nm]

Ce

ll S

ize

[m

m2]

SRAM

eDRAM

DRAM

6F2

4F2 0.0006

0.0004

SRAM, eDRAM, & DRAM Cell Scaling Trend

0.008

0.0228

27

6

4

Memory Cell Size Factor Trend

27.3

44.6

36.4 52.5

8

6 6

190.1 167.0 170.9

134.9 123.5

Design Rule F [nm]

Ce

ll S

ize

F

ac

tor

80

228

3.7x 5.0x

2.85x

28

Memory Market Positioning

Memory Size [Mb/mm2]

Sp

ee

d

DRAM

L1

Cache

29

New Memory Technology: Stt-RAM

[S. Chung, IEDM, 2010]

• MTJ (magnetic Tunneling Junction) provides good scalability (

30

L3 Cache Memory Scenario

L1/L2 cache

SRAM

L3 cache

SRAM

CPU

L1/L2 cache

SRAM

L3 cache

eDRAM

CPU L1/L2 cache

SRAM

External

L3 cache

eDRAM

CPU

+ L1/L2 cache

SRAM

External

L3 cache

DRAM/Stt-RAM

CPU

+

31

Conclusion

1. SRAM cell’s scalability metrics are determined by “genuine” performance

of cell transistors (Ion, Ioff, & VTH).

2. “Divide and rule the DRAM”: Scaling on 1T1C cell and SA VTH could be

optimized separately.

3. SRAM is too fat to fit into sub-20nm generation technology. New

architecture innovation needed or to be replaced by new technologies in

L2$/L3$ applications.

4. DRAM scaling in sub-20nm generations will be continued by innovation in

Cb/Cs scaling, Hi-K MiM, & highly matched sense amp device technology.

5. eDRAM’s macro size benefit against SRAM is narrowing down. More

matured process & design to be developed.

32

Thank you