Texas TAS3308 Instruments Digital Audio Processor With Analog Interface

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TAS3308

Data Manual

This document contains TI confidential and proprietary information

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Contents 1. TAS3308 Features ........................................................................................................................................5 2. Introduction...................................................................................................................................................6 3. Comparison between TAS3208 and TAS3308...........................................................................................7 4. Analog Inputs – 10:1 Stereo MUX and 1 Stereo ADC ...............................................................................8 5. Stereo PWMs for Headphone/Line Driver Outputs/Speakers ............................................................... 10

5.1 Pulse Width Modulation .....................................................................................................................10 6. Reference System ..................................................................................................................................... 17 7. Power Supply............................................................................................................................................. 17 8. Control pins ............................................................................................................................................... 17

8.1 Reset (/RESET) – Boot-up Sequence ...............................................................................................17 8.2 I2C Chip Select ...................................................................................................................................20 8.3 GPIO Pins ..........................................................................................................................................21 8.4 GPIO & Watchdog Timer ...................................................................................................................23 8.5 Mute Control.......................................................................................................................................25

9. Clock, PLL, and Serial Data Interface...................................................................................................... 25 9.1 Master Mode Operation .....................................................................................................................27 9.2 Slave Mode Operation .......................................................................................................................27 9.3 Serial Audio Data Formats .................................................................................................................27 9.4 Discrete I2S Timing.............................................................................................................................27 9.5 Discrete Left Justified.........................................................................................................................28 9.6 Discrete Right Justified ......................................................................................................................29 9.7 SAP Output Normalization .................................................................................................................29 9.8 Auto clock and serial data rate detection ...........................................................................................33

10. SPDIF Transmitter ..................................................................................................................................... 36 10.1 SPDIF Encoder operation ..................................................................................................................37 10.2 Transmitter control register ................................................................................................................37 10.3 I2C Register Map for SPDIF and specification coverage ...................................................................39

11. Micro Controller......................................................................................................................................... 41 11.1 General I2C operations.......................................................................................................................42 11.2 I2C Master Mode Device Initialization ................................................................................................43 11.3 Memory block format..........................................................................................................................44 11.4 I2C Slave Mode Operation .................................................................................................................50 11.5 Microcontroller I2C Controls ...............................................................................................................51 11.6 8051 Addressing Modes ....................................................................................................................52

12. Digital Audio Processor (DAP) Arithmetic Unit...................................................................................... 53 12.1 Overview ............................................................................................................................................53 12.2 DAP Interface.....................................................................................................................................56 12.3 Delay Memory ....................................................................................................................................57 12.4 DAP Instruction Word.........................................................................................................................58 12.5 DAP Instruction set ............................................................................................................................60

13. Physical Characteristics........................................................................................................................... 61 13.1 Absolute Maximum Ratings over Operating Temperature Ranges ...................................................61 13.2 Recommended Operating Conditions................................................................................................62 13.3 Audio Specifications (Channel – Input to Output)..............................................................................62 13.4 Audio Specifications (Digital Filters) ..................................................................................................62 13.5 Electrical Specifications (Analog Sections)........................................................................................63 13.6 Electrical Characteristics....................................................................................................................64 13.7 TAS3308 Timing Characteristics .......................................................................................................65 13.8 MCLK and serial input operation conditions ......................................................................................71 13.9 Terminal Assignments........................................................................................................................74 13.10 Pin Description ...................................................................................................................................77

14. I2C Register Map ........................................................................................................................................ 80 14.1 SAP / Clock Setting (0x00).................................................................................................................82 14.2 Status Register (0x02) .......................................................................................................................84

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14.3 Load Memory Control and Data Register (0x04, 0x05) .....................................................................87 14.4 PEEK and POKE (0x06, 0x07)...........................................................................................................88 14.5 Mute Control (0x09) ...........................................................................................................................90 14.6 GPIO Control (0x0C)..........................................................................................................................91 14.7 Power Down Control (0x10) ...............................................................................................................91 14.8 A-MUX Control (0x12)........................................................................................................................92 14.9 SPDIF Control (0x16).........................................................................................................................93 14.10 Fast Volume Ramp Control (0x17) ....................................................................................................95 14.11 PWM Control (0x18)...........................................................................................................................96 14.12 PWM Channel Delay, Modulation limit and Offset (0x1A) .................................................................98 14.13 PWM Duty 50 Mode Control (0x1D) ..................................................................................................99 14.14 DAP Program Start Address (0x1E) ............................................................................................... 101 14.15 I2C Master Load (0x1F)................................................................................................................... 101

15. Application Information .......................................................................................................................... 102 15.1 Application Diagram........................................................................................................................ 102 15.2 PWM low-pass filters....................................................................................................................... 103

Mechanical Information..................................................................................................................................... 105

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1. TAS3308 Features

Audio Input /Output

• Up to 3 synchronous serial audio inputs (6 Channels)

• Up to 2 synchronous serial audio outputs (4 Channels)

• Input Data Formats: 16-, 20-, or 24-bit data Left, Right and I2S

• Output Data Formats: 16-, 20-, or 24-bit data Left, Right and I2S

• 64 * Fs Bit clock rate • 24.576 MHz XTAL input for Master clock

modes and clock auto detection • Slave mode 256, 384 or 512 * Fs MCLKIN in

with automatic clock rate detection • Slave mode 32, 44.1, and 48 kHz Fs with

auto sample rate detection • Master Mode - 48 kHz Fs • 10 Mux’ed Stereo Analog inputs selectable

into one stereo ADC. ADC maximum input level: 1 Vrms SE

• 3 Stereo differential PWM output’s • High quality DNR 100 dBA (typical) ADC

Channel Performance (2-channels) with Master mode clock

• High quality DNR 105 dBA (typical) PWM Channel performance (6-Channels)

• 1 single ended Analog Stereo Line Driver Outputs with 1 of 10 selectable inputs, 10 kΩ, 100pF drive Capability (Maximum output level: 1 Vrms)

• Line-out supports a LL/RR multiplexer option

Audio Digital Signal Processor

• Programmable functionality • 135MHz operation • 48-bit datapath with 76-bit accumulator • Hardware single cycle multiplier (28 x 48) • Two memory loads and one memory store

per cycle • Usable 1K words data RAM (48-bit) and

usable 1K coefficient RAM (28-bit) • 3.25K words instruction program RAM (2.8K

words available) • 360 mS @ 48KHz, 17,408 words 24-bit

delay memory

PWM Features

• Proven PurePath technology • Fourth order chaotic noise shaper with non-

linear correction • High quality DNR 105 dBA (typical) PWM

performance • Click and pop minimizing at power up/down

using TI patented technology

General Features

• Easy to use control interface • I2C Serial Control Master & Slave Interface • Control Interface operational without

external MCLK input • Single 3.3V Power Supply • Integrated Regulators • 100 Pin TQFP Package • M8051 device controller • Auto clock and serial data rate detection and

automatic device configuration without audible artifacts

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2. Introduction

TAS3308 is an audio SOC designed for digital TV Audio Systems and Mini/Micro Component applications. It includes analog interface functions: 10 multiplexed stereo inputs with one stereo ADC and three stereo PWM outputs. TAS3308 has a programmable audio DSP that preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle 28 x 48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM. Two serial digital outputs provide I2S PCM data. One of the outputs can also provide I2S and/or S/PDIF encoded PCM DATA. The TAS3308 is composed of eight functional blocks.

• Analog input/MUX/Stereo ADC • 3 Stereo PWM output for Speaker/Headphone/stereo Line driver outputs • Reference System • Power Supply • Clock, Digital PLL, Analog PLL, Serial Data Interface and auto-detect system • Serial Control Interface/Device Control • Audio DSP - Digital Audio Processing • 8051 Device Controller

8051 Devicemicro-controller

DigitalAudio

Processor

I2C

APLLPower

ReferenceXTAL

Reset

SincDecimation

Input Serial Audio Port

1-3

PWM1-3

Output Serial Audio Port

10 STEREOANALOG

IN

SDIN1-3SDOUT1

Auto-detect

DPLLOSC

StereoADC

SPDIF

LRCLKI, SCLKI

SPDOUT/SDOUT2

LRCLKO, SCLKO,MCLKO

VALID

PWM1L (I+D),R(I+D)

SPDIN

DecimationFW

MCLK

PWMCLK,ADCCLK

DIGCLK%2

Interpolation

PWM2L (I+D),R(I+D)

PWM3L (I+D),R(I+D)

LINEOUT1(L+R)

1024WDATARAM

360MSDELAYRAM

1024WCOEFRAM

Figure 2-1, shows the functional structure of the TAS3308.

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3. Comparison between TAS3208 and TAS3308 The TAS3208 to TAS3308 overview table compares the feature set in the TAS3308 with its predecessor the TAS3208.

Features TAS3208 TAS3308 Auto clock and serial data rate detection NO YES ADC Performance (DNR) in Master mode 93 dBA (typical) 100 dBA (typical) DAC Performance (DNR) 96 dBA (typical) --------- PWM Performance (DNR) -------- 105 dBA (typical) High Performance APLL NO YES SPEAKER OUT DAC OUT PWM OUT HP OUT DAC OUT PWM OUT LINEOUT DAC OUT PWM OUT ANALOG LINE OUT 3 Stereo 1 Stereo PWM Click and pop minimizing at power up/down using TI patented technology NO YES

Available DAP CYCLES 2000 2400 INTERPOLATION FILTER DAP Software Dedicated Hardware DAP DATA RAM 768 1024 DAP COEFF RAM 1024 1024 DAP PROGRAM RAM 2.5K 2.8K DELAY RAM 17,408 words 24 bit 17,408 words 24 bit MICRO PROGRAM RAM 16K 20K GPIO PINs 4 2 Hardware Delay RAM Flush Support NO YES LL/RR lineout support NO YES

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4. Analog Inputs – 10:1 Stereo MUX and 1 Stereo ADC

The TAS3308 has 10 analog stereo inputs by 1 Vrms or less signal level to be sent to the stereo ADC to the Line output multiplexer. The input multiplexer includes a preamp function that drives the ADC. The line-ins is feed to a 10 to 1 multiplexer for selection of the stereo pairs going to the lineout. In the multiplexer it is possible to select which stereo pair is going to the line-out. Additionally, for one set of stereo pairs, the multiplexer can select line-Out1 only L/L or R/R. However, L+R monaural selection is not supported.

Figure 4-1, TAS3308 LL/RR control

L R L R L R L R L R L R L R L R L R L RLINEOUT1 L L L L L L L L L L L

LINEOUT1 R R R R R R R R R R R

LINEOUT1 L LLINEOUT1 R L

LINEOUT1 L RLONEOUT R R

LIN

EIN

8

LIN

EIN

9

LIN

EIN

10

One set of stereo pairs selection for everychannel can be performed

L/ L common selection for every channelcan be performed.

R/ R common selection for every channelcan be performed.

LIN

EIN

7

LIN

EIN

1

LIN

EIN

2

LIN

EIN

3

LIN

EIN

4

LIN

EIN

5

LIN

EIN

6

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Figure 4-2, TAS3308 Analog input/output, PWMoutput

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5. Stereo PWMs for Headphone/Line Driver Outputs/Speakers

5.1 Pulse Width Modulation The TAS3308 uses TI PurePath PWM modulators for audio signal outputs. The device utilizes noise shaping and advances non-linear correction to achieve excellent performance from 20 Hz to 20 kHz. When used with TI power stages, TI patented PWM start and stop sequences minimize audible artifacts at the outputs during power up and down. The PWM outputs can be configured to drive either a low pass filter (Comb-AD modulation) or a Pure-Path output stage BTL AD modulation when used as a digital amplifier. The PWM outputs can be configured to drive either a low pass filter (Comb-AD modulation) or a Pure-Path output stage (Single ended, BTL AD, or BTL BD modulation) when used as a digital amplifier. The TAS3308 uses a high quality analogue PLL to generate the low jitter high frequency clock used to generate the PWM pulses from. The noise shaper operates at an 8Fs for 44.1and 48 kHz and 12 Fs for 32 kHz. Section 13.4 lists the performance numbers for this filter.

5.1.1 Comb-AD Modulation A PWM signal contains a significant amount of out of band components. This is normally not a big concern when driving a speaker from a power stage. However, when driving a line-out this may become a problem, depending upon what the line-out is feed into. In particular, a lot of energy is present in the PWM carrier (384 kHz for Fs equal to 48 kHz) and in harmonic of PWM carrier. To effectively suppress this, a notch filter with the notch placed at the PWM carrier frequency is used. The notch filter used is a comb filter, with the transfer function:

2/11)( −+= zzH With the sampling frequency equal to two times the PWM sampling frequency. Figure 5.1 shows the principle of this arrangement. The delay is implemented in the TAS3308, but the addition is done externally to the device. For this reason the modulator has two PWM outputs, PWMI that is the immediate PWM signal and PWMD that is the delayed PWM signal. Section 15.2 shows the detailed implementation for the LPF used add PWMI and PWMD and suppress out of band noise.

Figure 5.1, Comb AD modulation

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When using the PWM as DAC, the outputs remain in hi-Z until enabled through I2C. When enabled, the nominal output voltage of the PWM output is the PWM supply voltage divided by two. Therefore, it is necessary to take precaution to avoid outputting a DC step to the speakers or to line out at power up. It is recommended to disable the output at the time where the PWM outputs is started, for example by using the TPA3100’s ENABLE input or by pulling the line out low with a NPN resistor. Se application diagrams in paragraph15.2 PWM low-pass filters. An alternative to this solution is to use an external resistor network to bias the low-pass filter thereby avoiding the DC step from starting the PWM outputs. However, due to resistor mismatch it is difficult to avoid a DC step all together. Consequently, Ti does not recommend this solution. When using the PWM as DAC, it is possible to reconfigure the VALID pin to output a synchronization signal to the PSU or to other switched circuits like an external analog PWM.

5.1.2 BTL AD Modulation When the PWM output is used as a digital amplifier with Pure-Path power-stages, one option is to configure the system in an AD mode bridge tied load configuration. In the AD mode, the speaker is driven differentially by the amplifier with the PWM and the inverse of the PWM signal. Figure 5.2 illustrates the principle in the AD Mode bridge tied load configuration. The inverter may be integrated in the power stage.

Figure 5.2, BTL AD modulation

The TAS3308 interfaces to a variety of PurePath power stages to provide a high performance audio power amplifier. See application diagrams in section14 I2C Register Map for configuration details. The TAS3308 use the VALID signal to sequence the power stages from hi-Z to their active state. After going from hi-Z to active state, the modulator uses a special PWM sequence to minimize clicks and pops during the start and stop operations. Figure 5.3 shows the power stage output during start and stop.

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PWMI

PWMD

PWMI

PWMD

PWM start up sequence

PWM stop sequence

Volume Ramp upAnd stream audio

Volume Ramp downTo 50% duty cycle

VALID

VALID

Figure 5.3, PWM start and stop sequence

5.1.3 BTL BD Modulation When the PWM output is used as a digital amplifier with Pure-Path power-stages, a second option is to configure the system in a BD mode BTL bridge tied load configuration. . In the BD mode, the speaker is driven differentially by the amplifier with the PWM and the inverse PWM signal. Figure 5.2Figure 5.4 illustrates the principle in the AD Mode bridge tied load configuration. The inverter may be integrated in the power stage

Figure 5.4, BTL BD modulation

The TAS3308 interfaces to a variety of PurePath power stages to provide a high performance audio power amplifier. See application diagrams in section14 I2C Register Map for configuration details. As shown in the previous section the TAS3308 use the VALID and a special PWM sequence to minimize clicks and pops during start and stop operations.

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edge1+d edge2+d edge2'+dedge1'+d

PWM A+

PWM B-

edge2 edge1 edge2' edge1'

-2Vcc

0V

+2VccVoltageon Load

(a) PWM Outputs and Voltage on Load with Zero Input

edge1edge2 edge2' edge1'

PWM A+

PWM B-

edge2+dedge1+d edge2'+dedge1'+d

-2Vcc

0V

+2VccVoltageon Load

PWM A+

LOAD

PWM B-

+Vcc

-Vcc

(b) PWM Outputs and Voltage on Load with Positive Input (c) H-Bridge

Figure 5.5 Waveform of BD Modulation PWM Outputs and Voltage on Load

5.1.4 Single Ended AD Modulation When the PWM output is used as a digital amplifier with Pure-Path power-stages, one option is to configure the system in a singled ended load configuration, where one terminal on the speaker is being driven from the amplifier and the other end is tied to ground. Figure 5.6 illustrates the principle of the single ended load configuration.

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PCM2PWM

PVDD

Figure 5.6, Single ended AD modulation

The SE configuration presents an additional challenge in order for starting up quietly. The second terminal of the loudspeaker is connected to a split capacitor between power and ground. The advantage of this circuitry is that it provides some degree of power-supply ripple rejection. The problem related to the split capacitor is that the voltage over it must be controlled when the modulator starts (i.e., when the power stage output goes out of high impedance state) to avoid a click in the speaker.

Figure 5.7, SE Filter configuration

The TAS3308 provides an soft start initialization sequence that charges the split capacitor through the loudspeaker. In order to do this without audible artifacts the charge current is limited by applying a start sequence which charges the output state between low, high and high-Z. Because the output stage is in high-Z in a part of the sequence, the resulting output impedance can be brought to a level suitable for charging the split capacitors without audible artifacts. This solution does not require external components, as shown in Figure 5.5. Not all power stages are compatible with the mid-Z scheme. Please refer to the power-stage data sheet for compatibility. To support single ended operation the TAS3308 has a soft start circuit which charges the split capacitor. This is controlled by the PWM Duty 50 Mode Control register (0x1D).

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5.1.5 PWM Valid In normal sense, PWM valid indicates that the PWM output is toggling and functioning as PWM signal. However, since the PWM valid is used to reset power stage in certain configurations, the PWM valid can also have different patterns. The behavior of PWM valid is different for each of three startup modes available in TAS3308.

Low PWM LowLow High LowValid

PWM- I

Enable Disable

Figure 5.8, PWM Valid in Normal Startup Mode In normal startup mode, the PWM modulation of audio data starts as soon as the output is enabled. The VALID output also becomes HIGH at the same time that the PWM starts. As soon as PWM is disabled, the VALID output and PWM output both become LOW. Note that the actual state of PWM pins depends on buffer mode selection. If the buffer is set to Hi-Z mode, then PWM output is high impedance when VALID output is LOW.

Low Duty50 PWM LowLow Mid- Z High LowValid

PWM- I

DisableEnable

Figure 5.9, PWM Valid in Mid-Z Startup Mode In Mid-Z startup mode, the PWM starts with duty 50% pattern. The VALID output starts with pulses at PWM edges with the pulse width grows through time until it reaches 100% (all-time HIGH). When the VALID becomes a continuous HIGH, the PWM output is in normal modulation. At this point audio information is output by the modulator. As soon as PWM is disabled, the VALID output becomes LOW and PWM output also becomes LOW. Note that the actual state of PWM pins depend on buffer mode selection. If the buffer is set to Hi-Z mode, then PWM output is high impedance when VALID output is LOW. The Mid-Z startup mode is intended to permit the PWM-DAC configuration to transition to smooth charging of external passive LPF capacitor and minimize any startup pop/click noise. In PWM-DAC configuration, the VALID output is not used and hence the buffer mode should be set to Hi-Z mode.

Low Duty50 PWM LowDuty50Low High LowValid

PWM- I

DisableEnable

Figure 5.10, PWM Valid in Duty50% Startup Mode In duty50% startup mode, the PWM starts with duty 50% pattern. The VALID output becomes HIGH as soon as the PWM starts. The duty 50% pattern duration is programmable via I2C. As soon as this duration elapsed, normal PWM modulation audio data starts.

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As soon as PWM is disabled, the VALID output becomes LOW but PWM output continues with outputting duty 50% pattern. The duty 50% pattern duration is shared with the duration during start-up. Note that the actual state of PWM pins depend on buffer mode selection. If the buffer is set to Hi-Z mode, then PWM output is high impedance when VALID output is LOW. However, Hi-Z buffer mode is not a recommended setting in the duty 50% pattern because the post PWM disable is not output because VALID will have already gone LOW.

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6. Reference System

This reference system provides all internal references needed by the analog modules. It also provides bias currents for all analog blocks. External decoupling capacitors are needed along with an external 5% tolerance resistor to set the internal bias currents. It includes a band gap reference and several voltage buffers and a tracking current reference. The TAS3308 also uses an internally generated mid supply that is used to re-reference all analog inputs and is present on all analog outputs. VGND is the analog mid supply and can be used when buffered externally to re-reference the analog inputs and outputs.

7. Power Supply

The Power supply contains internal supply regulators that provide analog and digital regulated power for various sections of the TAS3308. The 3.3V analog supply supports the ADC and the output multiplexers. The digital core runs on the internally generated 1.8V supply. The internal voltage regulators are enabled via /VREG_EN pin. This pin must be tied LOW permanently.

8. Control pins

8.1 Reset (/RESET) – Boot-up Sequence /RESET is an asynchronous control signal that restores all TAS3308 components to the default configuration. When a reset occurs, the Digital Audio Processor (DAP) is put into an idle state and the Micro starts initialization. A reset can be initiated by inputting logic ‘0’ on the reset pin /RESET. A reset will also be issued at power turn-on by the internal 1.8V regulators sub-system. There is a 1.3 us de-glitch filter on the /RESET pin. As long as the /RESET terminal is held LOW - the device is in the reset state. During reset, all I2C and Serial Data bus operations are ignored. The I2C interface SCL and SDA lines goes HIGH and remain in that state until device initialization has completed. For proper device initialization and operation:

The /RESET pin should be held low until all of the TAS3308 supply inputs are at 3.0 V or higher or

The /RESET pin should be applied after the all of the TAS3308 supply inputs are at 3.0 V or higher The rising edge of the reset pulse begins the initialization of housekeeping functions by clearing memory and setting the default register values. After housekeeping initialization is complete, the TAS3308 will enable the master interface. Using the Master interface the TAS3308 will automatically test to see if an external I2C EEPROM is at address “1010xxx”. The value xxx can be chip selects, other information, or don’t care depending on the EEPROM selected. If a memory is present and it contains the correct header information and one or more blocks of program/memory data, the TAS3308 begins to load the program, coefficient and/or data memories from the external EEPROM. If an external EEPROM is present, the down load is considered complete when an end of program header is read by TAS3308. At this point, the TAS3308 will disable the master I2C interface, enable the slave I2C interface, and start normal operation. After a successful download, the micro program counter will be reset and the downloaded micro and DAP application firmware will control execution.

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If no external EEPROM is present or if an error occurred during the EEPROM read, TAS3308 will disable the master I2C interface, enable the slave I2C interface initialization, to load the slave default configuration. In this default configuration, the TAS3308 will stream audio from input to output if the GPIO1 pin is LOW. Note: The master and slave interfaces do not operate simultaneously.

Figure 8-1. Digital Boot-up Sequence

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Figure 8-2. Reset Process (Boot Sequence)

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Figure 8-3. I2C Slave Download Flow

8.2 I2C Chip Select The CS pin on the TAS3308 specifies the slave and Master I2C addresses. This control permits up to 2 TAS3308 devices to be separately addressed without external logic.

SLAVE ADDRESS CS 0x68/69 0 0x6A/6B 1

Table 8.1. I2C Slave Addressing

MASTER ADDRESS

CS

0xA0/A1 0 0xA2/A3 1

Table 8.2. I2C Master Addressing

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8.3 GPIO Pins The TAS3308 has two level-sensitive GPIO pins, GPIO1 and GPIO2, which are firmware programmable. Upon power up or following a /RESET, the GPIO1 pin becomes an input, and has a special function as described in the following sections.

8.3.1 GPIO1 pin function after /RESET or power-up Following a /RESET or power up initialization, if no EEPROM is present, a memory error occurs, or SDA and SCL are pulled LOW for 1 ms, then TAS3308 will disable the master I2C interface and enable the slave I2C interface initialization, to load the slave default configuration. When GPIO1 has been pulled HIGH through a 10-20 k ohm resistor The TAS3308 will then initialize in the default configuration with the serial data outputs not active. Once

the TAS3308 has completed its default initialization procedure, with the status register updated and the I2C slave interface enabled, then the GPIO1 pin will become an output and will be driven LOW. Following the High to Low transition of the GPIO1 pin, the system controller can access the TAS3308 through the I2C interface and read the status register to determine the load status.

If a memory read error occurs, the TAS3308 will report the error in the status register. When GPIO1 has been pulled LOW though a 10-20 k ohm resistor To permit a simple functional device test, the GPIO1 pin can be pulled low using external logic and a 10-

20 k ohm resistor. In this case, once the TAS3308 has completed its default test initialization procedure, with the status register updated and the I2C slave interface enabled, the TAS3308 will stream audio from SDIN1 to SDOUT1 and SDOUT2.

At this point the GPIO1 pin will become an output and will be driven LOW. If the external logic is no

longer driving the GPIO1 pin low after the load has completed, then the state of the GPIO1 pin can be observed.

At this point the system controller can access the TAS3308 through the I2C interface and read the status

register to determine the load status. Note 1: If the GPIO1 pin state is not observed, the only indication that the device has completed its initialization procedure is that the TAS3308 will stream audio and the I2C slave interface has been enabled. Note 2: Some I2C masters will hang when they receive a NAC during an I2C transaction. Figure 8-4 illustrates this GPIO1 pin functionality.

8.3.2 GPIO1 pin function once the TAS3308 has been programmed. Once the TAS3308 has been programmed either through a successful boot load or via slave I2C download, the operation of GPIO1 can be programmed to be an input or an output.

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Any State

Enable GPIO1 to be an

Input

Initiate

EEPROM Load

Set Status

Disable Slave & Enable Master

I2 C Interface

Enable Slave

FollowProgramming

Reset or Power up

GPIO1 configured

as an Input

Master I 2C Interface Enabled

Successful Load

Status Set

Set GPIO1to

output

Set GPIO1 LOW

GPIO1 LOW

GPIO1 HIGH

Set GPIO1 LOW

Unsuccessful Load OR

No EEPROM PresentOR

SCL, SDA = LOW for 1ms

Disable Master& Enable Slave

I2C interface

Set GPIO1to

output

Steam SDIN1 toSDOUT1 and

SDOUT2

Figure 8-4. GPIO1 Status Indicator

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8.3.3 General Purpose I/O Ports (GPIO) In the I2C slave mode, the GPIO ports can be used as true general-purpose ports. Each port is configurable individually through I2C, either as an input or an output port. The default assignment for all GPIO ports, in the I2C slave mode, is an input port. When a given GPIO port is programmed as an output port, by setting the appropriate bit in the bit field GPIODIR of sub-address 0x0C to logic 0, the logic level output is set by the logic level programmed into the appropriate bit in bit field GPIO IN OUT. The I2C bus then controls the logic output level for those GPIO ports assigned as output ports. When a given GPIO port is programmed as an input port by setting the appropriate bit in bit field GPIODIR to logic 1, the logic input level into the GPIO port is written to the appropriate bit in bit field GPIO IN OUT. The I2C bus can then be used to read bit field GPIO IN OUT to determine the logic levels at the input GPIO ports. Whether a given bit in the bit field GPIO IN OUT is a bit to be read via the I2C bus or a bit to be written to via the I2C bus is strictly determined by the corresponding bit setting in bit field GPIODIR. In the I2C slave mode, the GPIO input ports are read every GPIOMICROCOUNT Micro Clocks, as was the case in the I2C master mode. However, parameter GPIO_samp_int does not have a role in the I2C slave mode. If a GPIO port is assigned as an output port, a logic 0 bit value is supplied by the TAS3308 for this GPIO port in response to a read transaction at sub-address 0x0C. If the GPIO ports are left in their power turn-on default state, they are input ports with a weak pullup on the input to VDSS.

8.4 GPIO & Watchdog Timer There is a watchdog timer in the TAS3308 that monitors the microprocessor activity. If the microprocessor ever Cease to execute its stored program, the watchdog timer fires and resets the TAS3308. The program structure used in the microprocessor assures that the microprocessor always executes its stored program unless a hardware failure occurs. The watchdog timer is reset based upon the value that is stored in GPIOMICROCOUNT, in sub-address 0x0C. GPIOMICROCOUNT sets the number of micro clock cycles that must pass before the watchdog timer is reset by the firmware. The value must be set to a value to so that will not expire during normal processing of the sample rates supported by the configuration The current value for this counter is 0x5820 which corresponds to a period of 625 µS. The watchdog timer operation is enabled by the MSB of the 32-bit word at sub-address 0x0C. The default value of the MSB of the 32-bit word at sub-address 0x0C is 0 to enable the watchdog timer.

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Figure 8-5. GPIO I/O Ports

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8.5 Mute Control Mute pin functionality is defined by I2C register address 0x09. It contains an 8-byte control word that controls the behavior of the XMUTE pin and software mute. See I2C Register Map Description in section I2C Register Map of this document for further details.

9. Clock, PLL, and Serial Data Interface

This module provides the timing and serial data interface for the TAS3308. The clocking system for the device is illustrated in Figure 9-1. The TAS3308 can be either clock master or clock slave depending on the configuration. Master mode is however the primary mode of operation. Detailed information regarding set-up of the clocking system is provided in section 14 ‘I2C Register Map’.

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Figure 9-1. TAS3308 Clocking System

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9.1 Master Mode Operation • External crystal oscillator is used to generate all internal clocks plus all clocks for external ASRC output

(if ext. ASRC is present) • LRCLKOUT is set at 48 kHz (Fs) • SCLKOUT is set at 64xFs • MCLKOUT is set 256xFs.

In master mode the external ASRC converts incoming serial audio data to 48 kHz sample rate synchronous to the internally generated Serial Audio Data Clocks

9.2 Slave Mode Operation • When auto detect is enabled (recommended setting) MCLKIN (256Fs,384 Fs or 512 Fs), SCLKIN

(64Fs), and LRCLKIN (Fs) • When auto detect is Not enabled (not recommended) MCLKIN (512 Fs), SCLKIN (64Fs), and LRCLKIN

(Fs) • DSP, MCU and I2C clocks are still derived from external crystal oscillator • MCLKOUT, SCLKOUT and LRCLKOUT are passed through from clock inputs (MCLKIN, SCLKIN, and

LRCLKIN). • Internal analog clocks for ADC and PWM’s are derived from external MCLKIN input. Analog

performance will depend on MCLKIN quality (i.e. jitter, phase noise, etc.). Some degradation in analog performance is to be expected with a less than perfect signal.

• Customer specific DAP filter coefficients must be uploaded by Customer system controller on changing sample rate.

In slave mode all incoming serial audio data must be synchronous to an incoming LRCLKIN of 32, 44.1 or 48 kHz.

9.3 Serial Audio Data Formats Serial data is input on SDIN1-3 on the TAS3308, allowing up to 6 channels of digital audio input. The TAS3308 supports serial data in 16-, 20-, or 24-bit data in Left, Right and I2S serial data formats. The parameters for the clock and serial data interface input formats are I2C configurable. Serial Data is output on SDOUT1-2, allowing up to 4 channels of digital audio output. The SDOUT data format is I2S 24 bit at the same data rate as the input. The SDOUT1-2 output uses the SCLKOUT and LRCLKOUT signals to provide synchronization. SDOUT2 is multiplexed with an SPDIF output whose input comes from either the DAP or a muxed SPDIF input.

9.4 Discrete I2S Timing I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is LOW for the left channel and HIGH for the right channel. A bit clock running at 64 × Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3308 will mask unused trailing data bit positions.

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Figure 9.2. SAP I2S Format 64 Fs Format

9.5 Discrete Left Justified Left Justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3308 will mask unused trailing data bit positions.

Figure 9.3. SAP Left Justified 64 Fs Format

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9.6 Discrete Right Justified

Right Justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3308 will mask unused leading data bit positions.

Figure 9.4. SAP Right Justified 64 Fs Format

9.7 SAP Output Normalization SAP input and SAP output normalization is supported. Please see Figure 9.5 to Figure 9.8. When output normalization is enabled, the LRCLKOUT is adjusted when necessary so that the serial data is aligned between input and output. The adjustment includes shifting the LRCLK by one SCLK period and inverting it. In master mode configuration where SAP input is used, there will be direct or indirect LRCLK/SCLK loopback and in this configuration certain input/output mode combinations are prohibited when output normalization is enabled. Table 9.1 and Table 9.2 shows the validity of combinations of input/output mode and output normalization setting, in both master and slave mode. Combinations marked with × are prohibited. Note that these restrictions apply only when SAP input is used.

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Output Normalization Input mode/Output Mode Enabled Disabled Non-I2S/Non-I2S Non-I2S/I2S × I2S/Non-I2S × I2S/I2S

Table 9.1. Validity of Output Normalization in Master Mode

Output Normalization Input mode/Output Mode Enabled Disabled Non-I2S/Non-I2S Non-I2S/I2S I2S/Non-I2S I2S/I2S

Table 9.2. Validity of Output Normalization in Slave Mode

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ExternalData

SourceTAS3308

DAC1(Left Justified)

DAC2(I2S)

I2S

I2SLRCLK

MSB

I2S LRCLK

SCLK

I2S SDIN MSB

Left Channel Right Channel

MSB

Left Justified LRCLK

Left Justified SDOUT MSB

Left Channel Right Channel

Figure 9.5. SAP Output Configuration (I2S to Left Normalization)

MSB

I2S LRCLK

SCLK

I2S SDIN MSB

Left Channel Right Channel

MSBLeft Justified SDOUT MSB

Right Channel Left Channel

Left Justified LRCLK

MSB

Right Channel

Figure 9.6. SAP Output Configuration (I2S to Left Normalization OFF)

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External

DataSource

TAS3308

DAC1(I2S)

DAC2( Left Justified)

Left Justified

I2S

LRC

LK

I2S

SD

OU

T

I2S

SD

IN

Left JustifiedLRCLK

MSB

Left Justified LRCLK

SCLK

Left Justified SDIN

MSB

Left Channel Right Channel

MSB

I2S LRCLK

I2S SDOUT MSB

Left Channel Right Channel

MSB

Left Channel

Figure 9.7. SAP Output Configuration (Left to I2S Normalization)

Figure 9.8. SAP Output Configuration (Left to I2S Normalization OFF)

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9.8 Auto clock and serial data rate detection With the TAS3308 auto clock and serial data rate detection, it is possible to switch clock and data source, without issuing any I2C commands to the TAS3308. The clock system protects the TAS3308 from MCLK glitches and extreme frequencies, and automatically handles clock and serial data rate changes without clicks and pops. Proven technology from the TAS5086 forms the base for the auto detection system implemented in the TAS3308. When the TAS3308 is in auto-detect mode it can operate in a number of different modes as defined in Table 9.3. If the input clock and serial data is valid, the TAS3308 operates on the MCLK and streams audio from ADC and SAP input. If either the incoming MCLK or SAP input is invalid, the TAS3308 mutes the outputs. During mute, the PWM continues operation at approximately 384 kHz to ensure compatibility with power stages.

Table 9.3, modes of operations when auto-detect is enable

Figure 9.9. Auto Detect circuit block diagram

When TAS3308 detects a change in clock or serial data rate, the device will switch clock source to the XTAL, soft mute the PWM and mute SAP outputs controlled by the firmware. The transition to the PWM soft mute is

Mode Input SAP Defines Fs MCLK SAP IN

Fs ADC Fs

DAP Fs

PWM Fs

SAP OUT/SPDIF Fs

Invalid Mute 48kHz 48 kHz 8x48 kHz 48 kHz XTAL source Invalid Mute 48kHz 48 kHz 8x48 kHz 48 kHz 48/44.1 kHz

48 kHz +5% to 44.1-5% 256,384 or 512 Fs Fs Fs Fs 8xFs Fs

32 kHz 32kHz +/- 5% 256,384 or 512 Fs Fs Fs Fs 12xFs Fs

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done gracefully by applying a (fast) volume ramp to the audio signals, thereby utilizing the internal delay memory and the slow response time of the PLL circuit. When new serial data rate is detected, after the configuration has completed, the device apply a reverse (fast) volume ramp and returns to operation. Note that the PWM and SAP continue to be active but outputs a zero signal in the soft mute state

OPERATION

SWITCH TOCRYSTAL ANDRAMP DOWN

VOLUME

WHEN SYSTEM STABLE,

CONFIGUREDEVICE

RAMP UPVOLUME

CLOCK ORSERIAL INPUT

CHANGE

VOLUMERAMP

COMPLETE

SYSTEM ISSTABLE AND

CONFIGURATIONCOMPLETE

VOLUMERAMP

COMPLETE

CLOCK ORSERIAL INPUT

CHANGE

Figure 9.10. Auto Detect Handling

In the ‘configuration’ state, the TAS3308 is operational. The 8051 micro controller can be programmed to interrupt the system controller through one of the GPIO pins. In this event the system board controller can, if desired, download new coefficients to the DAP to match the sample rate

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Figure 9.11. Examples of auto-detect scenarios

Figure 9.6 illustrates three different scenarios when auto-detect is enable. Upper figure shows the behavior when the device is starting up and lock to an incoming serial data stream at 48 kHz. In the middle, sample rate changes from 48 kHz to 44.1 kHz take place. The device detects an Fs change and enters the MUTE state. After locking to the new Fs=44.1KHz, the device restarts the operation with a volume ramp up.

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10. SPDIF Transmitter

The SPDIF transmitter (encoder) is a digital audio transmitter designed for use in consumer audio applications. Transmit data rates up to 48 kHz are supported. The SPDIF encoder complies with the requirements of the IEC-60958 interface standard.

Figure 10-1. SPDIF encoding The SPDIF encoder creates a multiplexed bit stream, containing audio, status, and user data. See Figure 10-2 for the multiplexed data format. The data is then Bi-Phase Mark encoded and output. The output of the SPDIF output port can be selected between the SPDIF encoder output, the serial audio port transmitter output and SPDIF input.

Figure 10-2. SPDIF Frame Format

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While the /RESET input is low, the transmitter output, SPDIF_OUT, is forced to logic low level. Upon setting /RESET high, the SPDIF encoder will remain inactive until the module reset is removed by writing “0” to the RST bit of the control register. Then this module will wait for synchronization with the internal frame clock and starts encoding audio data. It is recommended to set all other SPDIF control register bits before releasing the module reset.

10.1 SPDIF Encoder operation The SPDIF encoder performs the multiplexing of audio, channel status, user, and validity flag. It also performs bi-phase mark encoding of the multiplexed data stream. Audio data for both left and right channels from DAP are latched at the rising of internal LRCLK which marks the beginning of next sample cycle. The SPDIF encoder then multiplexes these samples with internally generated preambles, channel status, user data, validity flag, and parity. The channel status and validity flag are generated based on the settings in the SPDIF control registers while the user data is set to all zero. The bi-phase mark encoded signal is then output starting at the next rising of the internal LRCLK. The generated SPDIF stream is set to consumer mode linear audio PCM format.

10.2 Transmitter control register Below is 8051 SFR register map for SPDIF module control. The relationship with I2C registers is described in the next section.

ADDR 7 6 5 4 3 2 1 0 XX00 RST CP EMP XX01 CATEGORY L XX10 SR VL VR SRCNUM XX11 CLKAC WORDLEN

RST : Module Reset 0 : Normal operation 1 : Reset SPDIF-TX module (default) CP : Copy Permit 0 : Copy prohibit (default) 1 : Copy permit EMP : Pre-emphasis 0 : No pre-emphasis (default) 1 : 50/15 us 2-channel pre-emphasis CATEGORY : Category Code 7-bit device category code. Default: “0101010” (Digital Sound Processor) L : Generation Status 0 : Generation 1 or higher (default) 1 : Original SR : Sampling Rate “00” : 44.1 kHz “01” : 48 kHz (default) “10” : Reserved “11” : 32 kHz VL : Validity for Left Channel 0 : Left channel data is valid (default) 1 : Left channel data is invalid

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VR : Validity for Right Channel 0 : Right channel data is valid (default) 1 : Right channel data is invalid SRCNUM : Source Number “0000” : Not specified “0001” : 1 “0010” : 2 (default) “0011” : 3 ... “1000” : 8 Others : Reserved CLKAC : Clock Accuracy “00” : Level II, 1000ppm “01” : Level III, variable pitch shifted “10” : Level I, 50ppm (default) “11” : Reserved WORDLEN : Sample bit size “0000” : 24 bits (default) “0001” : 23 bits “0010” : 22 bits ... “0100” : 20 bits ... “1000” : 16 bits Others : Reserved

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10.3 I2C Register Map for SPDIF and specification coverage

Figure 10.3 I2C Register to EFSR and Hardware Connection Map

Figure 10.3 shows system accessible I2C register mapping for controlling the SPDIF-TX module. The mute control (MTE) uses the same control bits for controlling SDOUT2 mute at sub-address 0x09 and the module reset (RST) is mapped to sub-address 0x10 together with other power down control bits. Other control bits are mapped to sub-address 0x16. Set-up of the SPDIF transmitter is described in details in section 14 I2C Register Map.

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Specification coverage IEC60956-1: Second Edition, 2004-03 IEC60956-3: Second Edition, 2003-01 IEC958-2: First Edition, 1994-07

Spec Section Supported Remarks IEC60958-1 Interface Format (4) YES Auto frame formatting. IEC60958-1 Channel Status (5) YES First 2 bits set to “00”. (consumer, linear PCM)

IEC958-2

Mode1 (software info delivery using b32-191 of channel stat) (4.2.2.1-4.2.2.3)

NO Bits 28-191 are set to all zero.

IEC60958-3 Channel Status -General (5.1) YES First channel status bit set to “0”.

IEC60958-3 Channel Status -Application (5.2.1) – Byte0 (control)

YES

b0-1 : Set (“00”) b2 : Register settable b3-5 : Register settable b6-7 : Set (“00”)

IEC60958-3 Channel Status -Application (5.2.2) – Byte1 (category)

YES, with restriction

Category code is register settable, with default value “0101010L” (Digital Sound Processor), but user data is set to all zero.

IEC60958-3

Channel Status -Application (5.2.2) – Byte2 (source & channel number)

YES b16-19 : Register settable b20-23 : H/W auto set (1 for left, 2 for right channel)

IEC60958-3

Channel Status -Application (5.2.2) – Byte3 (sampling freq & clock accuracy)

YES, with restriction

b24-27 : Register settable (32,44.1,48 kHz only) b28-29 : Register settable

IEC60958-3

Channel Status -Application (5.2.2) – Byte4 (word length, original sampling rate, Byte0, b1,6,7 = “0”)

YES, partially

b32-35 : H/W auto set according to register setting 24-bit original output sample is truncated to the specified word length. b36-39 : Set to all zero (not indicated)

IEC60958-3 Category Code Groups (5.3.2)

YES, with restriction

Specifying categories other than “0101010L” (Digital Sound Processor), especially those require non-zero user data is not recommended.

IEC60958-3 User Data (6) All Zero

IEC60958-3 Timing accuracy (7.2.1) YES

Clock accuracy indication is register settable. Expected to set level I (50ppm) for master mode (XTAL source) or level II (1000ppm) for slave mode.

IEC60958-3 Line driver characteristics (7.3.2) NO Standard output buffer. Needs external SPDIF driver

(ex.: optical driver)

Table 10.1.

Note: Other sections of the spec that are not mentioned here are either considered irrelevant or covered else. IEC60958-4 is specific for professional applications and thus, irrelevant.

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11. Micro Controller

The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus controllers the required I2C read data, and participate in most processing tasks requiring multi-frame processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C commands, a set boot program ROM and a programmable program RAM. The microprocessor’s boot program cannot be altered. The Micro Controller has specialized hardware for a master and slave interface operation, and a programmable interval timer interrupt. The TAS3308 has a slave only I2C interface that compatible with the I2C (Inter IC) bus protocol and supports both 100 KBPS and 400 KBPS data transfer rates for single and multiple byte write and read operations. The TAS3308 has a master only I2C interface that compatible with the I2C (Inter IC) bus protocol and supports 400 KBPS data transfer rates for single and multiple byte write and read operations. The control interface is used to program the registers of the device and to read device status. Upon power up the TAS3308, the slave interface is disabled and the master interface is enabled. Following a Reset, the TAS3308 will disable the slave interface and enable the master interface. Using the Master interface the TAS3308 will automatically test to see if an I2C EEPROM is at address “1010xxx”. The value xxx can be chip selects, other information, or don’t care depending on the EEPROM selected. If a memory is present and it contains the correct header information and one or more blocks of program/memory data, the TAS3308 load the program, coefficient and/or data memories from the EEPROM. If a memory is present, the down load is complete when header is read that has a zero length data segment. At this point, the TAS3308 will disable the master I2C interface, enable the slave I2C interface, and start normal operation. If no memory is present or if an error occurred during the EEPROM read, TAS3308 will disable the master I2C interface, enable the slave I2C interface initialize, and load the unprogrammed default configuration. In this default configuration, the TAS3308 will stream 2 channels of audio from SDIN1 to SDOUT1/SDOUT2if the GPIO1 pin is LOW. In the slave mode, the I2C bus is used to:

• Load or instruct the load of program and coefficient data o Micro Program memory o Micro Extended Memory o DAP Program Memory o DAP Coefficient Memory o DAP Data Memory

• Update coefficient and other control values • Read status flags

Once the micro program memory has been loaded, it can not be updated until the TAS3308 has been RESET. The master and slave modes do not operate simultaneously. When acting as an I2C master, the data rate transfer is set at 375 kHz. The I2C communication protocol for the I2C slave mode is shown in Figure 11-1.

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Figure 11-1. I2C Slave Mode Communication Protocol

11.1 General I2C operations The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data be transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. The master generate the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The slave holds SDA LOW during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 11-1 shows the TAS3308 Read and Write operation sequences. As shown in Figure 11-1, a read transaction requires that the master device first issue a write transaction to give the TAS3308 the sub address to be used in the read transaction that follows. This sub address assignment write transaction is then followed by the read transaction. For write transactions, the sub address is supplied in the first byte of data written, and this byte is followed by the data to be written. For write transactions, the sub address must always be included in the data written. There cannot be a separate write transaction to supply the sub address, as was required for read transactions. If a sub-address assignment only writes transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS3308 as another sub address replacing the one previously written.

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S TAS3108Address W

Start(By Master)

Write(By Master)

7-Bit Slave Address(By Master)

A CK Sub-Address

Acknowledge(By TAS3108)

TAS3108Sub-Address(By Master)

A CK S

Stop(By Master)

S TAS3108Address R

Start(By Master)

Read (By Master)

7-Bit Slave Address(By Master)

A CK Data

Acknowledge(By TAS3108)

Data(By TAS3103)

A CK S

Stop(By Master)

Acknowledge(By Master)

Data A CK

Data(By TAS3103)

Acknowledge(By Master)

NA K

No AcknowledgeBy Master

I2C READ TRANSACTION

S TAS3108Address W

Start(By Master)

Write(By Master)

7-Bit Slave Address(By Master)

A CK Sub-AddressA CK

Acknowledge(By TAS3108)

Acknowledge(By TAS3108)

Acknowledge(By TAS3108)

Acknowledge(By TAS3108)

Data

Data(By Master)

A CK Data

Data(By Master)

A CK S

Stop(By Master)

A CK

Acknowledge(By TAS3108)

I2C WRITE TRANSACTION

Acknowledge(By TAS3108)

TAS3108Sub-Address(By Master)

Figure 11-2. I2C Sub-address Access Protocol

11.2 I2C Master Mode Device Initialization I2C Master Mode operation is enabled following a reset or power on reset. The TAS3308 uses the master mode to download from EEPROM the memory contents for the:

• Micro Program memory • Micro Extended Memory • DAP Program Memory • DAP Coefficient Memory • DAP Data Memory

The TAS3308, when operating as an I2C master, can execute a complete download of any internal memory or any section of any internal memory without requiring any wait states. When the TAS3308 operates as an I2C master the TAS3308 will generate a repeated start without an intervening stop command while downloading program and memory DATA from EEPROM. When a repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to quickly transfer large blocks of data. The TAS3308 will query the bus for an I2C EEPROM at an address “1010xxx”. The value xxx can be chip selects, other information, or don’t cares depending on the EEPROM selected. The first act of the TAS3308 as master will be to transmit a start condition along with the device address of the I2C EEPROM with the read/write bit cleared (“0”) to indicate a write. The EEPROM acknowledges the address byte, and the TAS3308 send a sub address byte, which the EEPROM will acknowledge. Most EEPROMs have at least 2-byte addresses and will acknowledge as many as are appropriate. At this point, the EEPROM sends a

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last acknowledge and becomes a slave transmitter. The TAS3308 acknowledges each byte repeatedly to continue reading each data byte that is stored in memory. The memory load information starts with reading the header and data information that starts at sub-address 0 of the EEPROM. This information must be stored in a sequential memory addresses with no intervening gaps. The Data block is contiguous blocks of data that immediately follow the headers locations. The TAS3308 memory data can be stored and loaded in (almost) any order. Additionally this addressing scheme permits portions of the TAS3308 internal memories to be loaded

I2C EEPROM Memory Map

Block Header 1

Block Header 2

Block Header N

…

Data Block N

Data Block 1

Data Block 2

Figure 11-3. EEPROM Address Map

The TAS3308 will sequentially read EEPROM memory and load its internal memory unless it does not find a valid memory header block, is not able to read the next memory location because the end of memory was reached, detects a check sum error, or reads a end of program header block. When it encounters a valid header or read error, the TAS3308 will attempt to read the header or memory location three times before it determines that it has an error. If the TAS3308 encounters a Check Sum error it will attempt to re-read the entire block of memory two more times before it determines that it has an error. Once the micro program memory has been loaded, it can not be reloaded until the TAS3308 has been RESET. If an error is encountered TAS3308 terminates its memory load operation, loads the default configuration and disables further master I2C bus operations. If an end of program data block is read, the TAS3308 has completed the initial program load The I2C master mode utilizes the starting and ending I2C check sums to verify a proper EEPROM download. The first 16-bit data word received from the EEPROM is the I2C check sum at sub address 0x00, is stored and compared against the 16-bit data word received for last sub-address, the ending I2C check sum and the check sum that is computed during the download. These three values must be equal. If the read and computed values do not match, the TAS3308 sets the memory read error bits in the Status register and repeats the download from the EEPROM two more times. If the comparison check again fails the third time, the TAS3308 sets the micro program to the default value.

11.3 Memory block format 11.3.1 Memory block header

Starting Byte Data Block Format Size Notes

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Checksum MS byte 0 Checksum LS byte 2 bytes Checksum of byte 2 through N+12

Header ID byte1 = 0x00 2 Header ID byte2 = 0x1F 2 bytes Must be 0x001f for the TAS3308

4 Memory to be loaded 1 byte

0x00 : micro program ram or termination header 0x01 : micro external data ram 0x02 : dap program ram 0x03 : dap coefficient ram 0x04 : dap data ram 0x05 : dap upper data ram 0x06 : dap upper coefficient ram 0x07 - 0x0F : reserved

5 0x00 1 byte unused Start memory address MS byte 6 Start memory address LS byte 2 bytes If this is a termination header, this value is

0000 Total number of bytes transferred MS byte

8 Total number of bytes transferred LS byte 2 bytes

Header size (12) + data byte + last checksum byte. If this is a termination header, this value is 0000

10 0x00 1 byte unused 11 0x00 1 byte unused

Table 11.1. Memory block header

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11.3.2 Memory block structures

Starting Byte Data Block Format Size Value NoteChecksum MS byteChecksum LS byteHeader ID byte1 0x00Header ID byte2 0x1F

4 Memory to be loaded 1byte 0x00 or 0x01 micro program ram or micro external data ram

5 0x00 1byte 0x00 unusedStart memory address MS byteStart memory address LS byteTotal number of byte transferred MS byteTotal number of byte transferred LS byte

10 0x00 1byte 0x00 unused11 0x00 1byte 0x00 unused

Data byte 1 (LS Byte)Data byte 2Data byte 3Data byte 4 (MS Byte)Data byte 5 (LS Byte)Data byte 6Data byte 7Data byte 8 (MS Byte)

0x000x00Checksum MS ByteChecksum LS Byte

N + 12 4byte repeated checksum byte 2 through N+11

12 4byte 1-4 microprocessor byte

16 4byte 5-8 microprocessor byte

6 2byte If this is a termination header, this value is 0000

8 2byte header (12) + data (N) + checksum (4)

0 2byte checksum of byte 2 through N+12

2 2byte must be 0x001f for the TAS3308

Table 11.2. Micro Program or External Data

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Starting Byte Data Block Format Size Value NoteChecksum MS byteChecksum LS byteHeader ID byte1 0x00Header ID byte2 0x1F

4 Memory to be loaded 1byte 0x02 DAP program ram5 0x00 1byte 0x00 unused

Start memory address MS byteStart memory address LS byteTotal number of byte transferred MS byteTotal number of byte transferred LS byte

10 0x00 1byte 0x00 unused11 0x00 1byte 0x00 unused

Program byte 1 (LS Byte) Program word 1 D7-D0Program byte 2 D15-D8Program byte 3 D23-D16Program byte 4 D31-D24Program byte 5 D39-D32Program byte 6 D47-D40Program byte 7 (Ms Byte) D55-D48Program byte 8 (LS Byte)Program byte 9Program byte 10Program byte 11Program byte 12Program byte 13Program byte 14 (MS Byte)

0x000x000x000x000x00Checksum MS ByteChecksum LS Byte

Program word 2

N + 12 7byte repeated checksum byte 2 through N+11

12 7byte

19 ７byte

6 2byte If this is a termination header, this value is 0000

8 2byte header (12) + data (N) + checksum (7)

0 2byte checksum of byte 2 through N+12

2 2byte must be 0x001f for the TAS3308

Table 11.3. DAP Program

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Starting Byte Data Block Format Size Value Note

Checksum MS byte

Checksum LS byte

Header ID byte1 0x00

Header ID byte2 0x1F

4 Memory to be loaded 1byte 0x03 DAP coefficient ram

5 0x00 1byte 0x00 unused

Start memory address MS byte

Start memory address LS byte

Total number of byte transferred MS byte

Total number of byte transferred LS byte

10 0x00 1byte 0x00 unused

11 0x00 1byte 0x00 unused

Data byte 1 (LS Byte) Coefficient word 1 D7-D0

Data byte 2 D15-D8

Data byte 3 D23-D16

Data byte 4 (MS Byte) D31-D24

Data byte 5 (LS Byte)

Data byte 6

Data byte 7

Data byte 8 (MS Byte)

0x00

0x00

Checksum MS Byte

Checksum LS Byte

0 2byte checksum of byte 2 through N+12

2 2byte must be 0x001f for the TAS3308

6 2byte If this is a termination header, this value is 0000

8 2byte header (12) + data (N) + checksum (4)

12 4byte

16 4byte coefficient word 2

N + 12 4byte repeated checksum byte 2 through N+11

Table 11.4. DAP Coefficient

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Starting Byte Data Block Format Size Value Note

Checksum MS byte

Checksum LS byte

Header ID byte1 0x00

Header ID byte2 0x1F

4 Memory to be loaded 1byte 0x04 DAP data ram

5 0x00 1byte 0x00 unused

Start memory address MS byte

Start memory address LS byte

Total number of byte transferred MS byte

Total number of byte transferred LS byte

10 0x00 1byte 0x00 unused

11 0x00 1byte 0x00 unused

Data byte 1 (LS Byte) Data word 1 D7-D0

Data byte 2 D15-D8

Data byte 3 D23-D16

Data byte 4 D31-D24

Data byte 5 D39-D32

Data byte 6 (MS Byte) D47-D40

Data byte 7 (LS Byte)

Data byte 8

Data byte 9

Data byte 10

Data byte 11

Data byte 12 (MS Byte)

0x00

0x00

0x00

0x00

Checksum MS Byte

Checksum LS Byte

N + 12 6byte repeated checksum byte 2 through N+11

Data word 2

12

18

6byte

6byte

6 2byte If this is a termination header, this value is 0000

8 2byte header (12) + data (N) + checksum (6)

0 2byte checksum of byte 2 through N+12

2 2byte must be 0x001f for the TAS3308

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Table 11.5 DAP Data Starting Byte Data Block Format Size Value Note

Checksum MS byte 0x00Checksum LS byte 0x00Header ID byte1 0x00Header ID byte2 0x1F

4 Memory to be loaded 1byte 0x00 micro program ram or micro external data ram5 0x00 1byte 0x00 unused

Start memory address MS byte 0x00Start memory address LS byte 0x00Total number of byte transferred MS byte 0x00Total number of byte transferred LS byte 0x00

10 0x00 1byte 0x00 unused11 0x00 1byte 0x00 unused

Data byte 1 (LS Byte) 0x00Data byte 2 0x00Data byte 3 0x00Data byte 4 (MS Byte) 0x000x00 0x000x00 0x00Checksum MS Byte 0x00Checksum LS Byte 0x00

0 2byte checksum of byte 2 through N+12

2 2byte must be 0x001f for the TAS3308

6 2byte If this is a termination header, this value is 0000

8 2byte header (12) + data (N) + checksum (4)

16 4byte checksum byte

12 4byte dummy data

Table 11.6 Termination header (End header)

11.4 I2C Slave Mode Operation The TAS3308 has two I2C interfaces. I2C-2 is dedicated for loading boot program from an EEPROM and is a master only interface. Both interfaces support standard and fast mode operations. The I2C-1 interface is a slave mode interface, that is used to change configuration parameters during operation and perform program and coefficient downloads from a master device. I2C-1 can be used to replace the I2C master mode EEPROM download. The TAS3308 support both random and sequential I2C transactions. The TAS3308 I2C slave address is “011010X”, where the first 6 bits are the TAS3308 device address and the final 1 bit is set by the TAS3308 internal microprocessor at power-up. The internal microprocessor derives the last bit from an external pin (pin CS) which is pulled up or down to create 2 unique addresses for control of multiple-TAS3308 part applications. The pull-down resistance of CS creates a default “00” address when no connection is made to the pin. The TAS3308 I2C block does respond to the broadcast address (00h).

Slave Address CS 0x68/69 0 0x6A/6B 1

Table 11.6. Slave Addresses

Master Address CS 0xA0/A1 0 0xA2/A3 1

Table 11.7. I2C Master Addresses

The complete Philips I2C bus specification version 2.1 January 2000 can be found at http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf. This document includes specification of the random and sequential transactions as well multi-byte write and read actions.

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11.5 Microcontroller I2C Controls 11.5.1 System Status

The TAS3308 has a 8 byte status register that provide general device information. Memory Load Errors Micro program Memory Micro External Data Memory DAP Program Memory DAP Coefficient Memory DAP Data Memory The status of a memory load is found by reading the memory error bits of the status word. All of these bits are set to zero upon reset. When a memory read error for a particular memory occurs, the memory load error bit for that memory is set to 1. When a memory read is successful performed for a particular memory the memory load error bit for that memory is set to 0.

11.5.2 I2C Memory Load Port The I2C Memory Load port permits the system controller to load the TAS3308 memories as an alternative to having the TAS3308 load its memory from EEPROM Micro Program memory Micro Extended Memory DAP Program Memory DAP Coefficient Memory DAP Data Memory The transfer is performed by writing to two I2C registers. The first register is a eight byte register than holds the check sum, the memory to be written, the starting address, the number of data bytes to be transferred. The second register holds eight bytes of data. The memory load operation starts with the first register being set. Then the data is written into the second register using the format shown. After the last data byte is written into the second register, an additional two bytes are written which constrain the two byte checksum. At that point, the transfer is complete and status of the operation is reported in the status register. Note – Once the micro program memory has been loaded, further updates to this memory are inhibited until the device is RESET. When the first I2C slave down load register is written by the system controller the TAS3308 will update the status register by setting an error bit to indicate an error for the memory type that is being loaded. This error bit is reset when the operation complete and a valid checksum has been received. For example when the Micro program memory is being loaded, the TAS3308 will set a Micro program memory error indication in the status register at the start of the sequence. When the last byte of the micro program memory and checksum is received, the TAS3308 will clear the micro program memory error indication. This enables the TAS3308 to preserve any error status indications that occur as a result of incomplete transfers of data/ checksum error during a series of data and program memory load operations. The checksum is always contained in the last two bytes of the data block. The I2C slave down load is terminated when a termination header with a zero length byte count filed is received.

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11.6 8051 Addressing Modes The 256 bytes of Internal Data Memory address space is accessible using indirect addressing instructions (including stack operations). However, only the lower 128 bytes are accessible using direct addressing. The upper 128 bytes of direct address Data Memory space are used to access ESFRs.

11.6.1 Register Banks There are four directly addressable register banks, only one of which may be selected at one time. The register banks occupy Internal Data Memory addresses from 00 hex to 1F hex.

11.6.2 Bit addressing The 16 bytes of Internal Data Memory that occupy addresses from 20 hex to 2F hex are bit-addressable. SFRs that have addresses of the form 1XXXX000 binary are also bit-addressable.

11.6.3 Scratchpad Internal Data Memory occupying direct addresses from 30 hex to 7F hex can be used as scratch pad registers or for the stack.

11.6.4 External Data Memory External Data Memory occupies a 64K address space. This space contains the External Special Function Data Registers ESFRs. The ESFR permit access and control of the hardware features and internal interfaces of the TAS3308.

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12. Digital Audio Processor (DAP) Arithmetic Unit

12.1 Overview The arithmetic processor is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The primary features are:

• Two pipe parallel processing architecture o 48-bit datapath with 76-bit accumulator o Hardware single cycle multiplier (28 x 48) o Three 48 bit general-purpose data registers o One 28 bit coefficient register o Adder with 48 bit and 76 bit inputs o Shift Right, Shift left o Bi-modal clip o Log2/Alog2 o Magnitude Truncation

• Read/read/write single-cycle memory access • Data input is 48-bit 2’s complement muxed in from SAP immediately following FSYNC pulse • Separate control for writing to delay memory. • Separate coefficient memory (28-bit) and data memory (48-bit) • Linear Feedback Shift Register (LFSR) in the instruction register doubles as a random number generator

in normal operating mode • Coefficient RAM, Data RAM, LFSR seed, Program counter, and memory pointers are all mapped into

the same memory space for convenient addressing by the micro • Memory interface block contains four pointers, two for data memory and two for coefficient memory

12.1.1 Data Format The following shows the data word structure of the arithmetic unit. Eight bits of overhead or guard bits are provided at the upper end of the 48-bit word, and 16 bits of computational precision or noise bits are provided at the lower end of the 48-bit word. The incoming digital audio words are all positioned with the most significant bit abutting the 8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as signed data samples. The arithmetic engine is a 48-bit (25.23 format) processor consisting of a general-purpose 76-bit arithmetic logic unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks) always involve 48-bit words and 28-bit coefficients (usually I2C programmable coefficients). If a group of products are to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain precision in the intermediate computational stages. To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations, intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow will correct the overflow condition. The memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM, and a set program ROM. Only the coefficient RAM, assessable via the I2C bus, is available to the user.

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Figure 12-1. Arithmetic Unit Data Word Structure

10110111 (-73) -73 + 11001101 (-51) + -51 10000100 (-124) -124 + 11010011 (-45) + -45 01010111 (57) -169 + 00111011 (59) + 59 10010010 (-110) -110

8-Bit ALU Operation (Without Saturation)

Rollover

Figure 12-2. DAP ALU Operation with Intermediate Overflow

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Figure 12-3. DAP Datapath Data Representation

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12.2 DAP Interface

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Figure 12-4. DAP Datapath Architecture

Figure 12-5. DAP Output Register Configuration

48-bitDatapath

28 x 48-bit Multiplier76-bit Accumulator

Coef RAM(1K x 28)

Data RAM(1K x 48)

Program RAM(3.25K x 55)

DSPController

MemoryInterface

Delay Memory

(17408 x 24)

8-bit MCU (8051)

InternalData RAM(256 x 8)

ExternalData RAM

(2K x 8)

Program RAM(20K x 8) Delay

Control

Figure 12-6. DAP, MCU and Memory Interfaces

12.3 Delay Memory The Delay Memory Interface (DMIF) is the interface block between the DAP core and the delay memory. The DMIF block’s primary purpose is to keep track of twenty four sets of delay memory pointers that are initially set

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up by the micro controller through an I2C command(s). Eight of the pointers are used to write/retrieve 48-bit data (full-precision intermediate) and the other sixteen for 24-bit data (post quantized). Thus to support 48-bit word reverb delay, two RAM locations must be used. The key features of the Delay memory are

• 17408 x 24 delay memory locations • Twenty four separately addressable pointers • Programmable start/stop address on each pointer • Pointers capable of accessing 24-bit or 48-bit words • Single port access (one pointer access per access cycle) • Access cycle < 4 DSP clocks • Self clearing – INIT pin used to clear all memory to zero • Fully synchronous

• DP1 – DP16 Sixteen 24-bit pointers • RP1 – RP8 Eight 48-bit (full precision) pointers

Since all of the pointers are contiguous, it is only necessary to write the address END point. For example, if DP1 is to be a three-sample delay, the register DP1 should be set to 0x003. If RP1 is to be a 3 sample delay, the register RP1 should be set to the value of DP15 + 6. All of the DP1-16 and RP1-8registers must be set to a minimum of a one sample delay (one or two words). DP1 Start address is defined as 0x0000 DP2 Start address is equal to DP1 end address + 1 ... RP1 Start address is equal to DP16 end address + 1 ... RP8 Start address is equal to RP7 end address + 2 Since the start/stop address for each pointer is programmable anywhere in the delay RAM’s address space, the delay for any one channel can be anywhere in the delay RAM. There is, however, no address space collision avoidance logic to separate the pointers. The user (or micro) must take care to avoid overlapping the address spacing of each pointer. Pointer register address endpoint registers DP1-DP16 and RP 1-RP8 are typically written only during the initialization (fast load) mode of the device. Writing to these registers while the TAS3308 DSP core is accessing the pointers may cause the pointers to cross the address space of another pointer. To write to the delay RAM, the TAS3308 DSP core controller must present the data to be written on the PT_DATA bus (LS bit always in bit zero of the bus), select the pointer to be accessed by driving the PT_SEL pins, and assert the PT_WZ pin for a minimum of four clocks. The pointer will not increment until a write has been performed and the PT_WZ pin has been de-asserted. To perform a read, the PT_OUT bus may be read four clocks after PT_SEL is driven.

12.4 DAP Instruction Word TAS3308 has a 55-bit instruction word. Each instruction has five independent operations, which can load two operands from data memory and coefficient memory, store the result into data or coefficient memory and perform two parallel arithmetic operations.

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55 bit instructionALU 1st stage ALU 2nd stage Data mem load Coef mem load Mem store

P1OP P2OP MOP1 AD1 MOP2 AD2 MOP3 AD353-49 48-42 41-37 26-24 13-1036-27 23-14 9-0

Ext

540

Figure 12-7. TAS3308 instruction word

The TAS3308 instruction set is a superset of the TAS3108 instruction set, extending the DAP processing capabilities for improved efficiency of FIR operations as well as extending the addressable memory space. The Ext instruction bit (bit 54) has been added to extend the internal memory address space by 1 bit, increasing the memory space from 1K to 2K words. The superset instruction word maintains backward compatibility with the 54-bit instruction word of the TAS3108 device, since the 54 bit instruction word required dummy storage of 2 bits in the EEPROM.

Figure 12-8. TAS3108 instruction word

As shown in Figure 12-9 the extension bit designates an offset of 1K to all three addresses in the instruction word. However, it should be noted that both data and coefficient memory addresses above the 1K boundary are reserved for housekeeping processing tasks (see Figure 12-1). Any attempt to write to these addresses may corrupt the audio output.

Figure 12-9. TAS3308 instruction word extension field

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12.5 DAP Instruction set Please see the TAS3108/TAS3108A Firmware Programmer’s Guide (SLEU067) for detailed information regarding programming of this device.

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13. Physical Characteristics

13.1 Absolute Maximum Ratings over Operating Temperature Ranges (Unless Otherwise Noted)+ Supply voltage range, DVDD.................................................................................................................-0.5 to 3.8 V Supply voltage range, AVDD.................................................................................................................-0.5 to 3.8 V Supply voltage range, DVDD_PWM......................................................................................................-0.5 to 3.8 V Input voltage range, VI : 3.3 V TTL................................................................................... -0.5 V to VDDS + 0.5 V 3.3 V LVCMOS.......................................................................... -0.5 V to VDDS + 0.5 V 3.3 V Analog............................................................................-0.5 V to AVDDS + 0.5 V 1.8 V LVCMOS....................................................................... -0.5 V to AVDD(1) + 0.5 V Output voltage range, VO : 3.3 V TTL................................................................................... -0.5 V to VDDS + 0.5 V 3.3 V LVCMOS.......................................................................... -0.5 V to VDDS + 0.5 V 3.3 V Analog............................................................................-0.5 V to AVDDS + 0.5 V 1.8 V LVCMOS....................................................................... -0.5 V to DVDD(2) + 0.5 V 1.8 V LVCMOS....................................................................... -0.5 V to AVDD(3) + 0.5 V Input clamp current, IIK (VI < 0 or VI > DVDD) ........................................................................................... +/-20 mA Output clamp current, IOK (VO < 0 or VO > DVDD) ..................................................................................... +/-20 mA Storage temperature range, Tstg ....................................................................................................... -65oC to 150oC Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .................................................................. 260oC + Stresses beyond those listed under “absolute ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operation conditions” is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability. Notes: (1) AVDD is an internal 1.8V supply derived from a regulator in the TAS3308 chip. Pin XTALI is the only

TAS3308 input that is referenced to this 1.8V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI.

(2) DVDD is an internal 1.8V supply derived from regulators in the TAS3308 chip. DVDD is routed to– DVDD_BYPASS_CAP – to provide access to external filter capacitors, but should not be used to source power to external devices.

(3) Pin XTALO is the only TAS3308 output that is derived from the internal 1.8V logic supply AVDD. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALO. AVDD is also routed to – AVDD_BYPASS_CAP – to provide access to external filter capacitors, but should not be used to source power to external devices.

PACKAGE DISSIPATION RATING TABLE (High-k Board, 105°C Junction)

PACKAGE TA ≤ 25° Power Rating

DERATING FACTOR ABOVE TA = 25°C

TA = 70°C POWER RATING

TQFP PZT100

1.62W 49.3°C/Ｗ 0.71W

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13.2 Recommended Operating Conditions PARAMETER MEASUREMENT MIN NOM MAX UNITS

Digital supply voltage, DVDD 3.0 3.3 3.6 V Analog supply voltage, AVDD 3.3V Analog 3.0 3.3 3.6 V PWM supply voltage, DVDD_PWM 3.3V PWM 3.0 3.3 3.6 V

3.3 V TTL 2.0 - V 3.3 V LVCMOS (I2C) 0.7 VDDS High-level input voltage, VIH

1.8 V LVCMOS (XTL_IN) 1.26 - V 3.3 V TTL - 0.8 V

3.3 V LVCMOS (I2C) 0 - 0.3 VDDS V Low-level input voltage, VIL 1.8 V LVCMOS (XTL_IN) - 0.54 V

Operating ambient air temperature range, TA (Guarantying Parametrics)

0 25 70 oC

Operating ambient air temperature range, TA (Guarantying Functions)

-20 25 70 oC

13.3 Audio Specifications (Channel – Input to Output) At +25°C, AVDD = +3.3V, DVDD = +3.3V, Fs (Audio) = 48kHz, Clock Source from XTALI, AES17 Filter (unless otherwise noted) Parameter Conditions Min Typ Max Units Overall dynamic range A-in->ADC->DSP->PWM A-WTD 99 dB

Overall dynamic range A-in -> MUX -> Lineout A-WTD 102 dB

13.4 Audio Specifications (Digital Filters) At +25°C, AVDD = +3.3V, DVDD = +3.3V, Fs (Audio) = 48kHz, Clock Source from XTALI, AES17 Filter (unless otherwise noted) Parameter Conditions Min Typ Max Units ADC DECIMATION FILTER: Fs = 48kHz Filter Passband Edge (*) 0.453 Fs Hz Passband Ripple +/- 0.05 dB Stopband Edge (*) 0.547 Fs Hz Stopband Attenuation -100 dB Filter Group Delay 37/Fs Sec PWM INTERPOLATION FILTER : Fs = 48kHz Filter Passband Edge (*) 0.4535Fs Hz Passband Ripple ±0.05 dB Stopband Edge (*) 0.5465Fs Hz Stopband Attenuation -48 dB Filter Group Delay 16.25/Fs Sec DC blocking filter -3db cut-off frequency 0.94 Hz

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(*) : Filter pass band for LPF FIR is defined as the band up to where the passband ripple is met. The ripple is defined as the deviation of the filter gain from its supposed one, which is 0 dB. The filter gain starts going below passband ripple constraint from the passband edge frequency. The frequency where the filter gain goes below the stop band attenuation level is defined as the stopband edge. In the case of LPF, the filter gain will not become more than stopband attenuation level beyond the stopband edge. The difference between passband edge and stopband edge gives the transition width of the filter.

13.5 Electrical Specifications (Analog Sections) At +25°C, AVDD = 3.3V, DVDD = 3.3V, Fs (Audio) = 48kHz, AES17 Filter, Clock Source from XTALI (unless otherwise noted)

Parameter CONDITIONS MIN TYP MAX UNITS

STEREO MUX INPUT/ADC Channel

1kHz sine wave input Measured at SDOUT@48kHz

Full Scale Input Voltage (0dB) 1.0 Vrms Input Common Mode Voltage Over recommended operating

conditions 1.5 V

DNR -60dB full-scale input applied at Line inputs, A-weighted

100 dBA

THD+N 1kHz, -4dB full scale input 80 dB PSRR 1kHz, 100mVpp on AVDD 57 dB Channel Separation 1kHz, between Lch and Rch

and each input source 78 dB

Input resistance Input buffer 26.11 KΩ Input capacitance Input buffer 10 pF PWM output (general characteristics)

1kHz sine wave digital input

Modulation index (programmable) 96.1 % PWM carrier frequency 48/44.1 kHz input Fs

32 kHz input Fs 8xFs

12xFs Hz

Hz PWM output (with passive LPF, no load)

1kHz sine wave digital input Measured at LPF output

Full Scale output voltage 1.09 Vrms DNR -60 dB full scale input, 105 dBA THD+N -10 dBFS 83

0.007 dB

% Frequency Response 20 Hz to 20 kHz -1 / + 0.5 dB Channel Separation and Cross talk

80 dB

Power Supply Ripple Rejection 6 dB Analog Mux in Bypass Mode 1kHz sine wave input,

Load = 10 KΩ, 10pF

Full Scale Output Voltage (0dB) 1.0 Vrms Full Scale Input Voltage (0dB) 1.0 Vrms DNR -60 dB full scale input 100 dBA Common Mode Voltage 1.5 V Input impedance 26.11 kΩ Load Capacitance 20 pF Load resistance 10 KΩ Cross talk 80 dB MUX Switching Noise LINEIN inputs floating 20 mV

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13.6 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)

PARAMETER MEASUREMENT TEST CONDITIONS MIN TYP MAX UNITS

3.3 V TTL IOH = -4 mA 2.4 - - V

3.3 V LVCMOS (I2C) IOH = - 0.10 mA VDDS-0.2 - - V High-level output

voltage, VOH 1.8 V LVCMOS (XTL_OUT) IOH = -0.6 mA 1.197 - - V

3.3 V TTL IOL = 4 mA - - 0.5 V 3.3 V LVCMOS (I2C) IOL = 0.10 mA - - 0.2 V Low-level output

voltage, VOL 1.8 V LVCMOS (XTL_OUT) IOL = 1.8 mA - - 0.585 V

3.3 V TTL - - - +/- 20 uA High-impedance output current, IOZ

3.3 V LVCMOS (I2C)

Driver only, driver disable - - +/- 20 uA

3.3 V TTL VI = VIL - - +/- 1 uA

3.3 V LVCMOS (I2C)

VI = VIL, Receiver only

- - +/- 1 uA Low-level input current, IIL

(1) 1.8 V LVCMOS (XTL_IN) VI = VIL - - +/- 1 uA

1.8 V LVCMOS (XTL_IN) VI = VIH - - +/- 1 uA

3.3 V LVCMOS (I2C)

VI = VIH, Receiver only

- - +/- 1 uA High-level input current, IIH(2)

3.3 V TTL VI = VIH - - +/- 1 uA Digital supply current, IDVDD

DSP clock = 135 MHz LRCLKIN/LRCLKOUT = 48 KHz, XTALI = 24.576 MHz

- - 160 mA

Analog supply current, IAVDD

DSP clock = 135 MHz LRCLKIN/LRCLKOUT = 48 KHz, XTALI = 24.576 MHz

- - 40 mA

Digital supply current, IDVDD

/RESET = LOW - - 100 mA

Analog supply current, IAVDD

/RESET = LOW - - 10 mA

Notes: (1) Value given is for those input pins that connect to an internal pull-up resistor as well as an input buffer. For

inputs that have a pull-down resistor or no resistor, IIL is ± 1 μa. 2) Value given is for those input pins that connect to an internal pull-down resistor as well as an input buffer. For

inputs that have a pull-up resistor or no resistor, IIH is ± 1 μa.

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13.7 TAS3308 Timing Characteristics 13.7.1 Master Clock Signals Over Recommended Operating Conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

fXTALI Frequency, XTALI (1 / tcyc1) 24.576MHz ±100ppm

MHz

tcyc1 Cycle time, XTALI See note 1 1/(512Fs) ns fMCLKIN Frequency, MCLKIN (1 / tcyc2) See note 5 256 Fs 512 Fs MHz twMCLKIN Pulse duration, MCLKIN See note 2 0.4 * tcyc2 - 0.6 * tcyc2 ns fMCLKOUT Frequency, MCLKOUT (1 / tcyc3) 256 Fs MHz trMCLKOUT Rise Time, MCLKOUT CL = 30 pF - - 10 ns tfMCLKOUT Fall Time, MCLKOUT CL = 30 pF - - 10 ns twMCLKOUT Pulse duration, MCLKOUT See note 3 0.4 * tcyc3 - 0.6 * tcyc3 ns MCLKOUT jitter

XTALI Master Clock Source 80 ps

tdMI - MO Delay time, MCLKIN rising edge to MCLKOUT rising edge

MCLKOUT = MCLKIN

See note 4 - - 17.0 ns

NOTE 1: tcyc1 = 1 / fXTALI NOTE 2: tcyc2= 1 / fMCLKIN NOTE 3: tcyc3= 1 / fMCLKOUT NOTE 4: When MCLKOUT is derived from MCLKIN, MCLKOUT jitter = MCLKIN jitter. MCLKOUT has the same duty cycle

as MCLKIN when MCLKOUT = MCLKIN NOTE 5 When operating as clock slave – MCLK should be 512 Fs when the auto detect function is not enabled or disabled.

Figure 13-1. Master Clock Signals Timing Waveforms

twMCLKI

trMCLKO tfMCLKO twMCLKO

XTALI

tcyc1

tcyc2

tcyc3

MCLKOUT

MCLKIN

tdMI - MO

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13.7.2 Power Up sequence

PARAMETER MIN TYP MAX UNITS Reset hold time against DVDD & AVDD_OSC powered up at 3.0V

T1 5 - - ms

Reset hold time against AVDD(Excepted VDD_OSC) & DVDD_PWM powered up at 3.0V

T2 1 ms

Figure 13-2. Power on sequence (Minimum Requirement)

T1

T2

RESETz

DVDD

AVDD_OSC

AVDD(Excepted_VDD- OSC)

DVDD_PWM

OSC start up and Digital block is reset by RESETz input in this period

3.0V

3.0V

3.0V

3.0V

AVDD&DVDD_PWM sett ling t ime in the device

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PARAMETER MIN TYP MAX UNITS AVDD(Excepted for AVDD-OSC) and DVDD_PWM power up start time against DVDD & AVDD_OSC powered up at 3.0V

T3 5 - - ms

Reset hold time against AVDD(Excepted VDD_OSC) & DVDD_PWM powered up at 3.0V ( AVDD(Excepted VDD_OSC) & DVDD_PWM settling time in the device)

T2 1 ms

Figure 13-3. Power on sequence (Recommended)

This power up sequence is recommended not to make noise on PWM out and Line out

in the power up sequence.

Please keep 5ms before power up start of AVDD(Except for OSC_VDD) and DVDD PWM

from DVDD and AVDD_OSC powered up at 3.0V.

T3

T2

RESETz

DVDD

AVDD_OSC

AVDD(Excepted_VDD- OSC)

DVDD_PWM

OSC start up and Digital block is reset by RESETz input in this period

3.0V

3.0V

3.0V

3.0V

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13.7.3 Reset Timing Control Signal Parameters over Recommended Operating Conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNITS

TrDMSTATE Time to outputs inactive - 100 us twRESET Pulse duration, /RESET Active 200 - ns TrEMSTATE Time to enable I2C

GPIO1=pull-up No EEPROM

- 100 ms

/RESET

Outputs Inactive

trdmstate = ~100 usec

tremstate

Enable I2CStart system

Start of Boot Sequence

twRESET

Figure 13-4. Reset Timing

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13.7.4 Serial Audio Port Slave Mode Signals Over Recommended Operating Conditions (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

fLRCLK Frequency, LRCLKIN (FS) 32 - 48 KHz twSCLKIN Pulse duration, SCLKIN high See note 1 0.4 tcyc - 0.6 tcyc ns fSCLKIN Frequency, SCLKIN - 64FS - MHz tcyc Cycle time, SCLKIN See note 1 - - 1/64FS ns tpd1 Propagation delay, SCLKIN falling edge to

SDOUT - - 16 ns

tsu1 Setup time, LRCLK to SCLKIN rising edge 10 - - ns th1 Hold time, LRCLK from SCLKIN rising edge 5 - - ns tsu2 Setup time, SDIN to SCLKIN rising edge 10 - - ns

th2 Hold time, SDIN from SCLKIN rising edge 5 - - ns tpd2 Propagation delay,

SCLKIN falling edge to SCLKOUT falling edge

SCLKOUT = SCLKIN

- - 15 ns

NOTE 1: tcyc = 1 / fSCLKIN

Figure 13-5. Serial Audio Port Slave Mode Timing Waveforms

SCLKIN

LRCLKIN (input)

SDOUT1 SDOUT2

SDIN1 SDIN2 SDIN3

tsu1

tpd1

tsu2 th2

th1

SCLKOUT

tpd2

twSCLKIN

tcyc

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13.7.5 Serial Audio Port Master Mode Signals Over Recommended Operating Conditions (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

fLRCLK Frequency LRCLKOUT - 48 - KHz trLRCLK Rise Time, LRCLKOUT CL = 30 pF

- - 12 ns

tfLRCLK Fall Time, LRCLKOUT CL = 30 pF

- - 12 ns

fSCLKOUT Frequency, SCLKOUT See note 1 - 64Fs - MHz trSCLKOUT Rise Time, SCLKOUT CL = 30 pF

- - 12 ns

tfSCLKOUT Fall Time, SCLKOUT CL = 30 pF

- - 12 ns

tpd1,SCLKOUT Propagation delay, SCLKOUT falling edge to LRCLKOUT edge

- - 5 ns

tpd2 Propagation delay, SCLKOUT falling edge to SDOUT1-2

- - 5 ns

tsu Setup time, SDIN to SCLKOUT rising edge 25 - - ns th Hold time, SDIN from SCLKOUT rising edge 30 - - ns

NOTE 1: Typical duty cycle is 50/50.

Figure 13-6. TAS3308 Serial Audio Port Master Mode Timing Waveforms

tsu

tpd1,SCLKOUT trSCLKOUT

tfLRCLK, trLRCLK

th

LRCLKOUT

SDOUT1 SDOUT2

tpd2

SDIN1 SDIN2 SDIN3

SCLKOUT

tfSCLKOUT

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13.7.6 SPDIF Interface Signals Timing Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Fs Encoded data sampling rate 32 - 48 kHz Rspdif SPDIF signal bitrate - 128 Fs - MHz UI Unit Interval - 1/Rspdif - ns TLO/THI LOW/HIGH periods 1 UI - 3 UI ns Tjitter Intrinsic Jitter - - 0.05 UI

13.8 MCLK and serial input operation conditions (Slave mode autodetect enabled) Parameter Conditions Min Typ Max Units Input SAP clocks LRCLK_IN frequency range (48 kHz) 45.6 50.4 kHz

LRCLK_IN frequency range (44.1 kHz) 41.9 46.3 kHz

LRCLK_IN frequency range (32 kHz) 30.4 33.6 kHz

Frequency Drift 1% (*) %/mS

SCLK 64*Fs 64*Fs kHz MCLK MCLK Frequency 25.7 MHz MCLK duty cycle (high period) 40 60 % MCLK to LRCLK ratios 256,384 or 512 X MCLK divided by 256/384/512 to LRCLK absolute phase variation π/64 Radians

(*) or limited by the APLL filter response.

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13.8.1 I2C Interface and I/O Characteristics of the SDA and SCL bus lines for Standard and Fast Mode I2C -bus devices

PHILIPS SPEC (Ver 2.1) STANDARD-MODE FAST-MODE PARAMETER SYMBOL UNIT MIN MAX MIN MAX

1 SCL clock frequency fSCL kHz 0 100 0 400(1)

2 Hold time (repeated) START condition. After this period, the first clock pulse is generated.

tHD;STA µs 4.0 - 0.6 -

3 LOW period of the SCL clock tLOW µs 4.7 - 1.3 -

4 HIGH period of the SCL clock tHIGH µs 4.0 - 0.6 -

5 Set-up time for a repeated START condition. tSU;STA µs 4.7 - 0.6 -

6 Data set-up time tSU;DAT ns 250 - 100(2) -

7 Rise time of both SDA and SCL signals (10) tr ns - 1000 0 300 8 Fall time of both SDA and SCL signals (10) tf ns - 300 0 300

9 Set-up time for STOP condition tSU;STO µs 4.0 - 0.6 -

10 Bus free time between a STOP and START condition tBUF µs 4.7 - 1.3 -

11 Capacitive load for each bus line Cb pF - 400 - 400

12 Noise margin at the LOW level for each connected device (including hysteresis)

VnL V 0.1VDD - 0.1VDD -

13 Noise margin at the HIGH level for each connected device (including hysteresis)

VnH V 0.2VDD - 0.2VDD -

14 Hysteresis of Schmitt trigger inputs: Vhys V n/a n/a 0 - 15 Pulse width of spikes which must be suppressed by the input filter tSP ns n/a n/a 0 50 16 Input current each I/O pin with an input voltage between 0.1 VDD and 0.9

VDD max Ii µA -1 1 -1(4) 1(4)

17 Capacitance for each I/O pin Ci pF - 10 - 10

18 Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400 pF (11)

tof ns - 250(5) 3 250(5)

Notes:

1. In Master mode the Maximum I2C clock rate is 375Khz.

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2. A Fast-mode I2C -bus device can be used in a Standard-mode I2C -bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

3. Cb = total capacitance of one bus line in pF. 4. I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off. 5. The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection

resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. 6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the

falling edge of SCL. 7. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 8. All values referred to VIHmin and VILmax levels. 9. Toversamp is the period of the Oversample Clock provided to the I2C Master Slave Controller. This clock is dependent on the Microprocessor clock

setting and the value set for the variable N in sub-address x01. 10. Specified tr, tf here are the allowable tr, tf time for I2C interface input of this device. 11. This tf time is the output buffer's characteristics.

Figure 13-7. I2C SCL and SDA Timing Waveforms

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13.9 Terminal Assignments The device will be available in a 100 pin TQFP package.

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Figure 39. Pinout

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13.10 Pin Description

Terminal Terminal Name I/O Type Description

1 DVDD_PWM2 P 3.3 V Digital Power Supply Pin for PWM2.

2 PWM2_RD DO C FS PWM out channel 2 right delayed output. This buffer is failsafe, no damage occurs to the device if the supply for the PWM section is not valid during power on for the rest of the device.

3 PWM2_RI DO C FS PWM out channel 2 right immediate output. This buffer is failsafe. 4 PWM3_LD DO C FS PWM out channel 3 left delayed output. This buffer is failsafe. 5 PWM3_LI DO C FS PWM out channel 3 left immediate output. This buffer is failsafe. 6 DVSS_PWM3 P Digital ground for PWM3 outputs

7 DVDD_PWM3 P 3.3 V Digital Power Supply Pin for PWM3. Refer to Figure 15.1 Analogue outputs.

8 PWM3_RD DO C FS PWM out channel 3 right delayed output. This buffer is failsafe. 9 PWM3_RI DO C FS PWM out channel 3 right immediate output. This buffer is failsafe. 10 VALID/SYNC DO TTL PWM valid signal or 256 kHz synchronization signal to PSU or PWM 11 DVDD2 P 3.3 V Digital Power Supply Pin 12 DVSS2 P Digital Ground Pin

13 /VREG_EN DI TTL Voltage regulator Enable. When enabled (LOW) this input enables the power supply regulators.

14 STEST DI TTL (Pull Down) Test Pin Used to Reconfigure Pins for testing

15 MCLKOUT DO TTL Output clock associated with the serial data outputs (SDOUT/SPDIF) 16 LRCLKOUT DO TTL Left / Right clock output associated with SDOUT 17 SCLKOUT DO TTL Serial Audio Data Clock (Shift Clock) output associated with SDOUT 18 SDOUT1 DO TTL Serial Audio Data 1 output

19 SDOUT2/ SPDIF_OUT DO TTL

Serial Audio Data 2 or SPDIF output. The SPDIF output can be selected from DAP or SPDIF_IN. When selecting SPDIF_IN, MCLK_OUT is not synchronized to the SPDIF_OUT.

20 SPDIF_IN DI TTL SPDIF input multiplexed to output SPDIF pin

21 SDIN3 DI TTL Serial Audio Data 3 Input is one of the serial data input ports. Associated with SCLKIN and LRCLKIN

22 SDIN2 DI TTL Serial Audio Data 2 Input is one of the serial data input ports. Associated with SCLKIN and LRCLKIN

23 SDIN1 DI TTL Serial Audio Data 1 Input is one of the serial data input ports. Associated with SCLKIN and LRCLKIN

24 LRCLKIN DI TTL Serial Audio Data Left / Right Clock (sampling rate clock) for ASRC

25 SCLKIN DI TTL Serial Audio Data Clock (Shift Clock) is the serial audio port (SAP) input data bit clock

26 MCLKIN DI TTL MCLK is a 3.3 V clock master clock input. The input frequency of this clock is 256/384/512 Fs

27 DVSS_DPLL P Digital Ground Pin for Digital PLL

28 VR_DIG2 P A pin-out of the internally regulated 1.8 V power. Connect a 4.7-uf low ESR capacitor between this terminal and DVSS. This terminal must not be used to power external devices

29 DVDD3 P 3.3 V Digital Power Supply Pin 30 DVSS3 P Digital Ground Pin

31 I2C_SDA2 DIO C FS Master I2C Serial Control Data Interface Input / Output. This buffer is failsafe; The device is not damaged if this line is driven externally before DVDD is valid.

32 I2C_SCL2 DIO C FS Master I2C Serial Control Clock Input / Output. This buffer is failsafe

33 I2C_SDA1 DIO C FS Slave I2C Serial Control Data Interface Input / Output. This buffer is failsafe

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34 I2C_SCL1 DIO C FS Slave I2C Serial Control Clock Input / Output. This buffer is failsafe 35 CS DI TTL Chip Select, this input defines the LSB in the I2C (1) address. 36 GPIO1 DIO TTL General Purpose I/O 1 37 GPIO2 DIO TTL General Purpose I/O 2

38 /MUTE DI TTL (Pull-Up)

As an input - performs a Mute of outputs, active LOW (Muted signal = a logic LOW, normal operation = a logic HIGH)

39 /RESET DI TTL (Pull-Up)

System Reset Input, active LOW. /RESET is an asynchronous control signal that restores the device default conditions

40 DVSS4 P Digital Ground Pin

41 VR_DIG3 P A pin-out of the internally regulated 1.8 V power. Connect a 4.7-uf low ESR capacitor between this terminal and DVSS. This terminal must not be used to power external devices

42 DVDD4 P 3.3 V Digital Power Supply Pin 43 LINEIN1L AI Analog input #1 Left 44 LINEIN1R AI Analog input #1 Right 45 AVSS_LI1 P Analog Supply Ground 46 LINEIN2L AI Analog input #2 Left 47 LINEIN2R AI Analog input #2 Right 48 AVDD_LI1 P 3.3V Analog Power Supply 49 LINEIN3L AI Analog input #3 Left 50 LINEIN3R AI Analog input #3 Right 51 LINEIN4L AI Analog input #4 Left 52 LINEIN4R AI Analog input #4 Right 53 AVDD_LI2 P 3.3V Analog Power Supply 54 LINEIN5L AI Analog input #5 Left 55 LINEIN5R AI Analog input #5 Right 56 AVSS_LI2 P Analog Supply Ground 57 LINEIN6L AI Analog input #6 Left 58 LINEIN6R AI Analog input #6 Right 59 AVSS_ADC/REF P Analog Supply Ground 60 LINEIN7L AI Analog input #7 Left 61 LINEIN7R AI Analog input #7 Right 62 AVDD_ADC P 3.3V Analog Power Supply 63 LINEIN8L AI Analog input #8 Left 64 LINEIN8R AI Analog input #8 Right 65 AVDD_LI3 P 3.3V Analog Power Supply 66 LINEIN9L AI Analog input #9 Left 67 LINEIN9R AI Analog input #9 Right 68 AVSS_LI3 P Analog Supply Ground 69 LINEIN10L AI Analog input #10 Left 70 LINEIN10R AI Analog input #10 Right 71 BIAS_REF AO Bias Output. Tie this pin to ground via e external 24 k Ohm resistor 5%. 72 BG_REF AO Band Gap Output; should have a 1 uF low ESR to analog ground. 73 V1P5_REF AO Common Mode Output; should have a 1 uF low ESR to analog ground. 74 AVDD_REF P 3.3V Analog Power Supply 75 AVDD_LO P 3.3V Analog Power Supply 76 LINEOUT1L AO Analog Line Output #1 Left Channel 77 LINEOUT1R AO Analog Line Output #1 Right Channel 78 AVSS_LO P Analog Supply Ground 79 AVDD_PLL P Analog Power Supply for PLL 80 PLL_FLTP A PLL filter 81 PLL_FLTM A PLL filter 82 AVSS_PLL P Analog Supply Ground for PLL

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83 VR_ANA2 P

A pin-out of the internally regulated 1.8 V power used by Analog, such as Oscillator, Clock divider and Analog clock. Connect a 4.7-uf low ESR capacitor between this terminal and DVSS. This terminal must not be used to power external devices

84 AVDD_OSC P 3.3V Analog Power Supply for Oscillator, Clock divider and Analog clock.

85 XTAL_IN DI Crystal Input (24.576MHz) 86 XTAL_OUT DO Crystal Output 87 AVSS_OSC P Analog Supply Ground

88 VR_ANA P A pin-out of the internally regulated 1.8 V power used by Analog. Connect a 4.7-uf low ESR capacitor between this terminal and DVSS. This terminal must not be used to power external devices

89 DVDD1 P 3.3 V Digital and DPLL Power Supply Pin 90 DVSS1 P DPLL Ground Pin

91 VR_DIG1 P A pin-out of the internally regulated 1.8 V power used by digital core. Connect a 4.7-uf low ESR capacitor between this terminal and DVSS. This terminal must not be used to power external devices

92 PWM1_LD DO C FS PWM out channel 1 left delayed output. This buffer is failsafe. 93 PWM1_LI DO C FS PWM out channel 1 left immediate output. This buffer is failsafe. 94 DVSS_PWM1 P Digital ground for PWM1 95 DVDD_PWM1 P 3.3 V Digital Power Supply Pin for PWM1. 96 PWM1_RD DO C FS PWM out channel 1 right delayed output. This buffer is failsafe.

97 PWM1_RI DO C FS PWM out channel 1 right immediate output. This buffer is failsafe.

98 PWM2_LD DO C FS PWM out channel 2 left delayed output. This buffer is failsafe. 99 PWM2_LI DO C FS PWM out channel 2 left immediate output. This buffer is failsafe.

100 DVSS_PWM2 P Digital ground for PWM2 P – Power DI – Digital Input DO – Digital Output DIO – Digital Input / Output AI – Analog Input AO - Analog Output C FS - CMOS Failsafe All pull-ups are 20-uA weak pull-ups, and all pull-downs are 20-uA weak pull-downs (166 kΩ) . The pull-ups and pull-downs are included to ensure proper input logic levels if the terminals are left unconnected (pull-ups ® logic 1 input; pull-downs ® logic 0 input). Devices that drive inputs with pull-ups must be able to sink 20 uA while maintaining a logic-0 drive level. Devices that drive inputs with pull-downs must be able to source 20 uA while maintaining a logic-1 drive level.

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14. I2C Register Map

Sub address

Register Number of Byte

Contents Default Value

0x00 SAP/Clock setting 4 See section 14.1 0x01, 0x01, 0x22, 0x22 0x01 I2C M and N (Reserved) 4 u(31:24), u(23:16), u(15:8), u(7)M(6:3)N(2:0) 0x00, 0x00, 0x00, 0x40 0x02 Status Register 8 See section 14.2 0x00, 0x00, 0x00, 0x00

0x00, 0x00, 0x00, 0x00 0x03 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x04 I2C memory load control register 8 See section 14.3 0x00, 0x00, 0x00, 0x00

0x00, 0x00, 0x00, 0x00 0x05 I2C memory load data register 8 See section 14.3 0x00, 0x00, 0x00, 0x00

0x00, 0x00, 0x00, 0x00 0x06 Peek/Poke memory select and address 4 See section 14.4 0x00, 0x00, 0x00, 0x00 0x07 Peek/Poke data 8 See section 14.4 0x00, 0x00, 0x00, 0x00

0x00, 0x00, 0x00, 0x00 0x08 Silicon version 4 ver(31:24), ver(23:16), ver(15:8), ver(7:0) 0x00, 0x00, 0x00, 0x01 0x09 Mute control 4 See section 14.5 0x00, 0x00, 0x00, 0x00 0x0a Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0b Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0c GPIO control 4 See section 14.6 0x00, 0x00, 0x00, 0x00 0x0d Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0e Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0f Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x10 Power Down control 4 See section 14.7 0x00, 0x00, 0x00, 0x00 0x11 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x12 A-MUX control 4 See section 14.8 0x00, 0x00, 0x00, 0x00 0x13 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x14 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x15 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x16 SPDIF control 4 See section 14.9 0x20 0x42, 0x54, 0x00 0x17 Fast Volume Ramp control 4 See section 14.10 0x00, 0x00, 0x08, 0x78 0x18 PWM control 4 See section 14.11 0x92, 0x92, 0x92, 0x08 0x19 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x1a PWM channel delay, modulation limit, and

offset 8 See section 14.12 0x00, 0x00, 0x08, 0x28

0x10, 0x30, 0x00, 0x20 0x1b Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00

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0x1c Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x1d PWM Duty50 Mode control 4 See section 14.13 0x00, 0x00, 0x00, 0x00 0x1e DAP Program Start Address 4 See section 14.14 0x00, 0x00, 0x0B, 0x90 0x1f I2C Master Load 4 See section 14.15 0x00, 0x00, 0x00, 0x00 0x20 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x21 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x22 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x23 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x24 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x25 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x26 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x27 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x28 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x29 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2a Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2b Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2c Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2d Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2e Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2f Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x30 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x31 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00

… … 0xfe Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0xff Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00

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14.1 SAP / Clock Setting (0x00) Table 14-1 SAP/Clock Setting

D31 D30 D29 D28 D27 D26 D25 D24 Function0 0 0 0 0 0 reserved

ATDEnable Clock Auto Detect = 1 (0 = disable, 1 = enable)(ONLY ENABLED IN SLAVE MODE)

CMS Clock Master/Slave Select (0 = slave, 1 = master)

D23 D22 D21 D20 D19 D18 D17 D16 Function0 0 0 0 0 0 0 reserved

ON SAP Output Normalization(0 = disable, 1 = enable)

D15 D14 D13 D12 D11 D10 D09 D08 Function0 0 reserved

OW1 OW0 Output SAP Word Size0 0 reserved

IW1 IW0 Input SAP Word SizeD07 D06 D05 D04 D03 D02 D01 D00 Function

0 0 reservedOM1 OM0 Output SAP Mode

0 0 reservedIM1 IM0 Input SAP Mode

14.1.1 Audio Data Word Size Bits 9-8 (IW1 and IW0) define the data word size for the input SAP. Bits 13-12 (OW1 and OW0) define the data word size for the output SAP.

IW1/OW1 IW0/OW0 Description 0 0 16-bit 0 1 20-bit 1 0 24-bit 1 1 reserved

14.1.2 Input and Output Data Format Bits 1-0 (IM1 and IM0) define the input data format. Bits 5-4 ((OM1 and OM0) define the output data format.

IM1/OM1 IM0/OM0 Description 0 0 Left Justified 0 1 Right Justified 1 0 I2S 1 1 reserved

14.1.3 SAP Output Normalization This function enables and disables SAP output normalization. OUTPUT NORMALIZATION SHOULD BE DISABLED ON NON-I2S TO I2S, AND I2S TO NON-I2S IN MASTER MODE.

Input mode/Output Mode Output Normalization

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Enabled Disabled Non-I2S/Non-I2S Non-I2S/I2S × I2S/Non-I2S × I2S/I2S

Table 14.2. Validity of Output Normalization in Master Mode

Output Normalization Input mode/Output Mode Enabled Disabled Non-I2S/Non-I2S Non-I2S/I2S I2S/Non-I2S I2S/I2S

Table 14.3. Validity of Output Normalization in Slave Mode

14.1.4 Clock mode with auto detection Bit25 ATD bit was defined as auto detection enable control in slave mode. Slave mode with auto detect disabled is not allowed. Bits 25-24 (ATD and CMS) define the clock mode. Host can specify only master mode or slave mode as the Table 114-4.

Table 114-4 Clock mode

ATD CMS Description 0 0 Reserved 0 1 Master mode (READ/WRITE) 1 0 Slave mode (READ/WRITE) 1 1 Reserved

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14.2 Status Register (0x02) Status register provide memory load information. There are two ways to load program, coefficient, or data which are “load from EEPROM with I2C master mode” and “load from HOST with I2C slave mode”. When a memory load error for a particular memory occurs, the memory load error bit for that memory is set to 1. When a memory load is successful for a particular memory the memory load error bit for that memory is set to 0. Host needs to check this load status after memory load. Host can clear all load error status to write 0 to D39-D32 of this register.

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Table 14-5 status register (0x02)

D63 D62 D61 D60 D59 D58 D57 D56 Function0 0 0 0 0 0 0 0 reserved

D55 D54 D53 D52 D51 D50 D49 D48 Function0 0 0 0 0 0 0 0 reserved

D47 D46 D45 D44 D43 D42 D41 D40 Function0 0 0 0 0 0 0 -

D40 D39 D38 D37 D36 D35 D34 D33 D32 Functionx x x x x x x x 1 Micro program memory load error

x x x x x x x 1 x Micro external memory load error

x x x x x x 1 x x DAP program memory load error

x x x x x 1 x x x DAP coefficient memory load error

x x x x 1 x x x x DAP data memory load error

x x x 1 x x x x x reserved

x x 1 x x x x x x reserved

x 1 x x x x x x x Invalid memory select

1 x x x x x x x x End of load header error

1 1 1 1 1 1 1 1 1 No eeprom

0 0 0 0 0 0 0 0 0 No error

D31 D30 D29 D28 D27 D26 D25 D24 Function0 0 0 0 0 0 0 0 reserved

D23 D22 D21 D20 D19 D18 D17 D16 Function0 0 0 reserved

VLD PWM Valid flag (Read Only)0: invalid, 1: valid

CLKE Clock Error (Only Slave Mode)0: no error, 1: error

APLL APLL Lock0: un-lock, 1: lock

FS1 FS0 Current FS Rate

D15 D14 D13 D12 D11 D10 D09 D08 Function0 0 0 0 0 0 0 0 reserved

D07 D06 D05 D04 D03 D02 D01 D00 Function0 reserved

0 reserved

0 reserved

S2M Clock slave mode to master mode busy

0 reserved

0 reserved

BUSE I2C Bus Error (Cleared by write "0")0: no error, 1: bus error happened

0 reserved

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14.2.1 Memory Load Error Bits 40 to 32 define the memory load error status on EEPROM download and Slave download. The load error status is kept until cleared by host uC except "invalid memory select" status which is cleared by 8051 automatically when next memory block load start.

14.2.2 I2C Bus Error If I2C Bus error happened, this flag will be set. Only host uC can clear this flag by writing “0” to this bit.

14.2.3 Clock slave mode to master mode busy This busy flag indicate during clock slave mode to master mode transition. In this transition, micro mute DSPE fast volume first to avoid noise, change slave to master mode, and un-mute after APLL stable.

14.2.4 Current Fs Rate Fs[1] Fs[0] Description

0 0 48kHz 0 1 44.1kHz 1 0 32kHz 1 1 reserved

14.2.5 APLL Lock Indicate APLL is in lock state.

14.2.6 Clock Error Indicate LRCLKI, SCLKI, or MCLKI are invalid in slave mode.

14.2.7 PWM Valid Indicate PWM valid pin condition. PWM start cause valid = H, and PWM stop cause valid = L.

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14.3 Load Memory Control and Data Register (0x04, 0x05) Table 14-6 Load Memory Control Register (0x04)

Byte Data Block Format Size Notes 1 - 2 Checksum Code 2 Bytes Checksum of bytes 2 through N+8, If this is a

termination header, this value is 00 00. 3 Memory to be loaded 1 Byte 0 Micro Program memory

1 Micro External Data memory 2 DAP Program memory 3 DAP Coefficient memory 4 DAP Data Memory 5 Reserved 6 Reserved 7-15 Reserved

4 Unused 1 Byte Reserved 6 - 7 Starting TAS3308

Memory Address 2 Bytes If this is a termination header, this value is 00 00

7 - 8 Number of Data Bytes to be Transferred

2 Bytes If this is a termination header, this value is 00 00

Table 14-7 Load memory Data Register (0x05)

Byte 8 Bit Data 28 bit data 48 bit data 55 bit data 1 Datum 1 D7 – D0 XXXX D27 – D24 2 Datum 2 D7 – D0 D23 – D16 X D54 – D48 3 Datum 3 D7 – D0 D15 – D8 D47 – D40 D47 – D40 4 Datum 4 D7 – D0 D7 – D0 D39 – D32 D39 – D32 5 Datum 5 D7 – D0 XXXX D27 – D24 D31 – D24 D31 – D24 6 Datum 6 D7 – D0 D23 – D16 D23 – D16 D23 – D16 7 Datum 7 D7 – D0 D15 – D8 D15 – D8 D15 – D8 8 Datum 8 D7 – D0 D7 – D0 D7 – D0 D7 – D0

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14.4 PEEK and POKE (0x06, 0x07) Registers 0x06 (Table 14-8) and 0x07 (Table 14-9) allow the user to access the internal resources of TAS3308.

Table 14-8 Memory Select and address (0x06)

D31 D30 D29 D28 D27 D26 D25 D24 Function0 0 0 0 0 0 0 0 unused

D23 D22 D21 D20 D19 D18 D17 D16 Function0 0 0 0 0 0 0 1 DAP coefficient memory0 0 0 0 0 0 1 0 DAP data memory0 0 0 0 0 0 1 1 Delay memory0 0 0 0 0 1 0 0 Micro internal data memory0 0 0 0 0 1 0 1 Micro external data memory0 0 0 0 0 1 1 0 SFR0 0 0 0 0 1 1 1 Micro program memory0 0 0 0 1 0 0 0 DAP program memory0 0 0 0 1 0 0 1 Reserved0 0 0 0 1 0 1 0 Reserved

D15 D14 D13 D12 D11 D10 D09 D08 FunctionA15 A14 A13 A12 A11 A10 A9 A8 Memory address (MS Byte)D07 D06 D05 D04 D03 D02 D01 D00 FunctionA7 A6 A5 A4 A3 A2 A1 A0 Memory address (LS Byte)

Table 14-9 Data Register (0x07)

D63 D62 D61 D60 D59 D58 D57 D56 FunctionD63 D62 D61 D60 D59 D58 D57 D56 Data to be written or readD55 D54 D53 D52 D51 D50 D49 D48 FunctionD55 D54 D53 D52 D51 D50 D49 D48 Data to be written or readD47 D46 D45 D44 D43 D42 D41 D40 FunctionD47 D46 D45 D44 D43 D42 D41 D40 Data to be written or readD39 D38 D37 D36 D35 D34 D33 D32 FunctionD39 D38 D37 D36 D35 D34 D33 D32 Data to be written or readD31 D30 D29 D28 D27 D26 D25 D24 FunctionD31 D30 D29 D28 D27 D26 D25 D24 Data to be written or readD23 D22 D21 D20 D19 D18 D17 D16 FunctionD23 D22 D21 D20 D19 D18 D17 D16 Data to be written or readD15 D14 D13 D12 D11 D10 D09 D08 FunctionD15 D14 D13 D12 D11 D10 D09 D08 Data to be written or readD07 D06 D05 D04 D03 D02 D01 D00 FunctionD07 D06 D05 D04 D03 D02 D01 D00 Data to be written or read

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14.5 Mute Control (0x09) D31 D30 D29 D28 D27 D26 D25 D24 Function

0 0 0 0 0 0 0 0 unusedD23 D22 D21 D20 D19 D18 D17 D16 Function

0 0 0 0 0 0 0 0 unusedD15 D14 D13 D12 D11 D10 D09 D08 Function

0 0 unusedAMX1 AMX1 AMUXO1 (LINEOUT1)

SD2 SD2 SDOUT2/SPDIFOUTSD1 SD1 SDOUT1

D07 D06 D05 D04 D03 D02 D01 D00 FunctionPWM1 PWM1 PWM1

PWM2 PWM2 PWM2PWM3 PWM3 PWM3

DIT DIT DIT (BiPhase)

mute[1] mute[0] Description 0 0 HW Mute control * 1 Force Mute OFF (Signal) 1 0 Force Mute ON (No Signal)

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14.6 GPIO Control (0x0C) D31 D30 D29 D28 D27 D26 D25 D24 Function

WDE watchdog timer(0: enable, 1: disable)

0 0 0 unusedIO2 GPIO2 Input or Output Value

IO1 GPIO1 Input or Output Value

DIR2 GPIO2 Direction(0 : output, 1 : input)

DIR1 GPIO1 Direction(0 : output, 1 : input)

D23 D22 D21 D20 D19 D18 D17 D16 Functionx x x x x x x x GPIOMICROCOUNT MS Byte

D15 D14 D13 D12 D11 D10 D09 D08 Functionx x x x x x x x GPIOMICROCOUNT LS Byte

D07 D06 D05 D04 D03 D02 D01 D00 Function0 0 0 0 0 0 0 0 unused

GPIOMICROCOUNT sets the number of micro clock cycles for Timer 0 interrupt. In Timer 0 interrupt service routine, watchdog timer is reset if it is enabled. The default value for this counter is 0x5280 which correspond to a period 1.25 msec.

14.7 Power Down Control (0x10) D31 D30 D29 D28 D27 D26 D25 D24 Function

0 0 0 0 0 0 0 0 unusedD23 D22 D21 D20 D19 D18 D17 D16 Function

0 0 0 0 0 0 0 0 unusedD15 D14 D13 D12 D11 D10 D09 D08 Function

0 0 0 0 0 0 0 0 unusedD07 D06 D05 D04 D03 D02 D01 D00 FunctionDIT SPDIF Enable (release reset)

PWM PWM Start/Stop0 0 0 0 0 0 unused

Description 0 Stop, Disable 1 Start, Enable

Analog components are always power up which is done at the initialization routine. TAS3308 does not have individual power control like TAS3208. NOTE: PWM Start control should be done after completion for PWM control register (0x18), PWM Channel Delay, Modulation limit and offset (0x1A), and PWM Duty 50 mode control (0x1D). If these registers (0x18, 0x1A, and 0x1D) update is needed during PWM running (after start), PWM Stop control is required.

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14.8 A-MUX Control (0x12) D31 D30 D29 D28 D27 D26 D25 D24 Function

0 0 0 0 0 0 0 0 unusedD23 D22 D21 D20 D19 D18 D17 D16 Function

0 0 0 0 0 0 0 0 unusedD15 D14 D13 D12 D11 D10 D09 D08 Function

* * * * 1 1 1 1 reserved* * * * 1 1 1 0 reserved* * * * 1 1 0 1 reserved* * * * 1 1 0 0 reserved* * * * 1 0 1 1 reserved

sel1 sel0 * * 1 0 1 0 AMUX1 IN 10sel1 sel0 * * 1 0 0 1 AMUX1 IN 9sel1 sel0 * * 1 0 0 0 AMUX1 IN 8sel1 sel0 * * 0 1 1 1 AMUX1 IN 7sel1 sel0 * * 0 1 1 0 AMUX1 IN 6sel1 sel0 * * 0 1 0 1 AMUX1 IN 5sel1 sel0 * * 0 1 0 0 AMUX1 IN 4sel1 sel0 * * 0 0 1 1 AMUX1 IN 3sel1 sel0 * * 0 0 1 0 AMUX1 IN 2sel1 sel0 * * 0 0 0 1 AMUX1 IN 1

* * 0 0 0 0 0 0 No selectD07 D06 D05 D04 D03 D02 D01 D00 Function

* * * * 1 1 1 1 reserved* * * * 1 1 1 0 reserved* * * * 1 1 0 1 reserved* * * * 1 1 0 0 reserved* * * * 1 0 1 1 reserved* * * * 1 0 1 0 ADC IN 10* * * * 1 0 0 1 ADC IN 9* * * * 1 0 0 0 ADC IN 8* * * * 0 1 1 1 ADC IN 7* * * * 0 1 1 0 ADC IN 6* * * * 0 1 0 1 ADC IN 5* * * * 0 1 0 0 ADC IN 4* * * * 0 0 1 1 ADC IN 3* * * * 0 0 1 0 ADC IN 2* * * * 0 0 0 1 ADC IN 10 0 0 0 0 0 0 0 No select

sel1 sel0 Description

0 * L/R (normal) 1 0 L/L 1 1 R/R

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14.9 SPDIF Control (0x16) D31 D30 D29 D28 D27 D26 D25 D24 Function

CPCopyright flag0: copy prohibit1: permit

EMPPre-emphasis flag0: No pre-emphasis1: 50/15 us pre-emphasis

b28 b29

WL3 WL2 WL1 WL0 Sample word lengthDefault "0000" (24bits)

D23 D22 D21 D20 D19 D18 D17 D16 Function

b24 b25

VLLeft channel validity flag0: valid1: invalid

VRRight channel validity flag0: valid1: invalid

b19 b18 b17 b16

D15 D14 D13 D12 D11 D10 D09 D08 Function

b8 b9 b10 b11 b12 b13 b14

L

Generation statusIEC60958-3 bit150: Generation 1 or Higher1: Original

D07 D06 D05 D04 D03 D02 D01 D00 Function0 0 0 0 0 0 unused

MUX1 MUX0

SPDIF MUX 3:100 : SDOUT201 : SPDIF Tx1* : SPDIF In

CATEGORYchannel status bit 8 - 14

Category code IEC60958-3 bit 8 - 14Default "0101010" (Digital Sound Processor)

SRCNUMchannel status bit16-19

Source numberIEC60958-3 bit16-19Default "0010" (2)

SRchannel

Sampling rateIEC60958-3 bit 24-25Default "01" (48kHz)

CLKACchannel

Clock accuracyIEC60958-3 bit 28-29Default "10" (Level I, 50ppm)

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SR Sampling Rate (“samp” input) 00 44.1 kHz 01 48 kHz 10 Reserved 11 32 kHz

SRCNUM Source Channel Number (“srcnum” input)

0000 Not indicated 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 others Reserved

CLKAC Clock Accuracy (“clkac” input)

00 Level II, 1000ppm 01 Level III, variable pitch shifted 10 Level I, 50ppm (default) 11 Reserved

WORDLEN Sample bit size (“wordlen” input)

0000 24 bits 0001 23 bits 0010 22 bits 0011 21 bits 0100 20 bits 0101 19 bits 0110 18 bits 0111 17 bits 1000 16 bits others Reserved

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14.10 Fast Volume Ramp Control (0x17) D31 D30 D29 D28 D27 D26 D25 D24 Function

0 0 0 0 0 0 0 0 unusedD23 D22 D21 D20 D19 D18 D17 D16 Function

0 0 0 0 0 0 0 0 reservedD15 D14 D13 D12 D11 D10 D09 D08 Function

Fast volume ramp step size0 0 0 0 1 0 0 0 default (0x08)

D07 D06 D05 D04 D03 D02 D01 D00 FunctionMaximum DSPE volume value

0 1 1 1 1 0 0 0 default (0x78)

Volume ramp step size

Maximum DSPE volume

14.10.1 Fast volume ramp period The DSPE volume ramp down/up period is calculated as MAX_DSPE_VOL / RAMP_STEP_SIZE.

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14.11 PWM Control (0x18) D31 D30 D29 D28 D27 D26 D25 D24 Function

EN PWM3 Enable Control0: disable, 1: enable

DISBPWM3D Disable Control0: PWM3D enable1: PWM3D disable

INVMInvert PWM3D output0: not inverted1: output inverted

MOD1 MOD0 PWM3 Modulation SelectDefault "10" (Comb-AD)

ADLY2 ADLY1 ADLY0 PWM3 ABD DelayDefault "010" (4)

D23 D22 D21 D20 D19 D18 D17 D16 Function

EN PWM2 Enable Control0: disable, 1: enable

DISBPWM2D Disable Control0: PWM2D enable1: PWM2D disable

INVMInvert PWM2D output0: not inverted1: output inverted

MOD1 MOD0 PWM2 Modulation SelectDefault "10" (Comb-AD)

ADLY2 ADLY1 ADLY0 PWM2 ABD DelayDefault "010" (4)

D15 D14 D13 D12 D11 D10 D09 D08 Function

EN PWM1 Enable Control0: disable, 1: enable

DISBPWM1D Disable Control0: PWM1D enable1: PWM1D disable

INVMPWM1D output invert control0: not inverted1: output inverted

MOD1 MOD0 PWM1 Modulation SelectDefault "10" (Comb-AD)

ADLY2 ADLY1 ADLY0 PWM1 ABD DelayDefault "010" (4)

D07 D06 D05 D04 D03 D02 D01 D00 Function0 0 0 0 reserved

MIDZ Enable MIDZ Start Up0: disable, 1: enable

HPBYPWM high-pass filter bypass control0: enable, 1: bypass

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14.11.1 PWM Modulation Select MOD1 MOD0 Description

0 0 AD Modulation 0 1 BD Modulation 1 0 Comb-AD Modulation 1 1 reserved

14.11.2 PWM ABD Delay ADLY2 ADLY1 ADLY0 ABD Delay (DCLKs)

0 0 0 0 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 39 1 1 0 40 1 1 1 41

14.11.3 De-emphasis Filter Mode DEM1 DEM0 Description

0 0 OFF 0 1 32kHz 1 0 44.1kHz 1 1 48kHz

NOTE: The default setting for PWM related registers suits for TAS3308 used as PWM DAC.

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14.12 PWM Channel Delay, Modulation limit and Offset (0x1A) D63 D62 D61 D60 D59 D58 D57 D56 Function

0 0 0 0 0 BS2 BS1 BS0 modulation limitDefault "000"

D55 D54 D53 D52 D51 D50 D49 D48 Function

OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 channel offsetDefault "00000000"

D47 D46 D45 D44 D43 D42 D41 D40 Function

0 0 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 delay for channel 3R (-32…+31)Default "001000"

D39 D38 D37 D36 D35 D34 D33 D32 Function

0 0 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 delay for channel 3L (-32…+31)Default "101000"

D31 D30 D29 D28 D27 D26 D25 D24 Function

0 0 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 delay for channel 2R (-32…+31)Default "010000"

D23 D22 D21 D20 D19 D18 D17 D16 Function

0 0 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 delay for channel 2L (-32…+31)Default "110000"

D15 D14 D13 D12 D11 D10 D09 D08 Function

0 0 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 delay for channel 1R (-32…+31)Default "000000"

D07 D06 D05 D04 D03 D02 D01 D00 Function

0 0 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 delay for channel 1L (-32…+31)Default "100000"

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14.13 PWM Duty 50 Mode Control (0x1D) The duty 50% start and stop sequence is fully controlled by micro F/W. The duty 50% duration control is done with 0x0C bit23-8 for GPIOMICROCOUNT which specifies Timer0 counter value (default 1.25ms) and this register which specifies Timer0 interrupt count. All zero indicates the duty 50% mode disable.

D31 D30 D29 D28 D27 D26 D25 D24 Function0 0 0 0 0 0 0 0 unused

D23 D22 D21 D20 D19 D18 D17 D16 Function0 0 0 0 0 0 0 0 unused

D15 D14 D13 D12 D11 D10 D09 D08 Functionx x x x x x x x Duration (Timer0 count)

0 0 0 0 0 0 0 0 Duty 50 mode disableD07 D06 D05 D04 D03 D02 D01 D00 Function

x x x x x x x x Duration (Timer0 count)

0 0 0 0 0 0 0 0 Duty 50 mode disable

14.13.1 SPLIT CAPACITOR CHARGE PERIOD REGISTER Configuration with Timer0 (1.25ms period) default setting is shown in Table 14-10.

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Table 14-10 Charge Period (Comparison between TAS3308 and TAS5086)

D15 - D12 D11 - D08 D07 - D04 D03 - D00 DurationTAS3308 (TAS5086)

0 0 0 0 Duty 50 Mode Disable0 0 0 A 12ms (13ms)0 0 0 D 16.25ms (16.9ms)0 0 1 2 22.5ms (23.4ms)0 0 1 8 30ms (31.2ms)0 0 2 1 41.25ms (41.6ms)0 0 2 B 53.75ms (54.6ms)0 0 3 A 72.5ms (72.8ms)0 0 4 C 95ms (96.2ms)0 0 6 8 130ms (130ms)0 0 7 C 155ms (156ms)0 0 B B 233.75ms (234ms)0 0 F 9 311.25ms (312ms)0 1 4 C 415ms (416ms)0 1 B 4 545ms (546ms)0 2 4 6 727.5ms (728ms)0 3 0 1 961.25ms (962ms)0 4 1 0 1300ms (1300ms)0 5 4 8 1690ms (1690ms)0 7 5 0 2340ms (2340ms)0 9 C 0 3120ms (3120ms)0 D 0 0 4160ms (4160ms)1 1 1 0 5460ms (5460ms)1 6 C 0 7280ms (7280ms)1 E 1 0 9620ms (9620ms)

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14.14 DAP Program Start Address (0x1E) The DAP instruction execution loops each Fs cycle. At the beginning of the Fs cycle, the DAP instruction pointer is set to the starting address specified in the 12 LSBs. The maximum address is the end address of DAP instruction address 3327. The default setting for TAS3308 is 0x0B90.

Table 14-11 DAP Program Start Address (0x1e)

D31 D30 D29 D28 D27 D26 D25 D24 Function0 0 0 0 0 0 0 0 unused

D23 D22 D21 D20 D19 D18 D17 D16 Function0 0 0 0 0 0 0 0 unused

D15 D14 D13 D12 D11 D10 D09 D08 Function0 0 0 0 x x x x Starting address MS Nibble

D07 D06 D05 D04 D03 D02 D01 D00 Functionx x x x x x x x Starting Address LS Byte

14.15 I2C Master Load (0x1F) This feature instructs the TAS3308 to go to a specified EEPROM memory address and initiate a load using the header and data that is stored at that location. In all other respects this feature operates identically to the I2C Master Load.

D31 D30 D29 D28 D27 D26 D25 D24 Function0 0 0 0 0 0 0 0 unused

D23 D22 D21 D20 D19 D18 D17 D16 FunctionA6 A5 A4 A3 A2 A1 A0 EEPROM Device address

0 2byte subaddress to be output1 1byte subaddress to be output

D15 D14 D13 D12 D11 D10 D09 D08 Function

SA15 SA14 SA13 SA12 SA11 SA10 SA09 SA08MS Byte Device subaddress(or the subaddress when 1byte subaddress is used)

D07 D06 D05 D04 D03 D02 D01 D00 FunctionSA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 LS Byte Device subaddress

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15. Application Information

15.1 Application Diagram

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Figure 15-1, Peripheral connections

15.2 PWM low-pass filters The audio output application diagram shows external low-pass filters used for suppressing out of band components in the PWM signals, thereby generating a low voltage signal useful for lineout, headphone or driving a TPA3100 that has an analogue audio input. One channel of PWM consists of an immediate PWM signal and a delayed PWM signal (not to be confused with differential output). The delayed PWM is identical to the immediate PWM except for the delay by a half PWM period. Adding the two PWM signals together produces a notch filter with the notch at the carrier frequency of the PWM. This filter suppresses HF noise at the PWM output, thereby allowing the output to drive an analog PWM amplifier.

Figure 15-2, Analogue outputs

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Mechanical Information