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The top documents tagged [fine tdc]
A flash high-precision Time-to-Digital Converter implemented in FPGA technology Topical Workshop on Electronics for Particle Physics Paris, 25 September
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Fig.2: Carry chain delay line: (a) logic block diagram; (b) layout obtained; (c) simplified block diagram of the Virtex 5 slice. Principle of operations
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Fig.2: Carry chain delay line: (a) logic block diagram; (b) layout obtained ;
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Fig.2: Carry chain delay line: (a) logic block diagram;
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