table of contents
DESCRIPTION
Laboratory Manual for Digital Design courseTRANSCRIPT
TABLE OF CONTENTSAcknowledgments
Introduction
Objectives
The Digital Kit1. Prototyping board2. Power Supply3. LEDs4. Switches5. 7-Segment Display6. Digital Clocks
Laboratory Exercises 0. Discrete Gates
1. Logic Gates a. Basic Logic Gates b. Logic Gates Applications
2. Digital Meets Analog Lab Exercise3. Full-Adder & Full-Subtractor
a. Construction of Full-Adder b. Construction of Full-Subtractor
4. Decoders a. Basic Decoders b. Decoder Applications
5. Multiplexer6. PLD 7. Sequential Circuit8. Counters9. Shift Registers10. Mini-Projects
a. Thunderbird Taillights b. Lamp Ping-Pong c. Other Proposal
11. IC Symbols & Pin-outs
ACKNOWLEDGMENTS
The laboratory exercises contained within this document have evolved from a set of exercises that have been taken from the Digital Design System Laboratory Manual 2005. Helpful comments have been made by Mr. Jose Claro Monje and Dr. Rosula Reyes who have used the experiments in their teaching of Digital Logic Design and Switching Theory.
INTRODUCTION
The goal of this experiment manual is to introduce the fundamentals of digital electronic components (basic gates, decoders, multiplexers, flip-flops, counters, shift registers) in a manner suitable for Engineering students. Breadboard prototyping will be performed to actualize digital circuits. Hopefully, this manual can serve as a systematic guide to “hands-on” experience with digital electronic concepts and devices taught in the lecture course.
OBJECTIVES
The course will provide the student with a firm foundation of the principles of digital design by building a working knowledge of digital electronics and its applications.
By the end of the semester, the student shall have acquired the basic skill in using the digital design kit;
● Use of prototyping board.● Use of basic gates, decoders and multiplexers.● Use of PLDs● Use of flip-flops, counters and shift registers.● Use of logic probe.
The Digital Kit
1. Prototyping/BreadboardThe breadboard is used to create a circuit without the need for soldering circuitelements together. The upper and lower halves of the breadboard contain 63 vertical rowsof 5 interconnected contacts. There are also 4 long horizontal rows of connectors (10groups of 5 contacts each) along the upper and lower edges. These long rows ofconnectors are referred to as power bus strips because they will be connected to thepower supplies to provide power connections over the entirety of the breadboard. Thisbreadboard socket is designed to accept integrated circuits, most common wire terminalcomponents, and wire interconnections.
2. POWER SUPPLYTh is segmen t of the board can pro v i d e a vo l t age of +5V and a max i m u m cur ren t of 1 Am pe re. The 220 ma i ns vo l t age is stepped down, rec t i f i e d, f i l t e red and regu la ted by a +12 V regu la t o r that supp l i es the powe r t o the shor t circu i t pro tec t i o n branch of th is segmen t. The +12 V is fu r t he r regu la ted to pro v i d e the +5V that is avai l a b l e for use in wha te ve r circu i t that is to be tested. Powe r is turned on by f i rs t mov i n g the sw i t c h to the 'ON' pos i t i o n and press i ng the 'RESE T / PUSH ON' but t on. Th is but t on is used fo r turn i n g on the board afte r a shor t ci rc u i t has happened.
3. LEDsThe re are eigh t LE D s ava i la b l e. These are act i va ted by supp l y i n g a TT L high to each of the cor respon d i n g term i n a l bloc k pins.
4. SWITCHESThe re are eigh t avai l a b l e swi t c hes in the k i t, six (Sw5 to Sw0) of wh i c h are ord i na r y togg le sw i t c hes wh i l e the two others are debounced swi t c hes (Sw6 & Sw7). The comm o n node of the sing le po le doub le thro w swi t c hes is connec ted to the w i re ho lde r wh i l e the other two nodes to ground and Vcc.
5. 7-SEGMENT DISPLAYThe two seven segmen t disp la ys are dr i ven by 7447 BCD- to-seven-segmen t disp l a y decode r/dr i v e rs. The said dr i ve r has 4 inpu ts cor respon d i n g to the binar y code of the desi red dec i ma l outpu t on the seven segmen t disp l a y. Inpu ts not connec ted to any value are cons ide red as 'f loa t i n g ' H I G H , thus caus ing the disp la y to turn of f when not in use.
6. DIGITAL CLOCKS Two fi xed cloc ks are pro v i d e d by the board, one hav i n g a frequenc y of 100Hz and the other 1 kHz. The frequen c y of cloc k 1 (CLK 1) can be changed by put t i n g across capac i t o r s in C1 and – . A capac i t o r value of 47 uF w i l l decrease the frequenc y to around 2 Hz. The frequenc y of cloc k 2 (CLK2) can be changed by put t i n g across capac i t o r s in C2 and – .
Laboratory Exercises
0. Discrete Gates
This laboratory exercise aims to relate logic gates with discrete electronic elements such as diodes and transistors. By using a truth table, determine the logic function performed by the circuits below. Assume that a voltage of 0 to 0.8V is a logic LOW and a voltage of 2.4V to 5V is a logic HIGH. Explain why you are getting the output voltage levels for each circuit. Are these the expected values for the given circuit?
1. LOGIC GATESObjectiveTo fam i l i a r i z e the studen ts w i t h the use of TT L (trans is t o r- trans is t o r log i c) GA T E S and the tru th tab le.
Logic GatesA logic gate per f o r m s a log i ca l opera t i o n on one or more log i c inpu ts and prod uces a sing le log i c outpu t. Since the outpu t is also a log i c- leve l value, an outpu t of one log i c gate can be connec ted to the inpu t of one or mo re other log i c gates. The log i c norma l l y per f o r m e d is Boo l ean log i c and is mos t comm o n l y found in dig i ta l circu i t s
The mos t comm o n log i c opera t i o ns are NO T, OR and AN D .
NOTTh is log i c opera t i o n outpu t s the comp l i m e n t of the operand. For examp l e, NO T 1 = 0 and NO T 0 = 1. The symb o l s used to represen t the NO T opera t i o n are the ti l de “~” befo re the operand ( ), a min us sign “ “ befo re the operand ( ), a pr i me symbo l “ “ ( ) afte r the operand or a bar over the operand ( )
Examp l es : or
or
OR Th is log i c opera t i o n outpu t s 1 if at least one operand is equa l to 1. For examp l e, 1OR 0 OR 1 OR 0 = 1. The symbo l used to represen t the OR opera t i o n is a plus sign “ ” between operands ( ).
Examp l e :1
ANDTh is log i c opera t i o n outpu ts 1 if and on l y i f al l operands are equa l to 1. For examp l e, 1 AN D 0 AN D 1 AN D 1 = 0. The symbo l s used to represen t the A N D opera t i o n are the ampersand “” or the dot prod uc t “٠” between operands ( ).
Examp l e : or
Truth tablesA tru th tab le is a table that desc r i bes the behav i o r of a log i c gate. It lis ts the value of the outpu t fo r every poss ib l e comb i n a t i o n of the inpu ts. Tab le 1 shows the tru th tab le for a NO T opera t i o n, Tab le 2 shows the tru th tab le fo r a two- inpu t AN D opera t i o n and table 3 shows the tru th tab le for a two- inpu t OR opera t i o n.
Table 1. NOT, AND and OR Truth TablesA NOT (A)
0 1
1 0
A B A AND B
0 0 0
0 1 0
1 0 0
1 1 1
A B A OR B
0 0 0
0 1 1
1 0 1
1 1 1
Logic Symbol
a. Basic Logic Gate ExerciseThe logic gates that we will use are integrated chips (ICs) that use transistors to perform logical operations, thus they are called transistor-transistor logic (TTL) ICs. The ICs that you will be using are quad 2-input logic gates; there are four logic gate units in each IC taking in two separate inputs each.
Each group will be provided with two of the following ICs: 74LS00, 74LS02, 74LS08,and 74LS32. These are the AND, OR, NAND (NOT AND) and NOR (NOT OR) quad gates (not respectively or not necessarily in that order). The pin assignments are shown below:
Note:1A, 1B are the inputs and 1Y is the output for the first logic gate in the IC;2A, 2B are the inputs and 2Y is the output for the second logic gate in the IC;and so on...Vcc is the supply voltage of the IC.
For TTL, Vcc should be +5V ± 5% ,i.e., 4.75V to 5.25V.GND is the ground pin or 0V.
Two volts (2V) to five volts (5V) applied to an input of the IC is considered a high signal (logic 1). While 0V to 0.8V is considered a low signal (logic 0). Greater than 0.8V and lower than 2V is considered undefined. This voltage requirement is for TTL but for other low-powered ICs like LVTTL, LVCMOS, the voltage requirements for a high signal is lower. You can use logic switches SW0 and SW1 as your inputs. Use the logic probe or LED0 for the output, construct the truth table for each of the ICs as shown below:
Exhaust all possible combinations of inputs and check the outputs of each.
SW0 = 1A SW1 = 1B 1Y of 7400
0 0
0 1
1 0
1 1
Based on your truth table, the logic function of 7400 is ________________
SW0 = 1A SW1 = 1B 1Y of 7402
0 0
0 1
1 0
1 1
Based on your truth table, the logic function of 7402 is ________________
SW0 = 1A SW1 = 1B 1Y of 7408
0 0
0 1
1 0
1 1
Based on your truth table, the logic function of 7408 is ________________
SW0 = 1A SW1 = 1B 1Y of 7432
0 0
0 1
1 0
1 1
Based on your truth table, the logic function of 7432 is ________________
b. Application1. The truth table below implements a 3-bit majority one circuit i.e. the output is 1 when the number of 1s in the input is a majority ( 2 or more 1s). Implement the truth table given below.
A B C OUT
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Write the equation for the 3-bit majority one circuit (OUT). Draw the circuit diagram. Construct the circuit using AND-OR-NOT gates.
FYI, The NOT gate or inverter IC is 74LS04, shown below.
2. A house alarm system has three inputs – alarm enable (E), door intruder (D) sensor and window intruder (W) sensor. The alarm (A) will turn on if the alarm is enabled (E) and the door intruder sensor (D) or window intruder sensor (W) is activated. The alarm will not be activated, if the alarm is not enabled even if there is an intruder coming from the door or the window. Alarm enable is ON when E = 1. The door intruder sensor is ACTIVATED when D = 0. The window intruder sensor is ACTIVATED when W = 0.
Construct a truth table for the house alarm system. Using the ICs provided, construct such an alarm system. Write the equation for the alarm system (A). Draw the circuit or schematic diagram of your designed alarm system. You may ask for additional ICs from your instructor like the 74LS04, which is a NOT gate or an inverter.
3. Basic Combinational Circuit Lab. Exercise
AND-OR-NOT. This laboratory exercise requires the design of a simple combinational circuits using AND-OR-NOT gates (i.e. 74xx08, 74xx32 & 74xx04). This exercise aims to familiarize the students in the use of logic gates as well as implementing circuits from a truth table.
Group 1
wxyz f wxyz f0000 1 1000 00001 1 1001 00010 1 1010 00011 1 1011 00100 0 1100 00101 1 1101 00110 1 1110 10111 1 1111 1
Group 2
wxyz f wxyz f0000 1 1000 10001 0 1001 10010 1 1010 10011 1 1011 10100 0 1100 00101 0 1101 00110 0 1110 00111 1 1111 1
Group 3
wxyz f wxyz f0000 0 1000 10001 0 1001 10010 1 1010 10011 0 1011 10100 0 1100 00101 0 1101 00110 1 1110 10111 1 1111 1
Group 4
wxyz f wxyz f0000 1 1000 10001 0 1001 00010 1 1010 10011 0 1011 10100 0 1100 00101 1 1101 10110 0 1110 10111 1 1111 1
Group 5
wxyz f wxyz f0000 1 1000 10001 0 1001 00010 0 1010 00011 0 1011 00100 1 1100 10101 1 1101 10110 1 1110 00111 1 1111 0
Group 6
wxyz f wxyz f0000 1 1000 00001 1 1001 00010 1 1010 00011 1 1011 10100 0 1100 10101 0 1101 10110 0 1110 10111 1 1111 1
Group 7
wxyz f wxyz f0000 0 1000 00001 1 1001 10010 0 1010 00011 0 1011 00100 1 1100 00101 1 1101 10110 1 1110 00111 1 1111 1
Group 8
wxyz f wxyz f0000 0 1000 00001 1 1001 10010 0 1010 10011 1 1011 10100 1 1100 10101 0 1101 00110 1 1110 10111 0 1111 1
4. NAND Gates. This laboratory exercise requires the design of a simple combinational circuits using NAND gates (i.e. 74xx00, 74xx10 or 74xx20). This exercise provides some insight into intuitive minimization at the package level (number of ICs used) rather than the gate level.
set A(assigned to groups 1 & 8)
wxyz f wxyz f0000 0 1000 00001 0 1001 00010 0 1010 00011 1 1011 10100 1 1100 00101 1 1101 00110 1 1110 10111 1 1111 1
set B(assigned to groups 2 & 7)
wxyz f wxyz f0000 0 1000 10001 0 1001 10010 0 1010 10011 1 1011 10100 0 1100 00101 0 1101 00110 1 1110 10111 1 1111 1
set C(assigned to groups 3 & 7)
wxyz f wxyz f0000 0 1000 00001 1 1001 00010 0 1010 00011 1 1011 10100 0 1100 10101 1 1101 10110 0 1110 10111 1 1111 1
set B(assigned to groups 4 & 5)
wxyz f wxyz f0000 0 1000 10001 0 1001 10010 0 1010 10011 1 1011 10100 0 1100 00101 0 1101 10110 0 1110 00111 1 1111 1
Paper Design (to be included in the lab report). Design and implement a 4-bit majority-1 circuit using NAND gates (i.e. 74xx00, 74xx10 or 74xx20). A majority-1 circuit is a circuit that outputs a 1 when three or four of the inputs are1.
2. Digital Meets Analog Lab ExerciseSeat Belt Warning System. In a certain seat belt warning system, a warning indicator is activated (turned on, high logic or logic 1) when at least one of the car passenger is not wearing the seat belt. Design a circuit (no need to simplify, use AND-OR-NOT gates) that will show the seat belt warning system output. Use this digital seat belt warning system output to control a buzzer. Note that the digital output might not be able to drive the buzzer so you have to use a transistor driver or an amplifier circuit. The system will work regardless of the number of passengers inside the car.
Assume: car is 4-seater, each seat has a sensor (S1, S2, S3, S4) and each seat belt has a sensor (B1, B2, B3, B4 corresponding to each seat sensor). Seat sensor is high (1) when it is occupied else low (0). Seat belt sensor is high when it is being used else it is low.
Light Sensor with Motor Control. You are to design a light sensor input system and motor control circuit. It consists of three input variables and two output variables. The variables are described as follows: (3) selectors and (2) controls. The selectors (S2, S1 and S0) are input signals coming from the light sensors (L1 and L0) and a switch, S1 = 1 when L1 is activated (light sensor ON) and S0 = 1 when L0 is activated (light sensor ON), S2 = 1 when the switch is ON. The control variables (C1 and C0) are output signals to the analog circuit that controls the DC motors (M1 and M0). The selector inputs (S2, S1 and S0) determine the motor functions (C1, C0) as follows:
S2 S1 S0 C1C0 function description0 0 0 1 1 forward : both motors are ON 0 0 1 0 1 turn right : M1 is ON, M0 is OFF0 1 0 1 0 turn left : M1 is OFF, M0 is ON0 1 1 1 1 forward : both motors are ON1 X X 0 0 stop : both motors are OFF
Note: In the absence of DC motors, a tungsten lamp maybe used to simulate the activation of the motor.
3. Full-adder & full-subtractorObjective:To fam i l i a r i z e the studen ts w i t h the const r u c t i o n and var i o us imp l e me n t a t i o n s of Adde r and Subt rac t o r ci rc u i t s.
Half-AdderA half-Adder is a comb i n a t i o n a l log i c circu i t that is able to per f o r m the add i t i o n of two bi ts. It takes two inpu t signa ls, X and Y, adds them and outpu ts a sum (S) and carry (C). Th i s ad -dit i o n cons is ts of fou r poss ib l e comb i n a t i o n s of inpu ts and outpu t s, name l y , 0+0=0, 0+1= 1 , 1+0= 1 and 1+ 1 = 1 0. The f i rs t three opera t i o ns have a sum whose leng t h is on l y 1 bit but the fou r t h , has a sum that cons is ts of two dig i t s. The carry is the highe r sign i f i c a n t bi t of the two dig i t s in the fou r t h poss ib l e comb i n a t i o n .
The tru th tab le belo w is der i ve d from th is descr i p t i o n.INPUT OUTPUT
X Y C(Carry) S(Sum)0 0 0 00 1 0 11 0 0 11 1 1 0
The Boo l ean express i o n fo r each outpu t can be der i ve d from the tru th tab le:
The two imp l eme n t a t i o n s shown belo w of the hal f- adder ci rc u i t are the sum of produ c t s and produ c t of sums nota t i o n taken from the tru th tab le above.
Sum of Produ c t s Produ c t of Sums
No te that S is the exc l us i v e- OR of X and Y. The comp l e me n t of S is the equ i v a l e n ce (exclu -sive-NOR) of x and y.
Sum of Produ c t s Produc t of Sums
The hal f- adder belo w is imp l eme n t e d using an exc l us i v e- OR (XOR) and an AN D gate.
a. Construct a Full-Adder Circuit.
A full-adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables denoted by x and y, represent the two significant bits to be added. The third input, z, represents the carry from the previous lower significant position. Two outputs are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3 needs two digits. The two outputs are designated by the symbols S for sum and C for carry. The binary variable S gives the value of the least significant bit of the sum. The binary variable C gives the output carry. (C,S = X + Y + Z). The partial truth table of the full-adder is given below. Kindly complete the table then implement the circuit. If you can, implement S and C using only XOR, OR and AND gates.
X Y Z C S
0 0 0 0 0
0 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0
1 0 1
1 1 0
1 1 1 1 1
Note: Don’t dismantle the circuit, you might need it in the succeeding exercise.
Shown below is an XOR gate IC, 74LS86.
b. Construction of a Full-Subtractor Circuit
A full-subtractor is a combinational circuit that performs a subtraction between two bits, taking into consideration that a 1 may have been borrowed by a lower significant stage. This circuit has three inputs and two outputs. The three inputs, x, y and z, denote the minuend, subtrahend and previous borrow, respectively. The two outputs, D and B, represent the difference and the output borrow, respectively. (B,D = X - Y - Z). The partial truth table of the full-subtractor is given below. Kindly complete the table then implement the circuit. If you can, implement D and B using the circuit constructed above and an INVERTER.
X Y Z B D
0 0 0 0 0
0 0 1 1 1
0 1 0
0 1 1 1 0
1 0 0
1 0 1
1 1 0
1 1 1 1 1
4. DecodersObjectiveTo fam i l i a r i z e the studen ts w i t h the use and app l i ca t i o n of decode rs in dig i t a l ci rc u i t s.
DecodersA decoder is a mu l t i p l e- inpu t, mu l t i p l e- outpu t log i c circu i t that conve r ts coded inpu ts in to coded outpu t s, whe re the inpu t and outpu t codes are di f f e re n t such as n-to-2 n Bi na r y Coded Dec i m a l (BCD) decode rs. Decode rs have an enab le pin, wh i c h needs to be turned on for the decode r to func t i o n, other w i s e its outpu ts assume a sing le "disab led" outpu t code wo r d. Decod i n g is necessary in app l i ca t i o n s such as data mu l t i p l e x i n g , 7 segmen t disp la y and memo r y address decod i n g .
Let us cons ide r n-to-2 n type bina r y decode rs. These decode rs are comb i n a t i o n a l ci rc u i t s that conve r t bina r y in f o r m a t i o n from 'n' numbe r of coded inpu ts to a max i m u m numbe r of 2 n
un iq ue outpu t s. We say a maximum number of 2 n outpu ts because if the 'n' bi t coded in fo r m a t i o n has unused bi t comb i n a t i o n s, the decode r wou l d have less than 2 n outpu t s. A va i l a b l e decode rs are the 2-to-4 decode r (74xx 139), 3-to-8 decode r (74xx 138) and 4-to-16 decode r (74xx 1 54). We can fo rm a 3-to-8 decode r from two 2-to-4 decode rs (with enab le signa ls). We can form a 4-to-16 decode r from two 3-to-8 decode rs (with enab le signa ls).
Exam p l e : A 2-to-4 L i ne Decode r (withou t an enab le line)
Examp l e of TT L ICs (a) dual 2-to-4 decoders with enable (74LS139);
(b) 3-to-8 decoder with enable lines (74LS138)
Lab Exercise: a. For the 3-to-8 decoder IC (74LS138) verify that it does the following function as shown in the table below:
IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT
G2B' G2A' G1 C B A Y0' Y1' Y2' Y3' Y4' Y5' Y6' Y7'
X X 0 X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
1 X X X X X 1 1 1 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 0
Note: “X” means “don’t care”,i.e., may take the values of 0 or 1.
Connect inputs G2B', G2A', G1, C, B and A to switches sw5, sw4, sw3, sw2, sw1 and sw0 respectively. Connect the outputs Y0', Y1', Y2', Y3', Y4', Y5', Y6' and Y7' to LED0 to LED7 respectively.
IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT
G2B' G2A' G1 C B A Y0' Y1' Y2' Y3' Y4' Y5' Y6' Y7'
X X 0 X X X
X 1 X X X X
1 X X X X X
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 0 1
0 0 1 1 1 0
0 0 1 1 1 1
b. Application:4-to-16 decoder. Implement the following truth table using 3-to-8 decoders
(74xx138) and a 4-input NAND gate (74xx20). The inputs d, c, b and a are to be connected to sw3, sw2, sw1 and sw0 respectively. Output f is to be connected to LED0.
set A (groups 1, 5 & 9)dcba f Cont. dcba Cont. f0000 1 1000 00001 0 1001 00010 0 1010 00011 0 1011 00100 1 1100 00101 0 1101 00110 0 1110 10111 1 1111 0
set B (groups 2, 6 & 10)dcba f Cont. dcba Cont. f0000 0 1000 00001 1 1001 00010 0 1010 10011 0 1011 00100 0 1100 00101 0 1101 00110 1 1110 00111 0 1111 1
set C (groups 3 & 7)dcba f Cont. dcba Cont. f0000 1 1000 10001 0 1001 00010 0 1010 00011 0 1011 00100 0 1100 10101 1 1101 00110 0 1110 00111 0 1111 0
set D (groups 4 & 8)
dcba f Cont. dcba Cont. f0000 0 1000 00001 0 1001 00010 1 1010 00011 0 1011 00100 0 1100 10101 0 1101 00110 1 1110 00111 0 1111 1
Hint: Construct a 4-to-16 decoder with two 3-to-8 decoders (74LS138).
5. MultiplexersA digital multiplexer or mux is a device that performs multiplexing; it selects one of many digital input signals and outputs that into a single line.
Example of 2-to-1 Multiplexer (symbol shown above) without an enable signal.
Example of TTL ICs: (a) dual 4-to-1 multiplexer with enable (74LS153) and
(b) 8-to-1 multiplexer with enable line (74LS151).
Truth table for a 4-to-1 multiplexer:
Selector Selector Strobe/Enable
Output Inverted Output
C B G' Y W
X X 1 0 1
0 0 0 C0 C0'
0 1 0 C1 C1'
1 0 0 C2 C2'
1 1 0 C3 C3'
Application:Tail Lights. You are to configure two multiplexers (74xx151 or equivalent) into a tail light system. It consists of four input variables and two output variables. The four input variables are describe as follows: (1) blinker and (3) selectors. The blinker input is connected to the CLOCK output of the digital kit. Use an appropriate frequency setting (one where blinking of LEDs can be observed) for the CLOCK output. The blinker is used to make the outputs turn on and off (LEDs blink). The selector inputs (S2 = sw2, S1 = sw1 and S0 = sw0) determine the tail light functions as follows:
S2 S1 S0 function description0 0 0 do nothing : the output LEDs are at logic low0 0 1 turn right : the right output LED is blinking while
the left output LED is at logic low.0 1 0 turn left : the left output LED is blinking while
the right output LED is at logic low0 1 1 emergency : all output LEDs are blinking1 x x brake : all output LEDs are at logic high
Where x means “don’t care” i.e. may take the values of 0 or 1.
Note: For better output display, connect two LEDs per output i.e. two LEDs for left signal and two LEDs for right signal.
6. PLDWe will be using a PAL/PALCE/GAL16V8A (PLD with 16 programmable pins, 8 of
which are inputs and the other 8 as input/output). We will be using a PLD compiler. A sample template accepted by the compiler is as follows:
Any line that starts with a bar ( | ) is considered as a compiler statement and any line that does not start with a bar ( | ) is considered as a remark or a comment.
PLD Compiler Template
A. Using Boolean equations
| Device_name in: (input_variable_declaration), io: (i/o_var_declaration)| Boolean_equation
B. Using Tables (Truth)
| Device_name in: (input_variable_declaration), io: (i/o_var_declaration)| Table: input_var_list -> output_var_list| { all_possible_input_combination -> output }
C. Example
Implement using PLD.
x y z f0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 11 1 1 0
using K-map: f = yz' + x'z
Using PAL/PALCE/GAL16V8A (say saved in file example.pld)
sol'n #1
| GAL16V8A in: (x,y,z), io: (f)| f = (y & z' ) # (x' & z)
sol'n #2
| GAL16V8A in: (x,y,z), io: (f)| table: x, y, z -> f| { 000b -> 0| 001b -> 1| 010b -> 1| 011b -> 1| 100b -> 0| 101b -> 0| 110b -> 1| 111b -> 0 }
sol'n #3
| GAL16V8A in: (x,y,z), io: (f)| table: x, y, z -> f| { 0 -> 0| 1 -> 1| 2 -> 1| 3 -> 1| 4 -> 0| 5 -> 0| 6 -> 1| 7 -> 0 }
D. Use of Compiler/Programmer
The compiler and programmer is located in c:\pld. So, from drive c, do the following commands.
c:\> cd pldc:\pld> pld example.pld
The pld.exe compiler, if no errors are encountered, will generate three (3) other files namely *.lst, *.jed and *.vec files. These files are described as follows:
example.lst -- contains the followingoriginal file the sum of product form of the equation or truth tablepin assignments *fuse file (JEDEC format)
example.jed -- contains the fuse file in JEDEC format that will be the input file of the PLD programmer
example.vec -- the vector file containing the check vectors
If there is an error the .lst file will tell you where the error occurred.
* The pin assignment by default is as follows pin 1 is reserved for the clock pulsepin 2-9 for the inputs respectivelypin 10 is ground (gnd)pin 11 is for flip-flop enable (not used at the moment)pin 19-12 for outputs respectivelypin 20 is for Vcc (+5 V)
After generating the .jed file, run the PLD programmer (wpld.exe).
load the JEDEC file check whether the PLD is blank if not then bulk erase it then program the PLD
You are all set (the default pin assignment will be 10 for gnd, 20 for Vcc, 2 for X, 3 for Y, 4 for Z and 19 for f).
The Lab. Exercise
1. Binary-to-seven-segment decoder. You are to program your PLD into a binary to 7-segment decoder. The decoder is a combinational circuit that accepts 4-bit input and generates the appropriate outputs for selection of segments in a display indicator used for displaying the decimal digit or letter (we'll be using hexadecimal representation). The seven outputs of the decoder (a, b, c, d, e, f and g) select the corresponding segments in the display as shown below (a).
(a)
As a preliminary exercise, you are to find the pin assignment for the seven-segment LED display using only a +5V supply and a 1k ohm resistor. Have a nice day!
2. Tail Lights. You are to program a PLD into a tail light system. It consists of four input variables and two output variables. The four input variables are describe as follows: (1) blinker and (3) selectors. The blinker input is connected to the TTL output of the function generator. Use an appropriate frequency setting (one where blinking of LEDS can be observed) for the TTL output. The blinker is used to make the outputs turn on and off (LEDS blink). The selector inputs (S2, S1 and S0) determine the tail light functions as follows:
S2 S1 S0 function description0 0 0 do nothing : the output LEDs are at logic low0 0 1 turn right : the right output LED is blinking while
the left output LED is at logic low.
0 1 0 turn left : the left output LED is blinking while the right output LED is at logic low
0 1 1 brake : all output LEDs are at logic high1 x x emergency : all output LEDs are blinking
3. Optional. To be assigned by your lab. instructor.
7. FLIP-FLOPS and SEQUENTIAL CIRCUIT
ObjectiveTo fam i l i a r i z e the studen ts w i t h the const r u c t i o n and use of di f f e ren t types of f l i p- f lo ps in dig i t a l ci rc u i t s.
Flip-FlopsA flip-flop ma i n ta i ns a binar y state inde f i n i t e l y (as long as the circu i t is powe re d) unt i l it rece i v es an inpu t signa l to sw i t c h states. There are var i o u s types of f l i p f lo ps that di f f e r in the numbe r of inpu ts they possess and how the inpu ts af fec t the binar y state.
Basic Flip-Flop/SR LatchThe basic flip-flop or the SR latch has two inpu ts, the set(S) and reset(R). The schema t i c for a basic f l i p- f lo p is shown belo w. A NOR gate outpu t s a log i c low when there is at least one log i c high inpu t. It on l y outpu ts log i c high when al l inpu ts are zero.
Whe n log i c high is app l i e d to the set(S) inpu t and a log i c low is fed to the reset(R) inpu t, the bot t o m NOR gate outpu ts a log i c low due to the log i c high of the S inpu t regard l ess of wha t is the value of the other inpu t. The log i c low outpu t of the bot t om NOR gate is then fed to the upper NOR gate, togethe r w i t h the log i c low of the R inpu t. The resu l t i n g outpu t from the S=1, R=0 inpu t comb i n a t i o n is Q= 1, Q’=0. The oppos i t e happens when R= 1 and S=0, the resu l t i n g outpu t is Q=0 and Q’= 1 . Whe n Q= 1 and Q’=0, it is said to be in the set state and when Q=0 and Q’= 1 , it is in the clear state.N A N D gates can also be used to cons t r u c t a basic f l i p- f lop. Its di f f e ren ce is that to act i va te the set mode, a 0 mus t be fed to the inpu t S wh i l e inpu t t i n g a 1 to the inpu t R, oppos i t e of the NOR imp l e me n t a t i o n .
ExerciseFor the NOR imp l e me n t a t i o n of the bas ic f l i p- f lo p, do the comb i n a t i o n of inpu ts S and R belo w , in order and record the outpu t in to the tru th tab le. Connec t inpu ts S and R to sw i t c hes sw 1 and sw0 respec t i v e l y . Connec t outpu ts Q and Q’ to LE D 1 and LE D0 respec t i v e l y . Dete rm i n e wh i c h comb i n a t i o n of inpu ts shou l d be avo i ded because of its outpu ts.
S R Q Q’1 0 1 00 0 1 00 1 0 10 0 0 11 1 0 0
RS Flip-FlopThe RS flip-flop is a mod i f i e d basic f l i p- f lop whe re an add i t i o na l inpu t con t r o l s when the states of the f l i p- f lop change. The basic f l i p- f lo p changes states as soon as the inpu ts change wh i l e an RS fl i p- f lop changes states at the nex t cloc k pulse. The tru th tab le for the chang i n g state of the Q outpu t of the RS fl i p- f lo p is shown belo w .
Q S R Q(t+1)0 0 0 00 0 1 00 1 0 10 1 1 Inde te rm i n a t e1 0 0 11 0 1 01 1 0 11 1 1 Inde te rm i n a t e
Whe re Q is the presen t state and Q(t+1) is the nex t state of the outpu t. No te that whene ve r S and R are both high, the nex t state is inde te rm i n a t e because it places zeroes into the inpu ts of the bas ic f l i p- f lo p used and makes outpu ts Q and Q’ both high, wh i c h is avo i ded because both mus t be comp l e me n t s of each other.
ExerciseCons t r u c t an RS Fl i p- f lo p by add in g two more N A N D gates to the N A N D imp l eme n t a t i o n of the basic f l i p- f lo p ci rc u i t . Connec t the three inpu t elemen t s, CP(cloc k pulse), S(set) and R(reset) to the pu lse r, sw 1 and sw0 of the dig i t a l k i t respec t i v e l y . Connec t outpu ts Q and Q’ to LE D 1 and LE D0 respec t i v e l y . Ma k e the pu lse r ’s speed low enough to obser ve the cloc k pu lse. The momen t the cloc k pu lse goes high, the log i c high of eithe r the S or R inpu t shou l d be fed into the inpu ts of the bas ic f l i p- f lo p. Ve r i f y that the cloc k con t r o l s the state change by obser v i n g when the outpu ts change state.
D Flip-FlopThe D flip-flop addresses the prob l em of the RS fl i p- f lo p abou t both inpu ts being 1 at the same time. The sole inpu t, D is connec ted to the S inpu t wh i l e its inve r ted value is fed into the reset inpu t of the RS fl i p- f lo p to ensure that on l y one inpu t is high and the other, low at a time. If D is 1, the nex t state of the outpu t Q goes to 1 and when D is 0, the nex t state of the outpu t Q becomes 0.
ExerciseCons t r u c t the D fl i p- f lo p from the NA N D imp l eme n t a t i o n of the RS fl i p- f lop. Comp l e t e the tru th tab le of the D fl i p- f lop belo w.
Q D Q(t+1)0 0 00 1 11 0 01 1 1
JK Flip-FlopThe JK fl i p- f lo p is ano the r mod i f i c a t i o n of the RS fl i p- f lop wh i c h has its own way of deal i n g w i t h the RS fl i p- f lo p ’s undes i rab l e inpu t comb i n a t i o n (when S=1 and R= 1). The JK fl i p- f lo p has 2 inpu ts J and K, each A N D e d w i t h the cloc k pulse and its cor respon d i n g NOR outpu t. The schema t i c fo r the JK fl i p- f lo p is shown belo w .
ExerciseCons t r u c t the JK fl i p- f lo p ci rc u i t . Obse r v e wha t happen when the inpu ts are J=1 and K= 1 . Comp l e t e the tru th tab le fo r the nex t state outpu t belo w.
Q J K Q(t+1)0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0
T Flip-FlopThe T fl i p- f lop is a mod i f i c a t i o n of the JK fl i p- f lo p but it has onl y one inpu t instead of two inpu ts that the JK fl i p- f lo p has. The nex t state is dependen t on the value of the inpu t T. When T=0, the nex t state outpu t is reta i ned but when T= 1 , the nex t state outpu t is the oppos i t e of the presen t state.
Q T Q(t+1)0 0 00 1 11 0 11 1 0
ExerciseDraw and cons t r u c t the schema t i c for the T fl i p- f lop based on the in fo r m a t i o n you have gathered from the JK fl i p- f lop and the desc r i p t i o n of the T fl i p- f lo p. Ve r i f y you r ci rcu i t using the T fl i p- f lo p ’s tru t h tab le.
SEQUENT IAL CIRCUIT EXE RC I S ES
Set 1/5/9A. Design a counter using D flip-flops. The circuit counts 0-1-3-7-15-7-3-1-0-1-3-etc.
a. give the state diagram & the transition tableb. the expressions for the D inputsc. the expression for the output if anyd. the logic diagrame. do the actual circuit implementation
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Set 2/6/10C. Design a counter using D flip-flops. The circuit counts 0-8-12-14-15-14-12-8-0-8-12-etc.
a. give the state diagram & the transition tableb. the expressions for the D inputsc. the expression for the output if anyd. the logic diagrame. do the actual circuit implementation
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Set 3/7/11 E. Design a counter using D flip-flops. The circuit counts 0-1-3-7-15-0-1-3-7-15-0-1-etc. a. give the state diagram & the transition table b. the expressions for the D inputs c. the expression for the output if any d. the logic diagram e. do the actual circuit implementation
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Set 4/8/12F. Design a counter using D flip-flops. The circuit counts 0-8-12-14-15-0-8-12-14-15-0-8-etc. a. give the state diagram & the transition table b. the expressions for the D inputs c. the expression for the output if any d. the logic diagram e. do the actual circuit implementation
FYI, The D-flip-flop IC is 74LS74, shown below.
PRE' CLR' CLK D Q Q'
0 1 X X 1 0
1 0 X X 0 1
0 0 X X 1 1
1 1 POS 0 0 1
1 1 POS 1 1 0
1 1 0 X Q0 Q'0
LEGEND:0 = logic low1 = logic highX = don't carePOS = positive edge of clock, low to high transition.
Q0, Q'0, means previous values of Q i.e. retain old value (HOLD)
8. COUNTERSConstruct a digital circuit that counts from 00 to 99 using two BCD counters (2 x 74LS190) and necessary gates. Use the 7-segment display of the digital design kit to show the counter output. Use the digital kit variable clock for the clock input of the counter. Use an appropriate frequency. You can connect CTEN' input to sw0 to make it an up or down counter.
CTEN' D/U' CLK LOAD' A B C D QA QB QC QD RCO' MAX/MIN
0 X X 0 a b c d a b c d * **
0 1 POS 1 X X X X Count down
Count down
Count down
Count down
* **
0 0 POS 1 X X X X Count up
Count up
Count up
Count up
* **
1 X X X X X X X QA0 QB0 QC0 QD0 * **
LEGEND:0 = logic low1 = logic highX = don't carePOS = positive edge of clock, low to high transition.
QA0, QB0, QC0, QD0 means previous values of Q i.e. retain old valueCount down means if previous count is 7, new count is 6Count up means if previous count is 7, new count is 8* = during the UP count MAX/MIN goes HIGH at count 9, during the DOWN count
MAX/MIN goes HIGH at count 0.** = during the UP count RCO goes LOW at count 9, during the DOWN count RCO
goes LOW at count 0.
9. SHIFT REGISTERConstruct a digital circuit that counts 0,1,3,7,15,31,63,127,255 then back to zero using two universal shift registers (2 x 74LS194) and necessary gates. Use the 8 LEDs to display output. Use the digital kit variable clock for the clock input. Use an appropriate frequency.
MODE INPUTS OUT- PUTS
CLR' S1 S0 CLK SL SR A B C D QA QB QC QD
0 X X X X X X X X X 0 0 0 0
1 X X 0 X X X X X X QA0 QB0 QC0 QD0
1 1 1 POS X X a b c d a b c d
1 0 1 POS X 1 X X X X 1 Qan Qbn QCn
1 0 1 POS X 0 X X X X 0 Qan Qbn QCn
1 1 0 POS 1 X X X X X Qbn Qcn Qdn 1
1 1 0 POS 0 X X X X X QBn QCn Qdn 0
1 0 0 X X X X X X X QA0 QB0 QC0 QD0
LEGEND:0 = logic low1 = logic highX = don't carePOS = positive edge of clock, low to high transition.
QA0, QB0, QC0, QD0 means previous values of Q i.e. retain old value
10. Mini-PROJECTS :-)Possible Projects:
a. T-BIRD TAILIGHTS
The design of a circuit that emulates the operation of the taillights of a Thunderbird is carried out in this project.
Lab. Exercise
You are to design and build a circuit that controls the eight taillights on a Thunderbird. Use eight LEDs to simulate the eight taillights (four on each side of the car), and use two toggle switches (L & R) for the turn signals and another for brake (B).
The turn signals and brake (L, R and B) determine the tail light functions as follows:
B L R function description0 0 0 do nothing the output LEDs are at logic low0 0 1 turn right the 4 rightmost output LEDs should
cycle as shown in figure 1 while the 4 leftmost output LEDs are at logic
low.0 1 0 turn left the 4 leftmost output LEDs should
cycle as shown below while the 4 rightmost output LEDs are at logic
low.0 1 1 emergency all output LEDs are blinking1 0 0 brake all output LEDs are at logic high1 0 1 brake + right
turnthe 4 rightmost output LEDs should cycle as shown below while the 4 leftmost output LEDs are at logic
high.1 1 0 brake + left turn the 4 leftmost output LEDs should
cycle as shown below while the 4 rightmost output LEDs are at logic
high.1 1 1 parked light all output LEDs are on
LED Pattern:Left turn: 0000 -> 0001 -> 0011 -> 0111 -> 1111 -> 0000 and so onRight turn: 0000 -> 1000 -> 1100 -> 1110 -> 1111 -> 0000 and so on
0 = LED off1 = LED on
b. LAMP PING- PONG
The design of the Ping-Pong machine for two human players is carried out in this project. The machine is an amusing application of shift registers as well as an exposure to control logic.
Design and construct a circuit that allows two people to play Ping-Pong using eight indicator lamps in a row to display the moving ball and using two push button (or toggle switches) for paddles.
Use two cascaded 4-bit shift registers containing a single turned on LED to represent the ball. Use one push button (toggle switch) for the right-hand user, one for the left-hand user. The ball should be moved by a clock source that causes a shift once every quarter second or so. When the ball is moving to the right, the right-hand player must depress his push button (toggle switch) at the time the ball is in its rightmost position. (The circuit should be sensitive only to the leading edge of the push button signal or toggle switch). If the player pushes at the correct time, the direction of the shift should be reversed and the ball should move toward to the left. The left-hand player must then the volley by pressing his button (toggle switch) when the ball is in its leftmost position. If a player presses his push button (toggle switch) too soon or too late, the ball should disappear at the end. When this happens, the player who has scored should be able to restart the game (serve) by pressing his push button (toggle switch).
OPTIONS
A number of options can be provided to make the game more interesting.
First of all, provide a number of different rates at which the ball can move. The rate of ball movement should be selected automatically as each player return a volley. The rate selected should be a function of how the volley is returned, perhaps with the fastest rate selected when the volley is returned at the last possible moment. To implement this feature you will need control circuitry to select a rate, a register to store the rate, and a counter to generate the different rates.
A second option is to keep score. Each player’s score should be kept in a 4-bit counter. The 4-bit scores should be displayed in the lights whenever the ball is out of play.
c. Student Proposal :-)
11. IC Symbol & Pin-Outs
