systemverilog uvm student workbook · this document is for information and instruction purposes....

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SystemVerilog UVM

Student Workbook

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Table of Contents

SystemVerilog UVM I

Module 1: Course Overview ................................................................................. 13

Objectives ........................................................................................................................................... 14

Why Learn UVM? .............................................................................................................................. 15

How This Course Makes Sense of UVM ........................................................................................... 16

Course Flow ....................................................................................................................................... 17

Introductions and Expectations .......................................................................................................... 18

Course Labs ........................................................................................................................................ 19

Examples & Labs Emphasize Scalable Best Practices ....................................................................... 20

Module 2: First Look At SystemVerilog UVM ................................................... 21

Objectives ........................................................................................................................................... 22

Course Glossary ................................................................................................................................. 23

Verification Methodologies ................................................................................................................ 24

What is UVM? ................................................................................................................................... 25

UVM Evolution .................................................................................................................................. 26

UVM as a Complete Methodology .................................................................................................... 27

What UVM Provides .......................................................................................................................... 28

SystemVerilog OOP Techniques in UVM ......................................................................................... 30

UVM Topology .................................................................................................................................. 31

Agent .................................................................................................................................................. 32

UVM Class Hierarchy ........................................................................................................................ 33

UVM Reporting/Messaging ............................................................................................................... 34

Verification Phases ............................................................................................................................. 35

UVM Phases ....................................................................................................................................... 36

Hello World Example ......................................................................................................................... 38

Table of Contents

SystemVerilog UVM II

UVM Overview Example ................................................................................................................... 39

Simple Transaction ............................................................................................................................. 40

Simple Driver ..................................................................................................................................... 41

Generating Stimulus ........................................................................................................................... 42

An Agent Bundles Protocol Classes ................................................................................................... 43

Testbench Environment ...................................................................................................................... 44

Test Class ........................................................................................................................................... 45

Packages ............................................................................................................................................. 46

Running the Test ................................................................................................................................ 47

Connecting Testbench and DUT: Dual Top ....................................................................................... 48

Knowledge Check .............................................................................................................................. 49

Configuration Classes ........................................................................................................................ 50

The UVM Factory .............................................................................................................................. 51

UVM Factory Introduction ................................................................................................................. 52

Viewing Topology .............................................................................................................................. 53

Printing Messages in UVM ................................................................................................................ 54

Message Verbosity ............................................................................................................................. 55

Message Tips ...................................................................................................................................... 56

UVM Source Code and Documentation ............................................................................................. 57

Debugging UVM Testbenches ........................................................................................................... 58

Learning UVM ................................................................................................................................... 59

Module 2 Lab: UVM First Look ........................................................................................................ 60

Questa SIM 10.6 Quick Guide ........................................................................................................... 61

Lab Instructions .................................................................................................................................. 63

Description of Lab Environment ........................................................................................................ 64

Table of Contents

SystemVerilog UVM III

Knowledge Check Answers ............................................................................................................... 70

Supplemental Information .................................................................................................................. 71

UVM Reporting .................................................................................................................................. 72

Module 3: Transactions and Sequences .............................................................. 77

Objectives ........................................................................................................................................... 78

Transactions and Sequences ............................................................................................................... 79

UVM Terminology and Class Hierarchy ........................................................................................... 80

UVM Stimulus Built From Sequence Items ...................................................................................... 81

What's Inside Your Transaction? ....................................................................................................... 82

Sequence Item Coding Styles ............................................................................................................. 83

Transaction Methods .......................................................................................................................... 84

Each Transaction Method Calls a Virtual Method ............................................................................. 85

Implementing the Transaction do_*() Methods ................................................................................. 87

The do_copy() Method ....................................................................................................................... 88

The do_compare() Method ................................................................................................................. 89

The convert2string() Method ............................................................................................................. 90

The do_print() Method ....................................................................................................................... 91

Pack, Unpack, Record ........................................................................................................................ 92

Extended Transaction Classes ............................................................................................................ 93

Best Practices with do_* Methods ..................................................................................................... 94

Knowledge Check - Transactions ...................................................................................................... 95

Building Stimulus From Transactions ................................................................................................ 96

UVM Sequences ................................................................................................................................. 97

Handshaking Between Test/Sequence/Driver .................................................................................... 98

Generating Multiple Transactions ...................................................................................................... 99

Table of Contents

SystemVerilog UVM IV

Randomized Sequences .................................................................................................................... 100

Complex Sequences ......................................................................................................................... 101

Knowledge Check - Sequences ........................................................................................................ 102

Module 3 Lab: Define Transactions and Sequences ........................................................................ 103

Lab Instructions ................................................................................................................................ 104

Knowledge Check Answers - Transactions ..................................................................................... 108

Knowledge Check Answers - Sequences ......................................................................................... 109

Supplemental Information ................................................................................................................ 110

Review: SystemVerilog Class Randomization ................................................................................ 111

Review: SystemVerilog Constraints ................................................................................................ 112

Each Transaction Method Calls Two Virtual Methods .................................................................... 113

Macros – When You Want It Now ................................................................................................... 114

Common `uvm_field_* Macros ....................................................................................................... 115

Field Macro Control Flags ............................................................................................................... 116

Module 4: Sequencers, Drivers, and TLM ........................................................ 117

Objectives ......................................................................................................................................... 118

Communication Between Components ............................................................................................ 119

TLM Communication ....................................................................................................................... 121

TLM Pull Port Flow ......................................................................................................................... 122

Sequencers, Drivers and Interfaces .................................................................................................. 123

Review: Using SystemVerilog Interfaces ........................................................................................ 124

The Role of Sequencers and Drivers ................................................................................................ 125

Example UVM Driver ...................................................................................................................... 126

Connecting the Driver and Sequencer .............................................................................................. 127

Emulation Friendly Drivers .............................................................................................................. 128

Table of Contents

SystemVerilog UVM V

Handshaking Between Test/Sequence/Driver .................................................................................. 130

Associating a Sequence with a Sequencer ....................................................................................... 131

Knowledge Check ............................................................................................................................ 132

Module 4 Lab: Define a Sequencer and Driver ................................................................................ 133


Knowledge Check Answers ............................................................................................................. 136

Module 5: Monitors and Agents ........................................................................ 137

Objectives ......................................................................................................................................... 138

UVM Monitors ................................................................................................................................. 139

Monitoring Ins and Outs .................................................................................................................. 140

Capturing Scoreboard and Coverage Collector Values .................................................................... 141

Communication Between Components ............................................................................................ 142

TLM Analysis Port Flow .................................................................................................................. 143

Monitor Example .............................................................................................................................. 144

Whose write() Method? .................................................................................................................... 146

UVM Agents .................................................................................................................................... 147

Multiple Agents ................................................................................................................................ 148

Active and Passive Agents ............................................................................................................... 149

UVM Testbench With Active and Passive Agents .......................................................................... 150

Analysis Port Connections ............................................................................................................... 151

Example: Analysis Ports .................................................................................................................. 152

Knowledge Check ............................................................................................................................ 154

Module 5 Lab: Monitors and Agents ............................................................................................... 155



Table of Contents

SystemVerilog UVM VI

Module 6: Coverage Collectors .......................................................................... 159

Objectives ......................................................................................................................................... 160

Review: SystemVerilog Functional Coverage ................................................................................. 161

Project Coverage Flow ..................................................................................................................... 167

UVM Coverage ................................................................................................................................ 168

Covering Transactions ...................................................................................................................... 169

What Should be Covered? ................................................................................................................ 170

Coverage Collector Example ........................................................................................................... 171

Connecting the Coverage Collector ................................................................................................. 173

Debugging Coverage ........................................................................................................................ 174

Knowledge Check ............................................................................................................................ 175

Module 6 Lab: Define a UVM Coverage Collector ......................................................................... 176



Module 7: Scoreboards and Environments ...................................................... 181

Objectives ......................................................................................................................................... 182

Review: TLM Analysis Connections ............................................................................................... 183

Introduction to Scoreboards ............................................................................................................. 184

Scoreboard Progression .................................................................................................................... 185

Scoreboard Storage .......................................................................................................................... 186

Copy On Write (COW) .................................................................................................................... 187

Two UVM Scoreboard Examples .................................................................................................... 188

Scoreboard TLM Communication ................................................................................................... 189

Ex1: ALU Predictor, Internal to Scoreboard .................................................................................... 190

Ex1: Evaluator for the ALU with FIFO Ports for Storage ............................................................... 191

Table of Contents

SystemVerilog UVM VII

Ex1: Scoreboard for the ALU example ............................................................................................ 193

Ex1: Environment for the ALU example ......................................................................................... 194

Ex2: Scoreboard with Multiple Analysis Imp Exports .................................................................... 195

UVM Environments ......................................................................................................................... 199

An Example UVM Environment ...................................................................................................... 200

Knowledge Check ............................................................................................................................ 201

Module 7 Lab: Scoreboards and Environments ............................................................................... 202

Lab Diagram ..................................................................................................................................... 203



Module 8: Configuration and Factory .............................................................. 207

Objectives ......................................................................................................................................... 208

Configurable Test Environments ..................................................................................................... 209

Passing Information Across the Topology ....................................................................................... 210

The UVM Configuration Database .................................................................................................. 211

UVM Configuration Database Example .......................................................................................... 216

Configuration Class Example ........................................................................................................... 217

Configuration Flow .......................................................................................................................... 218

Setting Configuration from Command Line .................................................................................... 224

Performance Considerations ............................................................................................................ 225

Configuring Sequences .................................................................................................................... 226

Component Arrays ........................................................................................................................... 228

Debugging UVM Configuration Database ....................................................................................... 229

UVM Factory Introduction ............................................................................................................... 230

Creating Objects With the Factory ................................................................................................... 231

Table of Contents

SystemVerilog UVM VIII

Registering Classes in the Factory ................................................................................................... 232

Factory Override .............................................................................................................................. 233

The Benefits of Factory Overrides ................................................................................................... 236

Module 8 Lab: Configuration and Factory ....................................................................................... 237



The UVM Configuration Database Priority ..................................................................................... 242

UVM Configuration exists() and wait_modified() Methods ............................................................ 243

Configuring Sequences Without Referring to a Sequencer ............................................................. 244

Viewing the Configuration Database Contents ................................................................................ 245

Controlling Tests From the Command Line .................................................................................... 246

Printing the Factory Contents ........................................................................................................... 247

Viewing the UVM Testbench Topology .......................................................................................... 248

Module 9: Tests and Virtual Sequences ............................................................ 249

Objectives ......................................................................................................................................... 250

UVM Test Class ............................................................................................................................... 251

UVM Test Class Example Code ...................................................................................................... 253

Project-Level Base Classes .............................................................................................................. 254

Delaying the End of Run Phase ........................................................................................................ 256

Knowledge Check 1 ......................................................................................................................... 259

Review: Test and Sequence Handshaking ....................................................................................... 260

Controlling Multiple Sequences ....................................................................................................... 261

Virtual Sequences and Running Multiple Sequences ...................................................................... 262

Acquiring a Sequencer Handle for a Sequence ................................................................................ 263

Sequencer Handle in a Configuration Object ................................................................................... 264

Table of Contents

SystemVerilog UVM IX

Configuration Objects in the Virtual Sequence ................................................................................ 268

Project-Level Base Classes .............................................................................................................. 269

Knowledge Check 2 ......................................................................................................................... 270

Module 9 Lab: Tests, and Virtual Sequences ................................................................................... 271


Knowledge Check Answers 1 .......................................................................................................... 274

Knowledge Check Answers 2 .......................................................................................................... 275


Sequencer Handle Connection Approaches ..................................................................................... 277

Sequence Handle Declarations ......................................................................................................... 281

Sequencer Example – The Environment .......................................................................................... 282

Virtual Sequencer Example – The Virtual Sequence ....................................................................... 283

Virtual Sequencer Example – The Test ............................................................................................ 284

Module 10: Sequences for Complex Stimulus .................................................. 285

Objectives ......................................................................................................................................... 286

Multiple Agents and Sequencers ...................................................................................................... 287

Virtual Sequence Starts Sequences on Both Agents ........................................................................ 288

A Virtual Sequence for Multiple Agents .......................................................................................... 289

Passing Information Into a Sequence ............................................................................................... 290

Parallel Multiple Sequences on the Same Sequencer ....................................................................... 292

Sequencer Arbitration ...................................................................................................................... 293

Selecting Sequencer Arbitration Algorithm ..................................................................................... 294

Setting Sequence Priority ................................................................................................................. 295

Exclusive Sequencer Access ............................................................................................................ 296

Generating Multiple Transactions in a Sequence ............................................................................. 297

Table of Contents

SystemVerilog UVM X

Parallel Sequence Gotchas ............................................................................................................... 298

Sequence Libraries and Hierarchical (Layered) Sequences ............................................................. 299

Driver/Sequence: get_next_item() and get() .................................................................................... 300

Feedback to Sequence: Same Transaction Object ............................................................................ 301

Feedback to Sequence: Different Transaction Objects .................................................................... 302

Knowledge Check ............................................................................................................................ 303

Module 10 Lab: Sequences for Complex Stimulus .......................................................................... 304



Feedback to Sequence: Driver Analysis Port ................................................................................... 307

Sequence Macros .............................................................................................................................. 308

Module 11: UVM Register Layer Overview ..................................................... 309

Objectives ......................................................................................................................................... 310

Advantages of the UVM Register Layer .......................................................................................... 311

UVM Register Layer Components ................................................................................................... 313

UVM Register Model ....................................................................................................................... 314

UVM Register Models Working with Bus Agents .......................................................................... 315

UVM Register Model Hierarchy ...................................................................................................... 316

Software Tools Generate UVM Register Models ............................................................................ 317

Register Model Integration ............................................................................................................... 318

UVM Register Values ...................................................................................................................... 319

Register Adapter ............................................................................................................................... 320

Register Prediction ........................................................................................................................... 321

Adding a Register Model to a Test ................................................................................................... 322

Integrating a Register Model ............................................................................................................ 323

Table of Contents

SystemVerilog UVM XI

User-defined Register Tests (Sequences) ......................................................................................... 325

UVM Register Access Methods ....................................................................................................... 326

Tests with User Defined Register Sequences ................................................................................... 328

Predefined Register Test Sequences ................................................................................................ 329

Test for a Predefined Register Sequence .......................................................................................... 330

Knowledge Check ............................................................................................................................ 331

Module 11 Lab: UVM Register Layer ............................................................................................. 332




Example Generated Register ............................................................................................................ 336

Example Generated Register Block ................................................................................................. 337

Module 12: UVM Summary ............................................................................... 339

Objectives ......................................................................................................................................... 340

What is the Other 97% ..................................................................................................................... 341

Advanced UVM Techniques ............................................................................................................ 342

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