systematic design for a successive approximation adc
TRANSCRIPT
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Systematic Design for a Successive
Approximation ADCMootaz M. ALLAM
M.Sc– Cairo University - Egypt
Supervisors
Prof. Amr Badawi
Dr. Mohamed Dessouky
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• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
Outline
2
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• Emerging new Applications▫ MEMS Sensor Interface:
Resolution: 7-8 bits, BW=50kHz [Scott 2003]
▫ Multi-standards RF receiverResolution: 8 bits, BW = 20 MHz [Montaudon 2008]
▫ Ultra Wide Band (wireless UWB): Resolution: 5-6 bits, BW=300MHz [Chen 2006]
3
The Successive Approximation ADC
« The Return»
Moderate Resolution
Low Power
Minimum Active blocs
Reconfigurable
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Figure of Merit
ResolutionFOM
2 *2*
P
BW
4
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Objectives
5
▫ Develop a systematic design method for successive approximation ADC from system to layout level .
▫ Develop a general simulation environment with different levels of abstraction and programmed performance analysis.
▫ Emphasis on analog design automation and reuse techniques:
Automatic sizing
Layout generation
▫ Optimizing Layout for best matching
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Principle of Operation
6
MSB
LSB1 1 0 0Comp
1 2 3 42 4 8 16
REF REF REF REFV V V VVin b b b b
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Outline
• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
7
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Single Ended SAR-ADC.
8
2
REFV REFV
REFV
REFV
inv
8C 4C 2C C C Clock
sample
sample
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Sampling Mode
9
REFV
REFV
inv
8C 4C 2C C C Clock
sample
samplesample
invert
Clock
2
REFV Re fV
REFV
VDAC
VDACVIn
VIn
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Inversion Mode
10
sample
invert
Clock
gnd
REFV
REF INV v
8C 4C 2C C C Clock
invertREFV
VDAC
REFV vin
VDAC =
INv
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Charge redistribution mode (MSB)
11
sample
invert
ClockREFV
2
REFREF
VV vin
8C 4C 2C C C Clock
REFV2
REFINITIAL
VV8C
8C
REFV
REFV
2
REFV
1
VDAC=
VDAC
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Charge redistribution mode (MSB-1)
12
sample
invert
ClockREFV
2 4
REF REFREF
V VV vin
8C 4C 2C C C Clock
REFV4
REFINITIAL
VV
4C
12C
REFV
REFV
4
REFV
1 0
VDAC =
VDAC
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Mode Redistribution de la charge (MSB-2)
13
sample
invert
ClockREFV
2 8
REF REFREF
V VV vin
8C 4C 2C C C Clock
REFV
REFV
8
REFV
REFV
1 0 1
VDAC =
VDAC
1 2 3 42 4 8 16
REF REF REF REFV V V VVin b b b b
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Mode Redistribution de la charge (LSB)
14
sample
invert
ClockREFV
2 8 16
REF REF REFREF IN
V V VV v
8C 4C 2C C C Clock
REFV
REFV
16
REFV
REFV
1 0 1 0
VDAC =
VDAC
1 2 3 42 4 8 16
REF REF REF REFV V V VVin b b b b
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Problem
15
ddV
Sometimes DAC ddV V
8C 4C 2C C C Clock
ddV
ddV
ddV
Leakage when using normal PMOS switch.
Possible Solution: Switched charge-pump [scott03] or Bootstrap [dessouky01]
Selecting To increase the dynamic rangeREF ddV V
DACV ddV
ddV
ddV
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Possible solutions - Leakage
16
Bootstrap Switch Charge pump Switch
0 < VDAC < 1.5 VDD
VDAC
VDAC
VDD
Since sometimes VDAC value=1.5 VDD
While VG1 = 0 when M1 is ON, VGD,M1 exceeds VDD
Reliability problem
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Possible solutions - Reliability
17
0 < VDAC < 1.5 VDD
Shielding Switch
Max OFF = VDD - Vtn
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Possible solutions - Circuitry
18
Bootstrap [dessouky01] Modified Shielding
Bootstrap
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Differential SAR-ADC
19
2
ddV ddV2
inv
4C 2C C CClock
sample
sample
2
inv
4C 2C C C
2
ddV ddV
2
ddV
2
ddV
Triple Reference
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Differential SAR-ADC
20
sample
invert
Clock
2
ddV
DAC1
In1
2
ddV
4C 2C C CClock
4C 2C C C
DAC2
ddV
In2
2
ddV
2 2 4 8 16
dd dd dd ddV V V Vvin
2 2 4 8 16
dd dd dd ddV V V Vvin
1 0 1 0
ddV
ddV 2
ddV
4C 2C C CClock
ddV
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Operation – Summary
21
Single Ended Double reference Differential Triple reference
2 times the numbers of capacitors6 times the numbers of switches
Special Switch (charge-pump - bootstrap)
No need for special switch
Differential architectures advantages : - Suppressing even harmonics-Common mode rejection-Offset removal
Lower power consumption Better performance at high frequencies
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Outline
• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
22
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Design - Architecture
23
Capacitor array
Comp
ControlSAR
Clock
Switches Control
Switches
In
Sample invert
Capacitor array
Switches
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Capacitor array design issues - Noise
24
ddV
ddV
inv
8C 4C 2C C C Clock
sample
sample
C increases, thermal noise decreasesUnit
16TOTC C
ddV
SwitchRinv
1- Thermal noise [ ], due to SamplingTOT
kT
C
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Capacitor array design issues - Mismatch
25
2 Capacitor Mismatch (Introduced in fabr ication)
- Affects Generated comparison levels of the capacitve DAC
2
ddV8( )C C
8C
ddV
C increases, mismatch effect decreasesUnit
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Capacitor array design issues -
26
16TOTC C
ddV
SwitchRinv
Switch TotalR C
sample
Clock
For an accurate sampling2
Clocksampling
Tt
Samplingf
3- Sampling Frequency
C decreases, bandwidth increasesUnit
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Switches
27
• NMOS to switch Vgnd and Vcm
• PMOS to switch Vdd
• CMOS to switch Vin
• Bootstrap to force deep off-state of critical switches
1) Switches selection
2) Sizing switches (compromise)
• Increasing W/L reduces Rswitch and so , on the account of
increasing switch parasitcs.
• In the used DAC, this will be of minor importance if operating in
low frequency because the switches are all connected to the
bottom plates
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Design - Architecture
28
Capacitor array
Comp
ControlSAR
Clock
Switches Control
Switches
In
Sample invert
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29
ep
Qm
h h
hh
em
MP7 MP8
MN5 MN6
MN1 MN2
MP9 MP11
MN3 MN4
Qp
Cuts the current path
in the RESET phase
Reset to Vdd
Comparator Circuit
Input Signal
Latch
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30
Comparison phaseReset phase to Vdd
Latch starts Inputs
Comparator – Operation phases
Resolution > 2
LSBV
Response time < 0.5 TH
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31
Sizing input pair and latch
Improve with decreasing L
Tradeoff
Comparator – Design tradeoff
Improve with increasing L
initlatchTotalI offsetV
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Design - Architecture
32
Capacitor array
Comp
ControlSAR
Clock
Switches Control
Switches
In
Sample invert
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33
LFSR: Linear Feedback Shift Register
DAC outputs C
0 0 0 0 0 0 0 0 0 X
1 1 0 0 0 0 0 0 0 a8
2 a8 1 0 0 0 0 0 0 a7
3 a8 a7 1 0 0 0 0 0 a6
4 a8 a7 a6 1 0 0 0 0 a5
5 a8 a7 a6 a5 1 0 0 0 a4
6 a8 a7 a6 a5 a4 1 0 0 a3
7 a8 a7 a6 a5 a4 a3 1 0 a2
8 a8 a7 a6 a5 a4 a3 a2 1 a1
SAR algorithm - Implementation
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Systematic design for SA-ADC
34
Resolution – BW – Power - Techno
Non idealities and noise Thermal noise, mismatch, …
Cmax >Cmin
Switches Sizing
Yes
No
Clock frequency
Cmax
C unity = C min
Sizing procedure
System architectureDAC topology, SAR algorithm, Sampling technique
Cmin
Comparator specsSettling, resolution, kickback….
Select number of stages
Check Specs
Layout
No No
Yes
Finalize design
No
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Outline
• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
35
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Case Study
36
• Case Study▫ Differential Architecture
▫ Resolution: 8bit
▫ BW: 50 KHz
▫ Fclock: 1MHz
▫ Technology: 0.13u ST, MIM Capacitors
• Verification▫ VHDL AMS used for verification with simulation
▫ Different levels of abstraction (Behavioral , gates, transistor, …)
▫ Mixed blocs simulation (Analog / Digital)
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Multiple abstractions
37
Capacitor array Comp
+ Latch
ControlIn
Switches
Macro
model
Macro
model Transistor
Transistor
MIM
VHDLMacro
model
Clock gen VHDLTransistor
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Verification Environment
38
Resolution – BW
Sketch output spectrum
Verification Environment presetsDAC topology, SAR algorithm, Sampling technique
Abstraction levelIdeal, mismatched, techno, …
Component sizes
Type of analysis
Calculate SNDR
Sketch SNDR v.s. fin
Sketch SNDR v.s. Ain
Sketch INL and DNL
Sketch Transient response at each node
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Transiant – Single Ended - Output
39
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Transistor level simulations
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Transiant – Differential - Output
40
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Transistor level simulations
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Transiant – Differential - DACs
41
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Differential DACs outputTransistor level simulations
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Transiant – Differential - Comparator
42
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Full conversion: Differential DACs output – Comparator outputTransistor level simulations
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Transient – SAR control
43
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
VHDL DescriptionControl block turning ON and OFF DAC switches [case of 0 input]
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Transient – Full Scale Ramp
44
Full Scale Slow ramp excitation
Vinp-p 1.2V
Zoom - in
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Static Performance - Transistor Level
45
Static performance Evaluation in (LSB): DNL and INL [16 sample / bin]
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Dynamic Performance – Ideal Models
46
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
SNDR = 47.47 dB
4096 point FFT
Ideal models simulation
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SNDR = 47.44 dBSNDR = 47.47 dB
SNDR = 46.78 dB SNDR = 46.69 dB
Dynamic Performance – Mixed Models
47
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
4096 point FFT
Ideal MOS
switches
MOS
comparator
0.01
mismatch
in Cu
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Dynamic Performance – Transistor Level
48
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
1024 point FFT
Pow
er
Specra
l D
ensity (
dB
)
Frequency (Hz)
SNDR = 46.2 dB
Transistor level simulations
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49
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
SNDR max
Ideal =47.47 dB
Transistor Level = 46.2
Sig
nal to
nois
e a
nd d
isto
rtio
n r
atio S
ND
R(d
B)
Amplitude of input signal(dB)
4096 point FFT
Transistor level simulations
Dynamic Performance
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50
Vdd 1.2V
Fclk 1MHz
Vinp-p 1.2V
BW =55 KHz
Sig
nal to
nois
e a
nd d
isto
rtio
n r
atio S
ND
R(d
B)
4096 point FFT
Transistor level simulations
Dynamic Performance
Frequency of input signal (Hz)
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Mismatch analysis
51
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
4096 point FFT
0.1
mismatch
in Cu
0.05
mismatch
in Cu
SNDR = 46.36 dB SNDR = 44.13 dB
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Layout generation for SA-ADC
52
Comparator transistor sizes
Unit capacitance
Common centroidplacement algorithm
Desired layout shape
Layout template s-Component connectivity-Relative place and route
CAIRO Layout generation
DRC – LVS
Design phaseNumber of
capacitors and sizes
Target technology
Verification
Parasitics Ext.
Fabrication
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Layout – Comparator - Floorplan
53
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Layout – Comparator - Generated
54
Dummies Removed for Layout verificationArea 22 x 39 µm2
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Layout – Differential DACs - Floorplan
55
Common centroid placement for 16 capacitor
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Layout – Differential DACs - Generated
56
Layout 1 - 256 Cu – Placed and Routed – Area
1.26 x 0.26 mm2 and Huge routing parasitics
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Layout – Differential DACs - Manual
57
Layout 2 - 256 Cu – Placed
and Routed – 2/3 less
routing parasitics
ZOOM
Area 0.1056 mm2
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Performance
58
[Hong07] This work* [scott03]
Technology 0.18 µm 0.13 µm 0.25 µm
Supply 0.83 V 1.2 V 1.0 V
Input range Rail to Rail Rail to Rail Rail to Rail
Sampling rate 111 KHz 111 KHz 100 KHz
Unit Cap. 24 fF 30fF 12f
Power (Analog) 1.16 µW 0.72µW 2.2 µW
Area 0.062 mm2 0.122 mm2 0.053 mm2
SNDR@BW 47.40 dB 46.2dB 43.8 dB
Architecture Single Ended Differential Single Ended
FOM 65 fJ/bit 64fJ/bit 2163 fJ/bit
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Outline
• Background
• Principles of Operation
• System and Circuit Design
• Case Study
▫ Simulations
▫ Layout Generation
▫ Performance Evaluation
• Conclusion
• Perspectives
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Summary and Conclusion
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▫ Systematic design methodology for SA-ADC from
system to layout.
▫ General simulation environment
▫ Different abstraction levels.
▫ Different verification tests.
▫ Emphasis on analog design automation and reuse
▫ Optimizing Layout for best component matching
▫ Verification with case study for WSN specs
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Perspectives
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▫ Targeting high frequency specs (>500 Msample/S) Redundant system error correction code [Kuttner02]
Digital calibration [Promitzer01]
Asynchronous operation [Chen06]
Time interleaving [Chen06]
▫ Full Automation Sizing procedure with layout parasitics awareness
Layout generation for the full ADC
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Thank You
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