System on Chip Implementation for Electrical ImpedanceTomography

Arun Rao, Yueh-Ching Teng, and Kofi Odame

IntroductionSystem on Chip (SoC) hardware implementations for electrical impedance tomography (EIT) are key to address high frequency operation (up to 10MHz), where electrical impedance of intracellular physiologyprovides increased contrast between benign and cancerous tissues. We present an SoC implementation for EIT which includes CMOS wideband current conveyor based current source for tissue excitation,a fixed gain instrumentation amplifier (IA) and variable gain amplifier (VGA) with large output swing and common mode attenuation, followed by a 10-bit SAR ADC on a single chip in the XFAB 0.18µmtechnology. The design enables realization of wideband, small form factor, multiple electrode EIT systems.

1 Channel Core Block Diagram Die Photo and Measurement PCB Description

v Chip with Current Driver, Instrumentation Amplifier

(IA), Variable Gain Amplifier (VGA) and SAR ADC was

fabricated in 0.18µm technology.

v Performance of individual blocks was measured with

custom built PCB’s (shown in the sections below).

v A 4 channel SoC comprising of the individual blocks

measured from the 1- channel SoC is currently sent for

fabrication.

v Simulation results for the 4 Channel SoC with an experi-

mental setup is shown in the concluding section.

4 Channel SoC

10MHz CMOS Current Driver : Measured ResultsOutput Current vs Frequency

102

103

104

105

106

107

frequency (Hz)

0

0.5

1

1.5

Cu

rren

t (A

)

10-3

Iinj

= 10 A Iini

= 300 A Iinj

= 600 A Iinj

= 1mA Iinj

= 1.2mA

THD vs Frequency

102

103

104

105

106

107

frequency (Hz)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

TH

D (

%)

IZ

= 1 mA

IZ

= 1.2 mA

Output Impedance vs Frequency

104

105

106

107

frequency (Hz)

104

105

106

107

Ou

tpu

t Im

ped

an

ce (

)

Current Source Specifications

Parameter This Work

Bandwidth 100Hz - 10MHz

Output

Impedance

101kΩ @ 1MHz,

19.5kΩ @ 10 MHz

Max. Output

Current1.2mA

THD(frequency)< 0.7% @

1.2mA(10MHz)

Voltage

Compliance0.7 V

Instrumentation Amplifier (IA) : Measured ResultsFrequency Response CMRR vs Frequency THD vs Frequency IA Specifications

Parameter This Work

Bandwidth 100Hz - 10MHz

Current

Consumption

(Core)

549µA

Input Impedance

(DC)> 1GΩ

Supply Voltage 3.3 V

Variable Gain Amplifier (VGA) : Measured ResultsFrequency Response CMRR vs Frequency THD vs Frequency VGA Specifications

Parameter This Work

Bandwidth 100Hz - 10MHz

Current

Consumption

(Core)

1.274mA

Input Impedance

(DC)> 1GΩ

Supply Voltage 3.3 V

4 Channel SoC Implementationv This SoC includes the sense resistor for accurate current measurement, and associated control switches for control sequence of iivv patterns on chip to reduce PCB footprint.v An experimental Wheatstone Bridge setup is designed to verify the 4-channel SoC. Here we verify the simulation results against the impedance equation corresponding to theiivv pattern at 1 MHz.v Chip simulation results are performed in Virtuoso Cadence. The simulation include the core circuits and the pads. The layout of the 4 channel SoC is shown.

Wheatstone Bridge Setup with Impedance Equations

Impedance Equations: iivv Patterns

v iivv1234 : Z1234 =Ve3−Ve4

0.0952∗Ie1

v iivv1342 : 2 ∗ Z1342 =Ve2−Ve4

0.1905∗Ie1

v iivv2413 : 2 ∗ Z2413 =Ve1−Ve3

0.1905∗Ie2

Simulation Results @ 1MHz

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

time (s) 10-6

101

102

103

104

105

Imp

ed

an

ce (

)

iivv1234

iivv1342

iivv2341

Layout of 4 Channel SoC

v ACKNOWLEDGEMENT :Supported by funding from the CDMRP, under Grant Agreement W81XWH-15-1-0571.