System-level Design of Embedded Systems

Franco FummiFranco Fummi

franco.fummi@univr.itfranco.fummi@univr.it

Dip.di InformaticaDip.di Informatica

Università di VeronaUniversità di Verona

Donatella SciutoDonatella Sciuto

sciuto@elet.polimi.itsciuto@elet.polimi.it

Dip. di ElettronicaDip. di Elettronica

Politecnico di MilanoPolitecnico di Milano

22

Contents

�� Hw/Hw/SwSw Systems DescriptionSystems Description�� embedded systemsembedded systems

�� ArchitectureArchitecture�� Simulation problemSimulation problem�� Modeling problemModeling problem�� Current solutionCurrent solution�� Hw/Hw/SwSw Synthesis Synthesis �� Hw Performance EvaluationHw Performance Evaluation�� SwSw Performance EvaluationPerformance Evaluation�� The role of R.T.O.S.The role of R.T.O.S.

33

Introduction

�� Electronic systems consist of:Electronic systems consist of:�� HW platformHW platform�� SW application layersSW application layers�� InterfacesInterfaces�� Analog componentsAnalog components�� Sensors and transducersSensors and transducers

�� Main trends: Main trends: �� Migration from analog to digital processingMigration from analog to digital processing�� Broader systemBroader system--level integration to support level integration to support

SystemSystem--OnOn--aa--Chip (SOC) approachChip (SOC) approach

Challenges in the design of embedded systems

�� increasing application complexity even in standard increasing application complexity even in standard and large volume productsand large volume products

�� large systems with legacy functionslarge systems with legacy functions�� mixture of event driven and data flow tasks mixture of event driven and data flow tasks �� flexiblityflexiblity requirements requirements �� examples: multimedia, automotive, mobile communication examples: multimedia, automotive, mobile communication

�� increasing target system complexityincreasing target system complexity�� mixture of different technologies, processor types, and design mixture of different technologies, processor types, and design

stylesstyles�� large systemslarge systems--onon--aa--chip combining components from chip combining components from

different sources (IP market)different sources (IP market)

�� numerous constraints and design objectivesnumerous constraints and design objectives�� reduced and over lapping design cyclesreduced and over lapping design cycles

Hardware/software codesign

�� Hardware/software coHardware/software co--design: design: Combined design of hardware and softwareCombined design of hardware and software

�� GoalsGoals�� design process optimization design process optimization

�� Increased design productivityIncreased design productivity�� design optimizationdesign optimization

�� Improved product qualityImproved product quality

�� TasksTasks�� coco--specification and cospecification and co--modelingmodeling�� coco--verificationverification�� coco--design process integration and optimizationdesign process integration and optimization�� design optimization and codesign optimization and co--synthesissynthesis

HW SW HW SW

co-design classic design

66

Co-design advantages

�� Explore different design alternatives in the Explore different design alternatives in the architectural design spacearchitectural design space

�� Tune HW to SW and viceTune HW to SW and vice--versaversa�� Reduce the system design timeReduce the system design time�� Support coherent design specification at the Support coherent design specification at the

systemsystem--levellevel�� Facilitate the reFacilitate the re--use of HW and SW partsuse of HW and SW parts�� Provide integrated environment for the Provide integrated environment for the

synthesis and validation of HW and SW synthesis and validation of HW and SW componentscomponents

77

Digital system classification

APPLICATION DOMAINComputerTelecom

Automotive

SYSTEM TYPEGeneral-Purpose Systems

Embedded Systems

PROGRAMMABIL ITYApplication-levelInstruction-levelHardware-level

IMPLEMENTATIONTechnologyDesign style

Level of integration

88

Co-design of embedded systems

�� Design of Design of dedicateddedicated computing and control computing and control systemssystems

�� Embedded controllersEmbedded controllers�� OnOn--line control of manufacturing processline control of manufacturing process�� Robots guidance and controlRobots guidance and control�� Aircraft, automobile and ship controlAircraft, automobile and ship control

�� Data processing and communication Data processing and communication systemssystems�� TelecomTelecom�� RadioRadio--navigationnavigation

99

Co-design of embedded systems

�� Design of dedicated Design of dedicated HW partsHW parts

�� Different design styles:Different design styles:�� CoCo--processors, embedded cores, processors, embedded cores, ASIPsASIPs, ..., ...

�� Widely varying design scaleWidely varying design scale

�� Design of dedicated Design of dedicated SW partsSW parts

�� SpecialSpecial--purpose operating systemspurpose operating systems

�� Drivers of peripheral devicesDrivers of peripheral devices

1010

Embedded systems

ENVIRONMENT

MEMORY ISP

HARDWIRED UNITApplication-specific logic

TimersA/D and D/A Converters

SEN

SOR

S

AC

TU

AT

OR

S

EMBEDDED SYSTEM

1111

Array-based design

�� PrePre--Diffused Array or Mask Programmable Diffused Array or Mask Programmable Gate Array Gate Array (MPGA)(MPGA)

�� PrePre--Wired Array or Field Programmable Wired Array or Field Programmable Gate Array Gate Array (FPGA)(FPGA)

�� SoftSoft--Programmable (Memory based)Programmable (Memory based)

�� HardHard--Programmable (AntiProgrammable (Anti--fuse based)fuse based)

1212

Integration level

�� Single chip systems (SOC approach):Single chip systems (SOC approach):�� ASICsASICs with embedded cores and memorieswith embedded cores and memories�� Cores (microprocessor, microcontroller, DSP, ...)Cores (microprocessor, microcontroller, DSP, ...)

�� Multiple chip systems:Multiple chip systems:�� ASICsASICs, , FPGAsFPGAs, …, …�� MemoriesMemories�� Programmable components such as processors, Programmable components such as processors,

DSPsDSPs or controllersor controllers�� OffOff --thethe--shelf or proprietary componentsshelf or proprietary components

�� Distributed systemsDistributed systems

1313

Comparison

IP ASIP ASIC

Performance + ++ +++

Pow er +++ ++ +

Reuse +++ ++

HW design effort ++ +++

SW design effort + ++

1414

Embedded system requirements

�� Reactive Reactive systems:systems:�� The system never stopsThe system never stops

�� The system responds to signals produced by the The system responds to signals produced by the environmentenvironment

�� RealReal--time time systems:systems:�� Timing constraints on task evolutionTiming constraints on task evolution

�� Hard and soft constraintsHard and soft constraints

1515

Specific steps in embedded control design

�� Architecture selection:Architecture selection:

�� Standard microcontroller or microprocessorStandard microcontroller or microprocessor

�� ASICASIC

�� ASIC with embedded core or coASIC with embedded core or co--processorprocessor

�� Technology selection for HW resourcesTechnology selection for HW resources

�� Design dedicated HW, SW and interfacesDesign dedicated HW, SW and interfaces

1616

Co-design flow of embedded systems

�� Modeling, validation and synthesisModeling, validation and synthesis�� SystemSystem--level simulationlevel simulation

�� Homogeneous modeling Homogeneous modeling �� HW/SW partitioningHW/SW partitioning�� HW/SW or SW/HW migrationHW/SW or SW/HW migration

�� Heterogeneous modelingHeterogeneous modeling�� Direct implementation and reDirect implementation and re--targetingtargeting

�� CoCo--synthesissynthesis�� HW and interface synthesisHW and interface synthesis�� SW compilation and code generationSW compilation and code generation

�� CoCo--simulationsimulation

1717

Embedded systems design process

reusedcomponents

suppor t(CAD, test, ...)

requirements definition

specification

system architecture development

integration and test

customer /marketing

systemarchitect

SWdeveloper

HWdesigner

SW development

• application SW

• compilers etc.

• operating syst.

inter face design• SW driver dev.

• HW interface synthesis

HW design

• HW architecture design

• HW synthesis

• physical design

1818

Observations on the design process

�� Increasingly concurrent design of hardware and Increasingly concurrent design of hardware and software with par tially incomplete or var iable software with par tially incomplete or var iable specificationspecification�� tight and permanent cooperation of hardware and software tight and permanent cooperation of hardware and software

designers, system architects and customer/marketing requireddesigners, system architects and customer/marketing required

�� Narrow timeNarrow time--toto--market windows require a safe market windows require a safe “ first“ first--timetime--r ight” design processr ight” design process�� early detection of systematic design flaws is crucialearly detection of systematic design flaws is crucial

�� reliable design times and precisely predictable product data arereliable design times and precisely predictable product data aremore important than design time minimizationmore important than design time minimizationprerequisite: reliable estimations prerequisite: reliable estimations -- today: designer experiencetoday: designer experience

1919

Observations on the design process

�� Increased productivity through reuse of Increased productivity through reuse of components and functionscomponents and functions�� function and component libraries requiredfunction and component libraries required�� problem: function migration between different technologies, problem: function migration between different technologies,

between hardware and softwarebetween hardware and software

State of the practice

�� CoCo--simulation as a suppor t of design simulation as a suppor t of design (process) integration(process) integration�� extension of simulation techniques to combined simulation of extension of simulation techniques to combined simulation of

hardware and software componentshardware and software components�� allows permanent control of hardware and software component allows permanent control of hardware and software component

consistencyconsistency�� supports early validation of reused component integrationsupports early validation of reused component integration

�� Integration validation more costly with Integration validation more costly with increasing level of detailincreasing level of detail�� cur rent focus on cocur rent focus on co--simulation for lower levels of a simulation for lower levels of a

designdesign�� simulation with models of specific processors, memories, busses,simulation with models of specific processors, memories, busses, ... ... �� reduction of accuracy mainly to improve simulation performancereduction of accuracy mainly to improve simulation performance�� examples: examples: Mentor Seamless CVS, Mentor Seamless CVS, ViewlogicViewlogic EagleEagle

State of the practice

�� ““ Executable” coExecutable” co--specification used as a specification used as a basis for system validationbasis for system validation

�� Vir tual prototypingVir tual prototyping�� simulation based validationsimulation based validation�� many commercial examplesmany commercial examples for different for different

applicationsapplicationsStatemateStatemate ((ii--LogixLogix), ), MatrixMatrixXX (ISI), MATLAB (ISI), MATLAB ((MathWorksMathWorks) )

�� RASSP program (DARPARASSP program (DARPA))�� Rapid prototypingRapid prototyping with “ hardwarewith “ hardware--inin--

thethe--loop”loop”�� hardware supported system emulation hardware supported system emulation � � real real

environmentenvironment�� often custom designoften custom design

2222

State of the practice

�� Executable coExecutable co--specification problemsspecification problems

�� combination of domain specific languages and combination of domain specific languages and

semanticssemantics

�� integration of reused functions and components integration of reused functions and components

in abstract modelin abstract model

�� inclusion of noninclusion of non--functional constraintsfunctional constraints

2323

Specification languages

�� Different communitiesDifferent communities

�� VLSI system design VLSI system design VHDL, VERILOG,VHDL, VERILOG, SpecchartSpecchart……

�� DSPDSP COSSAP, SPW, …COSSAP, SPW, …

�� Continuous designContinuous design MATLAB, MATRIXX, ….MATLAB, MATRIXX, ….

�� Synchronous system designSynchronous system design EsterelEsterel , , LustreLustre, , StatechartStatechart

�� Classical programmingClassical programming C, C++, Java, ….C, C++, Java, ….

�� Functional and algebraicFunctional and algebraic VDM, Z, B, VDM, Z, B, FunmathFunmath, …., ….

�� Structured design methodsStructured design methods SART, OMT, ….SART, OMT, ….

2424

Concepts for system level specification

�� CONCURRENCYCONCURRENCY�� different levels (bit, operation, statement, process, different levels (bit, operation, statement, process,

system)system)�� two types: datatwo types: data--driven, controldriven, control --drivendriven

�� HIERARCHYHIERARCHY�� needed for structured design methodologiesneeded for structured design methodologies�� Two types: behavior, structureTwo types: behavior, structure

�� COMMUNICATIONCOMMUNICATION�� data exchange between concurrent subsystemsdata exchange between concurrent subsystems�� two types: message passing, shared memorytwo types: message passing, shared memory

�� SYNCHRONIZATIONSYNCHRONIZATION�� Two models: synchronous, asynchronousTwo models: synchronous, asynchronous

2525

Example of Specification Language

�� SDLSDL

�� wellwell--suited for controlsuited for control--intensive, realintensive, real--time time systemssystems

�� flow chart FSM, both graphics and text flow chart FSM, both graphics and text

�� abstract data typesabstract data types

�� dynamic process creationdynamic process creation

�� synchronization via blocking, RPCsynchronization via blocking, RPC

�� can monitor performance constraintscan monitor performance constraints

2626

Example of Specification Language

�� StateChartsStateCharts, , SpecChartsSpecCharts�� graphical FSM of states and transitionsgraphical FSM of states and transitions�� addition of hierarchical states for modeling addition of hierarchical states for modeling

complex reactive behaviors complex reactive behaviors �� SpecChartsSpecCharts addsadds

�� behavioral completionbehavioral completion�� exceptionsexceptions

�� may attach VHDL code to states and may attach VHDL code to states and transitions arcstransitions arcs

�� extended with extended with arithmeticsarithmetics�� Easy to use for controlEasy to use for control--dominated systemsdominated systems

2727

Petri Nets (1966)

�� Powerful Powerful uninterpreteduninterpreted modeling toolmodeling tool�� Describes explicitly and graphically the Describes explicitly and graphically the

main paradigms of concurrent computation:main paradigms of concurrent computation:�� sequencing/causalitysequencing/causality�� conflict/ nonconflict/ non--deterministic choicedeterministic choice�� concurrencyconcurrency

�� Asynchronous model (partial ordering)Asynchronous model (partial ordering)�� Main drawback: Main drawback: no hierarchyno hierarchy

2828

Structure and firing rule

�� Bipartite graphBipartite graph�� places: represent distributed state by holding places: represent distributed state by holding

tokenstokens�� marking: token count for each placemarking: token count for each place�� initial marking = initial stateinitial marking = initial state

�� transitions: represent actions/eventstransitions: represent actions/events�� enabled transition: enough tokens in predecessorsenabled transition: enough tokens in predecessors�� firing transition: modifies markingfiring transition: modifies marking

2929

Petri Nets properties

�� LivenessLiveness:: from any marking and from any marking and transition can become transition can become fireablefireable

�� BoundenessBoundeness: the number of tokens in any : the number of tokens in any place cannot grow indefinitelyplace cannot grow indefinitely(1(1--bounded also called bounded also called safesafe))

�� decidable problemdecidable problem�� Basic analysis tool for bounded nets: Basic analysis tool for bounded nets:

reachabilityreachability graphgraph

3030

Petri nets extensions

�� Add interpretation to tokens and transitionsAdd interpretation to tokens and transitions�� predicate/transition netspredicate/transition nets�� colored netscolored nets

�� Add timeAdd time�� time/timed Petri netstime/timed Petri nets�� stochastic Petri netsstochastic Petri nets

�� Add hierarchyAdd hierarchy�� Petri boxesPetri boxes�� Place Chart netsPlace Chart nets

3131

Simulation and debugging requirements

�� Embedded controllers:Embedded controllers:�� ASICsASICs plus SW running on a processorplus SW running on a processor

�� VHDL or VHDL or VerilogVerilog plus C programsplus C programs

�� Weakly heterogeneous systemsWeakly heterogeneous systems

�� Embedded data processing and Embedded data processing and communication systemscommunication systems�� ASICsASICs plus SW running on a processor or ASIPplus SW running on a processor or ASIP

�� Environmental modeling (e.g. telephone lines)Environmental modeling (e.g. telephone lines)

�� Strongly heterogeneous systemsStrongly heterogeneous systems

3232

Co-simulation

�� Simulate at the same time both hardware Simulate at the same time both hardware and softwareand software

�� Two conflicting requirements:Two conflicting requirements:

�� execute the software as fast as possibleexecute the software as fast as possible

�� keep hardware and software simulations keep hardware and software simulations synchronized so they interact as they will in the synchronized so they interact as they will in the target system.target system.

3333

Co-simulation

�� Desired features:Desired features:�� Level of timing accuracyLevel of timing accuracy�� Speed of simulation runsSpeed of simulation runs�� Visibility of internal statesVisibility of internal states

�� Potential problems:Potential problems:�� Meaningful results are obtained with large SW Meaningful results are obtained with large SW

programsprograms�� Model availabilityModel availability�� Strong heterogeneity requires specialized Strong heterogeneity requires specialized

environmentenvironment

3434

Co-simulation paradigms

�� HomogeneousHomogeneous modeling:modeling:

�� HW models in HDLHW models in HDL

�� Processor model in HDLProcessor model in HDL

�� SW in assembly codeSW in assembly code

�� Usage of HDL simulator for the whole Usage of HDL simulator for the whole

system including the processor modelsystem including the processor model

�� Simple method but quite inefficientSimple method but quite inefficient

3535

Co-simulation paradigms

�� WeaklyWeakly heterogeneousheterogeneous systemssystems�� a) HDL simulators with processor modela) HDL simulators with processor model

�� b) Compiled SWb) Compiled SW

�� c) HW emulationc) HW emulation

�� StronglyStrongly heterogeneousheterogeneous systemssystems�� Require specialized simulation environmentsRequire specialized simulation environments

(e.g. Ptolemy)(e.g. Ptolemy)

�� Communication mechanisms among domains Communication mechanisms among domains and their corresponding schedulersand their corresponding schedulers

3636

HDL processor modeling

�� Precise timing modelPrecise timing model�� Accurate timing and complete functionalityAccurate timing and complete functionality

�� EventEvent--driven simulationdriven simulation

�� ZeroZero--Delay Model (ZDM) for timingDelay Model (ZDM) for timing�� Correct transitions at clock edgesCorrect transitions at clock edges

�� CycleCycle--based simulationbased simulation

�� InstructionInstruction--set simulator set simulator �� Model emulates processor while insuring Model emulates processor while insuring

correct register and memory valuescorrect register and memory values

3737

Compiled SW

�� Basic assumption:Basic assumption:�� HW/SW communication protocol such that HW/SW communication protocol such that

communication delay has no effect on communication delay has no effect on functionalityfunctionality

�� SW is compiled and linked to simulatorSW is compiled and linked to simulator

�� HW/SW communication is replaced by HW/SW communication is replaced by handshakehandshake

�� Simulation speed is limited by HW Simulation speed is limited by HW simulation speedsimulation speed

3838

HW emulation

�� HW mapped onto programmable HWHW mapped onto programmable HW

�� One order of magnitude loss in speedOne order of magnitude loss in speed

�� Programmable HW boards connected to Programmable HW boards connected to

workstationsworkstations

�� Limited visibility of internal statesLimited visibility of internal states

Co-synthesis design flow-Principle

HDL generation

constraints and user directives

OS, component &

communication librar ies

system function

compilation&system analysis

intermediate code generation

object code HW model

code generation

HW/SW par tit ioning & scheduling

HL synthesisco-simulation,

analysis

Co-design using co-synthesis and design space exploration

HDL generation

constraints and user directives

OS, component &

communication libraries

system function

compilation&system analysis

intermediate code generation

object code HW model

code generation

HW/SW partitioning& scheduling

HL synthesisco-simulation

analysis

• specification parameter change

• high level transformations

hardware designer

software developercustomer system

architect

cost, per formance, ...

estimations

4141

Modeling Current Solution

�� Some C++ dialects have been proposedSome C++ dialects have been proposed

�� General idea:General idea:�� new classes are defined to model hardware new classes are defined to model hardware

characteristicscharacteristics

�� no standardization for new classesno standardization for new classes

�� SystemC 1.0 (end of 1999)SystemC 1.0 (end of 1999)�� proposal of standardizationproposal of standardization

�� continuous extensions (2.0 ... 3.0)continuous extensions (2.0 ... 3.0)

4242

Standard C-based Design Flow

System LevelModel C, C++

Results

AnalysisRefine

VHDL/Verilog

Simulation

Synthesis

FSMD description

Manual converision

4343

SystemC-based Design Flow

SystemC ModelSystem Level

SystemC ModelRT Level

Refinement

VHDL/Verilog

Synthesis

FSMD Logicdescription

Authomatic translation

Simulation

4444

Contents

�� Hw/Hw/SwSw Synthesis Synthesis

�� Hw Performance EvaluationHw Performance Evaluation

�� SwSw Performance EvaluationPerformance Evaluation

�� The role of O.S.The role of O.S.

4545

Simple target architecture

�� A set of dedicated HW unitsA set of dedicated HW units

�� A programmable core or coA programmable core or co--processorprocessor

�� MemoryMemory�� Including SW program storageIncluding SW program storage

�� Interfaces and interconnectionsInterfaces and interconnections

ASIC ASIC PROC RAM

4646

Hardware and software synthesis

�� Implementation of hardware and software Implementation of hardware and software components after partitioningcomponents after partitioning

�� Constraints and optimization criteria similar to Constraints and optimization criteria similar to those for partitioningthose for partitioning

�� Area and code size tradedArea and code size traded--off against off against performance (dominant for realperformance (dominant for real--time systems)time systems)

�� Cost considerations Cost considerations �� offoff--thethe--shelf processorshelf processor�� separation of software and hardware synthesis, separation of software and hardware synthesis,

relying on a prerelying on a pre--designed customizable interfacedesigned customizable interface

�� Exception: synthesis of ASIP and microcode Exception: synthesis of ASIP and microcode

4747

System-level co-synthesis flow

�� Consistent systemConsistent system--level modelinglevel modeling�� Partitioning into dedicated and programmable Partitioning into dedicated and programmable

unitsunits�� HW synthesis of dedicated unitsHW synthesis of dedicated units

�� Based on research or commercial standard synthesis Based on research or commercial standard synthesis toolstools

�� SW synthesis for programmable units SW synthesis for programmable units (processors)(processors)�� Based on specialized compiling techniquesBased on specialized compiling techniques

�� Interface synthesisInterface synthesis�� Definition of HW/SW interface and synchronizationDefinition of HW/SW interface and synchronization�� Drivers of peripheral devicesDrivers of peripheral devices

4848

SW synthesis problems

�� Target architecture is an ASIPTarget architecture is an ASIP

�� Develop a specific compilerDevelop a specific compiler

�� NonNon--executable systemexecutable system--level specification level specification

of computerof computer--aided partitioningaided partitioning

�� Synthesize highSynthesize high--level or assembly codelevel or assembly code

�� Interface to HW with given protocolInterface to HW with given protocol

�� Synthesize interfacing routinesSynthesize interfacing routines

4949

Re-targetablecompilers

�� Compiler technology suitable for different Compiler technology suitable for different architectural backarchitectural back--endsends�� ASIPsASIPs have specific instruction sets, memory have specific instruction sets, memory

and interconnection resourcesand interconnection resources

�� Code quality (i.e. execution speed) is Code quality (i.e. execution speed) is important whereas compilation time is less important whereas compilation time is less criticalcritical

�� Assembly code programming is still Assembly code programming is still common practicecommon practice

5050

Re-targetablecompilers

�� Portable compilersPortable compilers

�� Compiler needs significant reCompiler needs significant re--write for portingwrite for porting

�� Compiler compilersCompiler compilers

�� Generates compiler from architectural Generates compiler from architectural templatestemplates

�� MachineMachine--independent compilersindependent compilers

�� Applicable to different architecturesApplicable to different architectures

5151

Re-targetablecompilers

�� Compile code into intermediate form and Compile code into intermediate form and optimizeoptimize�� Standard optimizing compiler algorithmsStandard optimizing compiler algorithms

�� Instruction selectionInstruction selection�� Pattern matching techniquesPattern matching techniques

�� Instruction schedulingInstruction scheduling�� Satisfaction of realSatisfaction of real--time constraintstime constraints

�� Register allocationRegister allocation�� MicroMicro--code compactioncode compaction

5252

Software synthesis

�� Constrained problem for embedded software:Constrained problem for embedded software:�� no virtual memory, reduced dynamic memory allocation no virtual memory, reduced dynamic memory allocation

and dynamic task creationand dynamic task creation

�� SW functions identified by program threadsSW functions identified by program threads�� A single processor requires thread serialization A single processor requires thread serialization

or interleaving of originally concurrent tasksor interleaving of originally concurrent tasks�� Scheduling of threads and instructionsScheduling of threads and instructions

�� Satisfying performance constraintsSatisfying performance constraints

�� SystemSystem--level runlevel run--time schedulertime scheduler to synchronize to synchronize SW and HW functionsSW and HW functions

5353

Sw synthesis from SystemC

�� SwSw processes are processes are isolatedisolated from the global from the global system descriptionsystem description

�� Hw/Hw/SwSw interfacesinterfaces are generatedare generated

�� SystemC keywords SystemC keywords remappedremapped on C++on C++

�� Software Software performanceperformance measurementmeasurement

HwHw constraintsconstraints

5454

Sw performance measurement

�� Use of Use of profilingprofiling toolstools

�� C library linked to executable code (e.g. C library linked to executable code (e.g. GNU GNU gprofgprof))

�� Program execution (problems?) Program execution (problems?)

Program Program profileprofile

5555

Measurement example% Time cumulative

secondsself

secondscalls self

ms/calltotal

ms/callname

33.34 0.02 0.02 7208 0.00 0.00 open16.67 0.03 0.01 244 0.04 0.12 offtime16.67 0.04 0.01 8 1.25 1.25 memccpy16.67 0.05 0.01 7 1.43 1.43 write16.67 0.06 0.01 mcount0.00 0.06 0.00 236 0.00 0.00 tzset0.00 0.06 0.00 192 0.00 0.00 tolower0.00 0.06 0.00 47 0.00 0.00 strlen0.00 0.06 0.00 45 0.00 0.00 strchr0.00 0.06 0.00 1 0.00 50.00 main0.00 0.06 0.00 1 0.00 0.00 memcpy0.00 0.06 0.00 1 0.00 10.11 print0.00 0.06 0.00 1 0.00 0.00 profil0.00 0.06 0.00 1 0.00 50.00 report

5656

Measurement legenda(1)

�� % time % time �� This is the percentage of the total execution time your This is the percentage of the total execution time your

program spent in this function. These should all add up to program spent in this function. These should all add up to 100%. 100%.

�� cumulative secondscumulative seconds�� This is the cumulative total number of seconds the computer This is the cumulative total number of seconds the computer

spent executing this functions, plus the time spent in all the spent executing this functions, plus the time spent in all the functions above this one in this table. functions above this one in this table.

�� self seconds self seconds �� This is the number of seconds accounted for by this function This is the number of seconds accounted for by this function

alone. alone.

5757

Measurement legenda(2)

�� callscalls�� This is the total number of times the function was called. This is the total number of times the function was called.

�� self ms/call self ms/call �� This represents the average number of milliseconds spent in This represents the average number of milliseconds spent in

this function per call, if this function is profiled. this function per call, if this function is profiled.

�� total ms/call total ms/call �� This represents the average number of milliseconds spent in This represents the average number of milliseconds spent in

this function and its descendants per call. this function and its descendants per call.

5858

Measurement correctness

�� Sampling periodSampling period::�� time interval between two measurements (e.g., time interval between two measurements (e.g.,

0.01 sec. 0.01 sec. �� 100hz)100hz)

�� Total Total execution timeexecution time::�� time window used to make the measurement time window used to make the measurement

(e.g., 0.06 sec.)(e.g., 0.06 sec.)�� number of samplesnumber of samples

�� sampling errorsampling error E.g.E.g. WriteWrite functionfunction

5959

Definition of testbench

�� Does testbench affect the measurement?Does testbench affect the measurement?�� Yes, definitely!Yes, definitely!

�� How to select How to select testbenchestestbenches::�� algorithm informationalgorithm information�� coverage metricscoverage metrics

�� branch coveragebranch coverage�� statement coveragestatement coverage�� condition coveragecondition coverage�� path coverage ...path coverage ...

�� statistical analysisstatistical analysis

6060

Role of RTOS

�� SwSw works under the RTOS supervisionworks under the RTOS supervision

�� Hw/Hw/SwSw interchange through RTOSinterchange through RTOS

�� Main problems:Main problems:�� uniform time definition conceptuniform time definition concept

�� tasks schedulingtasks scheduling

�� realreal--time performance issuestime performance issues

6161

Summary

�� HW/SW coHW/SW co--design is a wide and rapid design is a wide and rapid evolving areaevolving area

�� Several application domains, architectures Several application domains, architectures and implementation stylesand implementation styles

�� Need to define design methodologies with Need to define design methodologies with the goal of developing CAD tool supportthe goal of developing CAD tool support

�� The impact of CAD on systemThe impact of CAD on system--level design level design will be more profound than the impact of will be more profound than the impact of CAD on VLSI designCAD on VLSI design