system ic design lab. dongguk university 1 study of cern for the alice its upgrade study of cern for...

System IC Design Lab.

Dongguk University1

Study of CERN for the ALICE ITS upgrade

Study of CERN for the ALICE ITS upgrade

KIM,D.H. , KWON,Y. ,SONG,M.K.

Department of Semiconductor Science,Dongguk Univ. for the ALICE collaboration.

Department of Physics, Yonsei Univ. for the ALICE collaboration.


Dongguk University2

< CONTENTS >

I. Introduction

II. Explorer – study of pixel sensor

III. pALPIDE – study of front-end and readout

IV. Conclusion

V. Appendix – work for ITS upgrade


Dongguk University3

I. Introduction - ALICE Inner Tracking System at present

2 layers of hybrid pixels (SPD)2 layers of silicon drift detector (SDD)2 layers of silicon strips (SSD)


Dongguk University4

I. Introduction - ITS upgrade – 7 layers

Inner Barrel Outer Barrel

Layer# 1 2 3 4 5 6 7

Radial position (mm) 22 28 36 200 220 410 430

Length in z(mm) 270 843 1475

Nr. Of staves 12 16 20 48 52 96 102

Nr. Of chips/staves 9 56 98

Nr. Of chips/layer 108 144 180 2688 2912 9408 9996

Material thickness ~0.3% X0 ~0.8% X0

Throughput < 200 Mbit / sec*cm2 < 6 Mbit / sec*cm2


Dongguk University5

I. Introduction - Design specifications for PIXEL Chip

Parameter Inner Barrel Outer Barrel

Silicon thickness 50 μm

Chip Size 15 mm x 30 mm

Pixel Size (r-ϕ) 20-30 μm 20-50 μm

Readout Time < 30 μs

Power density << 300 mW / cm2 < 100 mW / cm2

Hit density < 115 / cm2 < 1.5 / cm2

Radiation Load (TID) < 700 krad < 10 krad

1 MeV neq fluency < 1013 cm-2 < 3x1010 cm-2

Data throughputs (*) 0.6 Gbit/s per chip 7 Mbit/s per chip

(*) Assumptions: • Nr of bits to code a hit: 35 • Fake hit: 10-5 /event


Dongguk University6

I. Introduction - Technology

• Commercial CMOS Imaging Sensor (CIS) 　 • High resistivity epi layer 　 • Deep p-well

• Physical gate oxide thickness: 3 nm • Metal Option 6ML1 　 • 5 routing metals + 1 last metal for power busses


Dongguk University7

II. Explorer- PIXEL SENSOR OPTIMIZATION 　


Dongguk University8

II. Explorer- Prototype July 2012 submission: Explorer-0

Analog readout for pixel characterization

Readout time decoupled from integration time

Possibility to reverse bias the substrate

Sequential readout with correlated double sampling

Contains two 1.8x1.8mm2 matrices of 20x20 and 30x30 micron pixels with different geometries

PU

LS

ED

RO

WS


Dongguk University9

II. Explorer- Charge collection

Minimum Ionizing Particle (MIP) creates ~ 60 e/h pairs per micron of silicon traversed (in a thin layer)

Example for 18 μm thick layer: 1200 e => 0.17 fC

Advantages of having collection by drift: Tolerance to non ionizing radiation (less trapping probability) Reduction of the cluster size (less charge sharing)

Diffusion Drift

Force Charge carrier concen-tration gradient

Electric field

Collection time

~ 10-7 s < 10-8 s

Minority charge carrier path length

Long Short


Dongguk University10

II. Explorer- Explorer - Collection electrode layout

Sector nwell width Shape Side length Spacing nwell area Characteristic

1 2 μm Octagon 0.83 μm 0.00 μm 3.31 μm2 Smallest diode, lower collection eff.

2 & 8 3 μm Octagon 1.24 μm 0.00 μm 7.46 μm2 Intermediate performance, S/N lower

3 4 μm Octagon 1.66 μm 0.00 μm 13.25 μm2 Lager diode, no spacing, more noise

4 3 μm Square 3.00 μm 0.00 μm 9.00 μm2 Performance similar to sector 2

5 3 μm Octagon 1.24 μm 0.60 μm 7.46 μm2 Small spacing, lower efficiency

6 & 9 3 μm Octagon 1.25 μm 1.04 μm 7.46 μm2 Better S/N increasing spacing

7 2 μm Octagon 0.83 μm 1.54 μm 3.31 μm2 Better collection eff., better S/N

NMOS transistors in sectors 7, 8 and 9 are in a triple well.

nwell – spacing – pwell contact



II. Explorer- Block diagram

• analog read-out for characterization studies • readout time decoupled from integration time • double readout in CDS mode

RESET STORE1 STORE2

Pixel circuit two independent

analog memory cells, signal stored just after RESET and at the end of integration cycle

rowSelect

VDD + VSS +

columnSelect

SEQUENCER

VPULSE …

analog biases

BIAS

pixels read serially

PULSER

Periphery

column select OUT



II. Explorer- Explorer- circuit

Features: • Serial readout. • Substrate bias < 0 V. • Tunable charge integration time.



III. pALPIDE - FRONT-END and READOUT 　



III. pALPIDE - pALPIDE: prototype ALice PIxel DEtector

Prio

rity

enc

od

er

Pix

el f

ron

t-e

nd

512

512

STATE

RESET

512

512

STATE

RESET

0 512

10

VA

LID

SE

LEC

T

AD

DR

10

VA

LID

SE

LEC

T

AD

DR

Periphery

DataBias Clock Control+ trigger

Pulser

Pix

el f

ron

t-e

nd

Prio

rity

enc

od

er

Pix

el f

ron

t-e

nd

512

512

STATE

RESET

512

512

STATE

RESET

Pix

el f

ron

t-e

nd

• low power in-pixel discriminator

• current comparator (bias of ~20 nA)

• storage element for hit information

• in-matrix address encoder

• tree structure to decrease capacitive load of lines

• outputs pixel address and resets pixel storage element

• loss-less data compression de-randomizing circuit• compresses cluster information in the column• multi-event memory



III. pALPIDE - IN-PIXEL HIT DISCRIMINATION

VRESET

PWELL

D0

D1

nand

nand

Reset

Hit_B

inv State Pix_reg

COMP/AMP

STATE_MEMORY

Priority Encoder

State Pix_regValid

Adress

RESET_B

Low Power Analog Front End (Power < 50 nW/pixel) based on a single stage amplifier/current comparator.

Data driven readout of the pixel matrix, only zero-suppressed data are transferred to the pe-riphery.

Dynamic Memory Cell, Storage capacitor instead of SR-latch to save space.



III. pALPIDE - Front-End principle

IBIAS_PIX

source

curfeed

VCASP

AVDD

AVSS

VCASN

ITHR_PIX

IDB_PIX

M0

M1

M2

M3

Cs

M4

M5M6

M7

VRESET

PWELL

D0

D1

OUT

OUT_B

Ibias(20nA) Ithr(0.5nA)

Idb(10nA)

Low Power Analog Front End based on an weak inversion operation mode. except current source transistor (M0, M4, M6)



III. pALPIDE - Front-End principle

IBIAS_PIX

source

curfeed

VCASP

AVDD

AVSS

VCASN

ITHR_PIX

IDB_PIX

M0

M1

M2

M3

Cs

M4

M5M6

M7

VRESET

PWELL

D0

D1

OUT

OUT_B

vin

vx

vsource

vcurfeed

voutvoutb



III. pALPIDE - Front-End output example

Front End output with a bias current of 20 nA IBIAS_PIX

source

curfeed

VCASP

AVDD

AVSS

VCASN

ITHR_PIX

IDB_PIX

M0

M1

M2

M3

Cs

M4

M5M6

M7

VRESET

PWELL

D0

D1

OUT

OUT_B



III. pALPIDE - Front-End output example

Minimum detectable charge definition

Me

mo

ry s

tate

(V

)

Qin (electrons) Minimum detectable charge as a function of the bias current

Cd = 1 fF Ith = 0.5 nA Ileak = 5 pA (nominal 20 nA condition)



III. pALPIDE - Priority Encoder readout

valid

select

a[0]a[1]

ADDR[0:1] ADDR[2:3]

VALID

SELECT

v[0]v[1]v[2]v[3]sel[0]sel[1]sel[2]sel[3]

Peripherylogic

CLOCK

valid

select

a[0]a[1]


valid

select

a[0]a[1]


valid

select

a[0]a[1]


valid

select

a[0]a[1]


TRIGGER

hierarchical readout 4 inputs basic block

repeated to create a larger encoder

1 pixel read per clock cycle

forward path (address encoder) in gray

feed-back path (pixel reset) in red

asynchronous (combinatorial) logic

clock only to periphery, synchronous select only to hit pixels

PIXELCOLUMN



III. pALPIDE - Layout of pALPIDE

Pixel Matrix: sensitive area

Chip size: 30 mm x 15 mm Pixel size: 28 μm x 28 μm 1024 Columns x 512 Rows

Periphery circuit ( DAC, PADs, periphery readout logic, etc)

PR

IOR

ITY

EN

CO

DE

R

FRONT-END

Collection Diode

State Mem-ory

PIX

EL

L

OG

IC

I can‘t see information of Digital circuit PRIORITY ENCODER, periphery readout logic, etc



IV. Conclusion Green : complete understanding

ExplorerExplorer

pALPIDEpALPIDE

PIXELPIXEL

ReadoutReadout

Front-EndFront-End

ReadoutReadout

PeripheryPeriphery

• Charge collection - Diffusion, Drift• Design of collection electrode - shape, nwell area, spacing …• Analysis about characteristic of each collection electrode

• Readout circuit• Rolling shutter architecture• Sequential readout with correlated double sampling

• Asynchronous comparator - operation principle ,weak inversion, noise analysis • Memory• Pixel Logic circuit

• Priority Encoder - Asynchronous logic, implement • Periphery readout logic - synchronous select only to hit pixels, implement

• DAC & ADC • PLL• PAD• etc



IV. Conclusion Blue : weak understanding

ExplorerExplorer

pALPIDEpALPIDE

PIXELPIXEL

ReadoutReadout

Front-EndFront-End

ReadoutReadout

PeripheryPeriphery








IV. Conclusion Red : didn’t understand

ExplorerExplorer

pALPIDEpALPIDE

PIXELPIXEL

ReadoutReadout

Front-EndFront-End

ReadoutReadout

PeripheryPeriphery








• Study of pixel Studied the collection electrode. (shape, size, layout, etc) But it was studied by Explorer result. So it needs to implement for more detailed analysis.

• Analog readout circuit Studied the Front-end circuit. (operation principle) But it was studied by simulation result. It needs to study an weak inversion operation mode in analog circuit for more detailed analysis of front-end circuit.

• Digital readout circuit I didn’t have a chance for study digital readout circuit.

IV. Conclusion



Thank you



V. Appendix DAC - List of Voltage and Current DACs

Voltage DAC Current DAC

Resolution • 8bit • 8bit

Type • Resistor • pMOS

Output/unitcol-umn

• 6EA 1) VCASP 2) VCASN 3) VRESET 4) VPULSE_LOW 5) VPULSE_HIGH 6) VAUX

• 5EA 1) IBIAS 2) ITHR 3) IDB 4) IAUX1 5) IAUX2



V. Appendix DAC – Voltage DAC

Bottom

Top

Resistor (256)

Unit cell (256)

Control Block(256)

VCASP

VCASN

VRESET

DACMONV

VPLSE_HIGH

VAUX

SE

T_V

CA

SP<

255:

0>

SE

T_V

CA

SN<

255:

0>

SE

T_V

RE

SE

T<

255:

0>

SE

T_V

PL

SE

_LO

W<

255:

0>

SE

T_V

PL

SE

_HIG

H<

255:

0>

SE

T_V

AU

X<

255:

0>

VPLSE_LOW

VC

ASP

VC

ASN

VR

ES

ET

VP

LS

E_L

OW

VP

LS

E_H

IGH

VA

UX

SW

CN

TL

_VC

ASP

SW

CN

TL

_VC

ASN

SW

CN

TL

_VR

ES

ET

SW

CN

TL

_VP

LS

E_L

OW

SW

CN

TL

_VP

LS

E_H

IGH

SW

CN

TL

_VA

UX

SW

CN

TL

_DA

CM

ON

V

VR

ES

ET

_IN

T

VP

LS

E_L

OW

_IN

T

VP

LS

E_H

IGH

_IN

T

VA

UX

_IN

T

VRESET_INT

VPLSE_LOW_INT

VPLSE_HIGH_INT

VAUX_INT

SET_VCASP

SET_VCASN

SET_VRESET

SET_VPLSE_LOW

SET_VPLSE_HIGH

SET_VAUX

SWCNTL_VCASPB

SWCNTL_VCASNB

SWCNTL_VRESETB

SWCNTL_VPLSE_LOWB

SWCNTL_VPLSE_HIGHB

SWCNTL_VAUXB

SWCNTL_DACMONVB

SWCNTL_VCASP

SWCNTL_VCASN

SWCNTL_VRESET

SWCNTL_VPLSE_LOW

SWCNTL_VPLSE_HIGH

SWCNTL_VAUX

SWCNTL_DACMONVB

SWCNTL_DACMONVB

SWCNTL_DACMONVB

SWCNTL_DACMONVB

SWCNTL_DACMONVB

VR

EF

AV

SS

DA

CR

EF

VCASP VCASN VRESETVPLSE_L

OWVPLSE_HI

GHVRESET

0 0 0 368mV 368mV 368mV 368mV255 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V

<Voltage DACS output range at nominal corner simulation>

VREF AVSS

<Voltage DAC resistor divider> <Voltage DAC unit block >

• Block diagram & Simulation result



V. Appendix DAC – Monitoring & Overriding mode

• Voltage DAC

DACMONV

VCASP

VCASN

VRESET

VPLSE_HIGH

VAUX

VPLSE_LOW

SWCNTL_VCASPB

SWCNTL_VCASNB

SWCNTL_VRESETB

SWCNTL_VPLSE_LOWB

SWCNTL_VPLSE_HIGHB

SWCNTL_VAUXB

SWCNTL_DACMONVB

SWCNTL_VCASP

SWCNTL_VCASN

SWCNTL_VRESET

SWCNTL_VPLSE_LOW

SWCNTL_VPLSE_HIGH

SWCNTL_VAUX

SWCNTL_DACMONVB

SWCNTL_DACMONVB

SWCNTL_DACMONVB

SWCNTL_DACMONVB

SWCNTL_DACMONVB

DAC

DAC

DAC

DAC

DAC

DAC

Input Operation

SWCNTL_VxxxOnly one SWCNTL_Vxxx can be “1”

0 To matrix (normal operation)

1 To DACMONV

SWCNTL_DACMONVcommon signal for all voltage DACs

0 Monitoring

1 Overriding

<Voltage DACs: monitoring and overriding scheme> <Voltage DACs operation modes>

Monitoring mode, external circuit requirement:o Measure a voltage value between 0 and VREF with a 10 bit reso-

lution.o Read-out circuit with a high input impedance (R in > 1 MΩ).

Overriding mode, external circuit requirement:o Set a voltage value on a high impedance net between 0 and VREF

with a 8 bit resolution



V. Appendix DAC – Monitoring & Overriding mode

• Current DAC

- Overriding reduction current mirror =10 : 1 for bias currents 11 : 1 for IREF - Monitoring amplification current

mirror = 1 : 10

0 to 20 A

Monitor or override a cur-rent in the 0 to 200 µA range

PAD

1 : 10

1 : 10

AVSS

Monitoring mode, external circuit requirement:o Measure a current between 0 and 200 µA o Suggested load for the current measurement: ~ 5 kΩ (shunt between DACMONI and AVSS)

Overriding mode, external circuit requirement:o Set a current between 0 and 200 µA with a 9 bit resolution. o The current can be set with a tunable resistor between 5 kΩ and 5 MΩ (shunt between DACMONI and AVSS)



V. Appendix PIXEL– Input capacitance

VRESET

PWELL

IBIAS_PIX

source

curfeed

VCASP

VDDA

GNDA

HITB

VCASN

ITHR_PIX

IDB

D0

D1

M0

M1

M2

M3

Cs

Cf

M4

M5M6

M7

<Front-End principle>

Routing capacitance

Collection diode capacitance

Reset diode capacitance




<Miller effect>

<pALPIDE Pixel Layout>

If –Av is 1 , Cm = 0

Input capacitance is can be compensated.

• Routing capacitance




<Special Source Follower scheme>

Vout

SUB

VDDA

GNDA

GNDA

125nA=IFOL1 x 1/4

IFOL1=500nA

• Routing capacitance pALPIDE front-end circuit instead of Special source Follower to decrease input capacitance

system ic design lab. dongguk university 1 study of cern for the alice its upgrade study of cern for...

Documents