system co-design and data management for flash devices ... · ibm research, switzerland stratis d....

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Bonnet, Bouganim, Koltsidas, Viglas, VLDB 2011

System Co-Design and Data Management for Flash Devices

VLDB’2011

Philippe Bonnet, ITU, Denmark

Luc Bouganim, INRIA, France

Ioannis Koltsidas IBM Research, Switzerland

Stratis D. Viglas University of Edinburgh, United Kingdom

2


Flash Devices (SSD)

Why Bother? Disk is disk

~650 mio units shipped in 2010

IO don't matter

CPU is the critical resource

PCM is coming

100x faster 10 mio write cycles

[Papandreou et al., IMW 2011]

Just a SATA drive

I can readily plug in flash devices in my server. What is the big deal?

3


Some Trends ... 2000 2010

HDD Capacity

HDD IOPS

200 GB 2 TB

200 200

SSD Capacity

SSD IOPS

14 GB (2001) 256 GB

HDD GB/$ 0,05

SSD GB/$ 3 x10E-4 0,5

30

10E6+ (PCIe) 5x10E3+ (SATA)

10E3 (SCSI)

x1 x600 x10

x20 x1000 x1000

PCM Capacity PCM IOPS 10E6+ (1 chip)

2x10E5 cells, 4 bits/cell

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… and a Fact

Flash-based SSDs do nothing well! They offer high throughput at low energy consumption.

[Tsorigiannis et al. 2010]

5


SSD-based Systems With more than 1,000 stores, Danish Supermarket group is one of Denmark’s largest retailers. To help keep up with customer needs, the company manages more than 10 terabytes of business intelligence data.

Neteeza Twin-fin Oracle Exadata

Database Appliances SSD-based blades Scaled up

Super Micro 6026

Scaled down

Amdahl blade [Szalay et al., 2009]

IOs matter. Systems are being designed and commercialized for efficient data management for flash devices.

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Block Device SSDs and HDDs provide the same memory abstraction: a block device interface

Figure courtesy of Koschaak and Saltzer

ERASE (address)

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Strong Modularity SSDs and HDDs provide the same memory abstraction: a block device interface

application => There should be no impact on application (e.g., DBMS) ?

8


Design Assumptions

Controller

read/write head

disk arm

tracks

platter

spindle

actuator

disk interface

=> Actually DBMS design very much based on disk characteristics: (1) locality in the logical space preserved in the physical space, (2) sequential access is faster than random access.

Page-based IO quantization;

Identical representation In memory and on disk

Random accesses are avoided

Sequential accesses are favored: Extent-based

allocation, clustering

Write-ahead logging; Physiological logging

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How do flash devices impact DBMS design? (Bottom-up) We need to understand flash devices a bit better.

If they exhibit stable properties

=> Design principles for data management

If they do not exhibit stable properties

=> How to tackle the increased complexity?

(Top-down) We make assumptions about the behaviour of flash devices, and we design adapted DBMS components. We then need to make sure that (at least some) flash devices actually fit our assumptions.

10


Tutorial Outline

1. Introduction (Philippe)

2. Flash devices characteristics (Luc)

3. Data management for flash devices (Stratis)

4. Two outlooks (Stratis & Philippe)

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A short motivating story (1)

•! Alice, Bob, Charlie and Dave want to measure the performance of a given data intensive algorithm for flash devices…

•! They use different strategies but start from the same IO traces of that algorithm and own an MTRON and 2 identical INTEL X25-M SSDs.

IO Traces RW(2000, 2.0, 8000) SR(2000, 16.0) RW(500, 2.0, 8000) RW(500, 2.0, 8000) RR(100, 4.0, 8000) …

Algorithm X

Same model Same firmware

Never used

Used

12


•! Alice believes in datasheets. She builds a simple SSD simulator configured with basic SSD performance numbers.

•! She takes the SSD performance numbers from the datasheet and runs the simulator using the traces….

•! Bob, does not believe in datasheets. He runs simple tests on both SSDs to obtain the basic performance numbers…He then runs Alice’s simulator on the traces with his numbers

Configuration File IOS SR RR SW RW 1 70 87 51 9023 2 81 98 64 8723 4 104 122 85 8686 8 150 167 129 8682

A short motivating story (2): Alice & Bob

IO Traces RW(2000, 2.0, 8000) SR(2000, 16.0) RW(500, 2.0, 8000) RW(500, 2.0, 8000) RR(100, 4.0, 8000)

Mtron Datasheet

Results Simulator

13


A short motivating story (3): Charlie & Dave

•! Charlie, does not believe in Bob! He is more cautious and runs long tests on the same SSDs and obtain his own basic performance numbers. Then, he proceeds as Bob.

•! Dave does not like simulation and runs the traces directly on the SSDs.

What is your take on the resulting measures?

IO Traces RW(2000, 2.0, 8000) SR(2000, 16.0) RW(500, 2.0, 8000) RW(500, 2.0, 8000) RR(100, 4.0, 8000)

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A short motivating story (4): Results

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INTEL X25 MTRON Used

Never used

•! Mtron and Intel devices behave differently

•! Identical Intel devices behave differently

! Confidence in performance measurements is very low!

•! Modeling flash devices seems difficult •! What about designing algorithms for flash devices ?

"! e.g., database systems, operating systems, applications ?

15


Outline of the first part of this tutorial

Goal: understand the impact of flash memory on software (DBMS) design and vice-versa

•!We study flash chips, explaining their constraints and trends

•!We then consider flash devices as black boxes and try to understand their performance behavior (uFLIP). Goal: Find a simple model, basis for a DBMS design

•!We hit a wall with the black box approach # we open the box, i.e., the FTL, and look at FTL techniques.

•! Finally, we propose an alternative to complex FTLs, better adapted for DBMS design.

16


The Good

NAND Flash chip performance! •!A single flash chip offers great performance

"! e.g., 40 MB/s Read, 10 MB/s Program "! Random access is as fast as sequential access "! Low energy consumption

17


The Bad

The severe constraints of NAND flash chips! •! C1: Program granularity:

"! Program must be performed at flash page granularity (2KB-16KB)

•! C2: Must erase a block before updating a page (256 KB-1MB) •! C3: Pages must be programmed sequentially within a block •! C4: Limited lifetime (from 104 up to 105 erase operations)

Program granularity: a page (32 KB) Pagess must be

programmed sequentially

within the block (256 pages)

Erase granularity: a block (1 MB)

18


Flash chips BY

A bit of electronic to understand flash chip constraints and trends


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Flash cells

Control Gate

Floating Gate

P substrate N+ N+

Oxide Layer

Flash cell: a floating gate transistor

•! Flash cell: resembles a semiconductor transistor "! 2 gates instead of 1 "! Floating gate insulated all around by an oxide layer

•! Electrons placed on the floating gate are trapped

•! The floating gate will not discharge for many years

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Flash cells: NOR vs NAND

NAND "! Slower read (Page) "! Quicker prog. (Page) "! Quicker erase (Block) "! Files, data

NOR "! Quick read (Byte) "! Slow prog. (Byte) "! Slow erase "! XIP # Code

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•! Programming: Apply a high voltage to the control gate # electrons get trapped in the floating gate

•! Erasing: Apply a high voltage to the substrate # electrons are removed from the floating gate

NAND Flash cells mode of operation

Programming

20 V

0 V 0 V

Wear out cell Erasing

0 V

20 V 20 V

•! Reading: the charge changes the threshold voltage of the cell "! Single level cell (SLC) store one bit per cell: charged = 0, not charged = 1 "! Multi level cell (MLC) store 2 bits per cell (4 levels)

•! After a number of program/erase cycle, electrons are getting trapped in the oxyde layer # End of life of the cell

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NAND Architecture & timings

•! Based upon independent blocks (4 Mio cells here)

•! Block: smallest erasable unit

•! Page: smallest programmable unit

Geometry & Timings

NAND flash MICRON MLC: MT29F128G08CJABB 34560 bits/page (4 KB + 224 B)

256 pages/block

1 page

1 flash cell

MLC Page Size 4 KB Block Size 1 MB Chip Size 16 GB Read Page (µs) 150 Program Page (µs) 1000 Erase Block (µs) 3000

Floating gate

Control gate

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Program Disturb

•! Some cells not being programmed receive elevated voltage stress (near the cells being programmed)

•! Stressed cells can appear weakly programmed

Reducing program disturb: •!Use Error Correction Code to recover errors •!Program page sequentially within a block Cooke (FMS 2007)

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Impact on flash chip IOs

•!Flash cell technology ! Limited lifetime for entire blocks (when a cell wear out,

the entire block is marked as failed).

•!NAND Layout and structure !Block is the smallest erase granularity

•!Program Disturb ! Page is the smallest program granularity (! for SLC) ! Pages must me programmed sequentially within a block ! Use of ECC is mandatory # ECC unit is the smallest

read unit (generally 1 or ! page)

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Flash chips: trends

•! Density increases (price decreases) "! NAND process migration: faster than Moore’s Law (today 20 nm) "! More bits/cell:

–! SLC (1), MLC (2), TLC (3)

•! Flash chip layout and structure: larger, parallel "! Larger blocks (32 # 256 Pages) "! Larger pages: 512 B (old SLC) # 16KB (future TLC) "! Dual plane Flash # parallelism within the flash chip

•! Lifetime decreases "! 100 000 (SLC), 10 000 (MLC), 5000 (TLC)

•! ECC size increases

•! Basic performance decreases "! Compensated by parallelism

Abraham (FMS 2011), StorageSearch.com

26





•!We then consider flash devices as black boxes and try to understand their performance behavior (uFLIP)

•!We hit a wall with the black box approach # we open the box, i.e., the FTL, and look at FTL techniques

•! Finally, we propose an alternative to complex FTLs, better adapted for DBMS design

27


The Good

The hardware! •! A single flash chip offers great performance

"! e.g., 40 MB/s Read, 10 MB/s Program "! Random access is as fast as sequential access "! Low energy consumption

•! A flash device contains many (e.g., 32, 64) flash chips and provides inter-chips parallelism

•! Flash devices may include some (power-failure resistant) SRAM

28


The Bad

The severe constraints of flash chips! •! C1: Program granularity:

"! Program must be performed at flash page granularity

•! C2: Must erase a block before updating a page •! C3: Pages must be programmed sequentially within a block •! C4: Limited lifetime (from 104 up to 106 erase operations)

Program granularity: a page (32 KB) Pagess must be

programmed sequentially

within the block (256 pages)

Erase granularity: a block (1 MB)

29


The software!, the Flash Translation Layer "!emulates a classical block device and

handle flash constraints

And The FTL

SSD

Write sector

Read sector

No constraint!

Flash chips

Read page

Program page

Erase block

Constraints

(C1) Program granularity

(C2) Erase before prog.

(C3) Sequential program within a block

(C4) Limited lifetime

MAPPING

GARBAGE COLLECTION

WEAR LEVELING

FTL

30


DBMS

Flash devices are black boxes! •! Flash devices are not flash chips

"! Do not behave as the flash chip they contain "! No access to the flash chip API but only through the device API "! Complex architecture and software, proprietary and not documented

#! Flash devices are black boxes ! #! DBMS design cannot be based on flash chip behavior!

We need to understand flash devices behavior!

SSD

Flash chips

Read page

Program page

Erase block

Constraints





Write sector

Read sector

No constraint!

MAPPING

GARBAGE COLLECTION

WEAR LEVELING

FTL ?

31


Understanding flash devices behavior

•!Define an experimental benchmark which can exhibit the behavior of flash devices.

•!Define a broad benchmark "! No safe assumption can be made on the device behavior (black box)

–! e.g., Random writes are expensive… "! No safe assumption on the benchmark usage!

•!Design a sound benchmarking methodology "! IO cost is highly variable and depends on the whole device history!

32


Methodology (1): Device state

Random Writes – Samsung SSD Out of the box

! Enforce a well-defined device state "! performing random write IOs of random size on the whole device "! The alternative, sequential IOs, is less stable, thus more difficult to enforce

Random Writes – Samsung SSD After filling the device

33


Methodology (2): Startup and running phases •!When do we reach a steady state? How long to run each test?

Startup and running phases for the Mtron SSD (RW)

Running phase for the Kingston DTI flash Drive (SW)

!! Startup and running phase: Run experiments to define "! IOIgnore: Number of IOs ignored when computing statistics "! IOCount: Number of measures to allow for convergence of those statistics.

34


Methodology (3): Interferences

! Interferences: Introduce a pause between experiments

0.1

1

10

0 250 500 750 1000 1250 1500

Sequential Reads Random Writes

Pause

Sequential Reads

35


Results (1): Samsung, memoright, Mtron

Locality for the Samsung, Memoright and Mtron SSDs

•! When limited to a focused area, RW performs very well

•! For SR, SW and RR, "! linear behavior, almost no latency "! good throughputs with large IO Size

•! For RW, !5ms for a 16KB-128KB IO

Granularity for the Memoright SSD

36


Results (2): Intel X25-E

RW (16 KB) performance varies from 100 µs to

100 ms!! (x 1000)

SR, SW and RW have similar performance.

RR are more costly!

IO size (KB)

Response time (µs)

Response time (µs)

37


Results (3): Fusion IO

•!Capacity vs Performance tradeoff (80 GB # 22 GB!) •!Sensitivity to device state

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38


Conclusion: Flash device behavior Finally, what is the behavior of flash devices? Common wisdom

$!Update in place are inefficient? $!Random writes are slower than sequential ones? $!Better not filling the whole device if we want good performance?

!Behavior varies across devices and firmware updates

!Behavior depends heavily on the device state!

Is it a problem ?

39


Conclusion: Flash device behavior (2)

•! Flash devices are difficult (impossible?) to model!

•! Hard to build DBMS design on such a moving ground!

Bill Nesheim: Mythbusting Flash Performance

•! Substantial performance variability "! Some cases can be even worse than disk

•! Performance outliers can have significant adverse impact

•!What’s Needed: –! Predictable scaling & performance over time –! Less asymmetry between reads/writes, random/sequential –! Predictable response time

(FMS 2011)

40








41


Opening the black box !


42


FTL – Basic components

SSD

Write sector

Read sector

No constraint!

Flash chips

Read page

Program page

Erase block

Constraints





MAPPING

GARBAGE COLLECTION

WEAR LEVELING

FTL

43


FTL – Page Level Mapping •! Basic page level mapping: translation table stored in SRAM

Block 0 Block 1 Block 2 Block 3

Logical

Physical

Translation blocks

Data blocks

Cached Mapping Table

SRAM

Flash

Global Translation Directory

•! Demand-base FTL: DFTL (Gupta et al. 2009) "! The translation table is stored in Flash and cached in SRAM

"! Problem: the table is too large ! (1 GB for 1 TB flash) (4KB pages)

44


FTL - Mapping: Block Level / Hybrid

•! Pure Block Level Mapping "! Translation table at block level "! The page offset remains the same "! Does not comply with C3!

Block 0 Block 1 Block 2 Block 3

Logical

Physical

•! Hybrid Mapping "! Updates done out-of-place in log blocks "! Data blocks # block mapping "! Log blocks # page mapping "! Proposals differ in the way log blocks are managed

–! 1 log block for 1 data block # BAST (Kim et al. 2002) –! n log blocks for all data blocks # FAST (Lee et al. 2007) –! Exploiting locality # LAST (Lee et al. 2008)

"! Cleaning when log blocks are exhausted # Major costs "! Block mapping for data blocks does not either comply with C3!

45


FTL – Garbage Collection

•!With page mapping:

Block 1 Block 2 Block 3 !! !! !! !! !! !!

Block 1 Block 2 Block 3 !! !! !! !! !! !!

Erased

!!

Blo

ck 0

!!

!!

Log(

Blo

ck0)

!!

!! !! !! !!

New

Blo

ck0

Erase Erase

Full Merge Partial Merge Switch

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lock

0 !!

Log(

Blo

ck0)

!!

Erase

!! !!

Blo

ck 0

Log(

Blo

ck0)

!!

Erase

!!

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•!With hybrid mapping: three cases with BAST

New block 0

•! More complex with FAST "! pages of the same block can be on different log blocks

46


FTL-Wear leveling

•! Goal: ensure that all blocks of the flash have about the same erase count (i.e., number of program/erase cycle).

•! Basic algorithm: hot-cold swapping (Jung et al. 2007) "! Swap the blocks with min and max erase count.

•! Difficulties: (1)!When to trigger the WL algorithm (2)!How to manage erase count, how to select min or max erase count block wrt

the limited CPU and memory resources of the flash controler (3)!What wear leveling strategy? (4)! Interactions between Garbage Collection and Wear Leveling

•! The same difficulties arise with garbage collection!

47


MAPPING

GARBAGE COLLECTION

WEAR LEVELING

FTL: Trends

Hybrid mapping

Consider hot/cold data

Detect sequential or semi-random

writes

Temporal/spatial locality?

Background/on demand

Compression /deduplication Security /

encryption

Dynamic / static WL

Caching

Adaptivity

TRIM management

48


FTL designers vs DBMS designers goals •! Flash device designers goals:

"! Hide the flash device constraints (usability) "! Improve the performance for most common workloads "! Make the device auto-adaptive "! Mask design decision to protect their advantage (black box approach)

•! DBMS designers goals: "! Have a model for IO performance (and behavior)

–! Predictable –! Clear distinction between efficient and inefficient IO patterns

! To design the storage model and query processing/optimization strategies "! Reach best performance, even at the price of higher complexity (having

a full control on actual IOs)

These goals are conflicting!

49








50


Minimal FTL: Take the FTL out of equation!

FTL provides only wear leveling, using block mapping to address C4 (limited lifetime)

•! Pros "! Maximal performance for

–! SR, RR, SW –! Semi-Random Writes

"! Maximal control for the DBMS

•! Cons "! All complexity is handled

by the DBMS "! All IOs must follow C1-C3 –! The whole DBMS must

be rewritten –! The flash device is

dedicated

Flash chips

Block mapping, Wear Leveling (C4)

DBMS Constrained Patterns only

(C1, C2, C3) (C1) Write granularity (C2) Erase before prog. (C3) Sequential prog. within a block


Min

imal

flas

h de

vice

51


Semi-random writes (uFLIP [CIDR09]) •! Inter-blocks : Random •! Intra-block : Sequential •! Example with 3 blocks of 10 pages:

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0 10 11 1 20 21 22 2 23 24 12 3 13 14 4 25 26 15 5 16 27 6 7 17 18 19 28 8 29 9

IO address

time

52


Bimodal FTL: a simple idea … •!Bimodal Flash Devices:

"! Provide a tunnel for those IOs that respect constraints C1-C3 ensuring maximal performance

"! Manage other unconstrained IOs in best effort "! Minimize interferences between these two modes of operation

•! Pros "! Flexible "! Maximal performance and

control for the DBMS for constrained IOs

•! Cons "! No behavior guarantees for

unconstrained IOs.

Flash chips

Block map., Wear Leveling (C4)

DBMS unconstrained constr. patterns patterns (C1, C2, C3)

(C1) Program granularity (C2) Erase before prog. (C3) Sequential prog. within a block (C4) Limited lifetime

Bim

odal

flas

h de

vice

Page map., Garb. Coll. (C1, C2, C3)

53


Bimodal FTL: easy to implement •! Constrained IOs lead to optimal blocks

•! Optimal blocks can be trivially "! mapped using a small map table in safe cache "! detected using a flag and cursor in safe cache

•! No interferences!

•! No change to the block device interface: "! Need to expose two constants: block size and page size

16 MB for a 1TB device

Page 0 Page 1 Page 2 Page 3 Page 4 Page 5

Flag = Optimal

CurPos=6

Page 0 Page 1 Page 1’ Page 1’’ Page 0’ Page 2

Flag = Non-Optimal

CurPos=6

54


Bimodal FTL: better than Minimal + FTL Free

(CurPos = 0)

Optimal

TRIM

Garbage collector actions

Write at @ ! CurPos

Write at @ CurPos++

Write at @ CurPos++

TRIM

Non optimal

•! Non-optimal block can become optimal (thanks to GC)

Page 0’ Page 1’’ Page 2

Flag = Optimal

CurPos=3

Page 0 Page 1 Page 1’ Page 1’’ Page 0’ Page 2

Flag = Non-Optimal

CurPos=6

55


Impact on DBMS Design Using bimodal flash devices, we have a solid basis

for designing efficient DBMS on flash:

•!What IOs should be constrained? "! i.e., what part of the DBMS should be redesigned?

•! How to enforce these constraints? Revisit literature: "! Solutions based on flash chip behavior enforce C1-C3 constraints "! Solutions based on existing classes of devices might not.

56


Example: Hash Join on HDD

Tradeoff: IOSize vs Memory consumption

•! IOSize should be as large as possible, e.g., 256KB – 1 MB "! To minimize IO cost when writing or reading partitions

•! IOSize should be as small as possible "! To minimize memory consumption: One pass partitioning needs

2 x IOSize x NbPartitions in RAM "! Insufficient memory # multi-pass # performance degrades!

One pass partitioning Multi-pass partitioning (2 passes)

57


Hash join on SSD and on bimodal SSD

•!With non bimodal SSDs "! No behavior guarantees but… "! Choosing IOSize = Block size (256 KB – 1MB) should bring good performance

•!With bimodal SSDs "! Maximal performance are guaranteed (constrained patterns) "! Use semi-random writes "! IOSize can be reduced up to page size (4 – 16 KB) with no penalty !!Memory savings !!Performance improvement !!Predictability!

58


Summary •! Flash chips

"! Performance & Energy consumption "! Wired in parallel in flash devices

•! Hardware constraints! (C1) Program granularity, (C2) Erase before program, (C3) Sequential program within a block, (C4) Limited lifetime

•! FTL: a complex piece of sofware "! Constantly evolving, no common behavior "! Hard to model "! Hard to build a consistent DBMS design!

59


Simple FTLs

HW Constraints

Bimodal

Predictable & Optimal

Stable Design

Complex FTLs

HW Constraints

Complex FTLs

Unpredictable performance

No stable design

Conclusion: DBMS Design ?

•! Adding bimodality does not hinder competition between flash device manufacturers, they can "! bring down the cost of constrained IO patterns (e.g., using parallelism) "! bring down the cost of unconstrained IO patterns without jeopardizing DBMS

design

60


Tutorial Outline





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114

115


Tutorial Outline





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116

117


Design Space

Query Processor

Storage Manager

OS

FTL Which IOs are issued?

How are IOs scheduled?

How are IOs interpreted?

Cross-layer issues: - Avoid duplicating work

- Split work most effectively - Schedule work most effectively

- Avoid arbitrary limitations

Sources of increased complexity: Improve Performance AND predictability, no stable performance contract at interfaces,

high utilization, d(techno)/dt

FD HW

RAID Controller

118


Performance Contract

- Predictable, unconstrained and inefficient : USB key or low-end SSD

- Predictable, constrained and efficient : mininal FTL

- Unpredictable and unconstrainted

•!Which DBMS functions can efficiently enforce constraints? How? •!Performance Modelling.

Derive constraints for efficient regimes (ad-hoc)

Existing DBMS are probably good enough

Flash Devices Characteristics:

Query Processor

Storage Manager

OS

FTL

FD HW

RAID controller

119


Flash chips trend: Less into the chip: Storage Class Flash

Scaramuzzo (FMS 2010)

120


Dealing with complexity

Figures courtesy of Koschaak and Saltzer

From a memory abstraction (block device)...

... to a communication abstraction (rich interface)

Command Interpreter

send(link_name, outgoing_message_buffer)

ERASE (address)

receive(link_name, incoming_message_buffer)

send(link_name, outgoing_message_buffer)

ERASE (address)

Query Processor

Storage Manager

OS

FTL

FD HW

[Schloser et al, CMU tech report 2003; Schloser et al, FAST 2004; Prabakharan et al., OSDI 2008] RAID controller

121


TRIM command - ATA/ATAPI Command set

Data Set Management command (TRIM) TRIM(LBA) is a hint to FTL to unmap LBA-PBA

•! Unmapping is asynchronous, i.e., fast (if at all executed)

•! Read after TRIM is unspecified

- Pushed by file systems community Supported in Linux kernel 2.6.33+ and Windows 7/2008R2 Implemented in X25

•! X25-M has 80GB capacity, but provides LBA for 74,4 GB

•! Trimming a whole disk does not take it back to factory settings.

122


Beyond TRIM

Slide courtesy of David Nellans, FusionIO, FMS'11

[Nellans et al. FusionIO 2010, Arpaci-Dusseau et al, HotStorage 2010]

123


Atomic Writes

Slide courtesy of , Gary Orenstein Fusion IO

[Prabakharan et al, OSDI 2008; Ouyang et al, HPCA'11]

Problem: partial writes due to system failure during an in-place update Solution: copy on write (InnoDB physiological logging + double write buffer);

atomic write at FTL level improve performance significantly (single write) and reduce DBMS complexity; it also limits concurrency.

124


Co-design: What's next?

- No in-place updates, do we still need WAL? - If we reconsider physiological logging, do we still

need page-based IOs? Do we still need the same representation in memory and on disk?

- Can we leverage prioritized IOs to improve a form of predictability?

- What does extent-based data allocation buy us? - How to efficiently deal with arrays of flash

devices?

125


Take-away Point # 1

&! Flash devices are here to stay Towards high-performance, energy proportionality

&! The key issue is to improve predictability AND performance

As long as flash devices hide flash chip constraints to support any types of IOs, performance characteristics will remain opaque.

126


Take-away Point # 2

&! Need to revisit DBMS design decisions stemming from hard drive characteristics

&! Need to revisit strict layering between DBMS, OS and FTL

The complexity of flash devices should not be abstracted away if it results in unpredictable and suboptimal performance.

127


There is an opportunity for the DB community to stop running after the technology, and influence the

upcoming developments of flash devices

Take-away Point # 3

&! Lot of work in DB community based on FD assumptions

&! The co-design train has left the station. FusionIO and Oracle are leading the way.

system co-design and data management for flash devices ... · ibm research, switzerland stratis d....

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