synthesis of low voltage integrated circuits suitable for analog signal

UNIVERSITY OF PATRAS

SCHOOL OF NATURAL SCIENCE

DEPARTMENT OF PHYSICS

ELECTRONICS LABORATORY

SYNTHESIS OF LOW VOLTAGE

INTEGRATED CIRCUITS SUITABLE FOR

ANALOG SIGNAL PROCESSING

DOCTORATE THESIS

RICHA ARYA

MASTERS OF SCIENCE IN PHYSICS

PATRAS OCTOBER 2013

iii

SYNTHESIS OF LOW VOLTAGE

INTEGRATED CIRCUITS SUITABLE FOR

ANALOG SIGNAL PROCESSING

A dissertation submitted to

The Department of Physics, University of Patras,

for the partial fulfillment of the requirements for the degree of

DOCTOR OF PHILOSOPHY

By

RICHA ARYA

In Supervision of

PROF. IOANNIS HARITANTIS

----------------------------------------------------------------------------------------

Approved by:

----------------------------------------------

Assoc. Prof. Costas Psychalinos

----------------------------------------------

Assit. Prof. Spiros Vlassis

----------------------------------------------

Prof. Vassilis Anastassopoulos

----------------------------------------------

Prof. George Economou

----------------------------------------------

Assist. Prof. Dimitrios Bakalis

----------------------------------------------

Assoc. Prof. Evangelos Zigouris

October 11, 2013

v

This research work is funded by State Scholarship Foundation (IKY).

Copyright © by Richa Arya, October 2013

All rights reserved.

No part of the material protected by this copyright notice may be reproduced or

utilized in any form or by any means electronic or mechanical including photocopying

recording or by any information storage and retrieval system without permission from

the author.

vii

Dedicated to my

Maternal Grandfather

and

Maternal Uncle

ix

ABSTRACT

The electronics industry has developed incredibly in last few years and the

need for low voltage and low power consuming devices is reflected with its growth. A

small extension in battery life can be reflected in an order of magnitude in terms of

retail prices. From multimedia gadgets (like laptops, mobiles, notebook etc.) to the

biomedical device, all applications have seen a rapid advancement. All these devices

need a low voltage and low power transceiver to connect with the wireless networks.

This PhD thesis is focused on the development of new designing techniques for low

voltage, low power integrated circuits, having close attention on circuits suitable for

analog devices.

The vast majority of high performance analog circuit cells realized in metal–

oxide–semiconductor field-effect transistor (MOSFET) technologies traditionally

exploits transistors operating in saturation. Meanwhile there exists a region of weak

inversion, which was left unexploited until recently, where the behavior of a MOS

transistor is similar to a bipolar transistor in qualitative terms. This region could be

exploited for the devices which require operating with low voltage supply. Instead of

operating in saturation region, the MOS devices employed in this design, operate in

weak inversion. The MOS devices in the proposed circuits are bulk-controlled. In the

conventional mode of biasing the bulk terminal is left unused and is connected with

lowest supply voltage or ground while the gate is usually chosen for the input signal

introduction to bias the circuit. The bulk can be used as an input for signal, can lower

the threshold of a transistor if biased properly, ultimately lowering the supply voltage

requirement of the transistor. In this work a modified Nauta’s Transconductor, which

operates on very low voltages and have a tunable transconductance is employed to

design filters. The filter constructed can be tuned in the range of few MHz. The

proposed filter is operated using a 0.5V supply and its cutoff frequency can be easily

adjusted. All circuits are designed and analyzed using a triple well 0.13μm CMOS

process.

This OTA is further modified to achieve better performance, in order to

implement it in a complex filter. In low IF devices the down-conversion of image

signal along with the wanted signal at the same frequency is a major problem.

Complex filter can easily remove this image signal by applying a frequency shifting

x

operation. A sixth order complex filter by implementing Leapfrog technique is

designed using the differential OTA. The filter is designed to meet the Bluetooth and

Zigbee standard requirements. The filter operates on a 0.5V supply voltage, and has

very good results for Image rejection, sensitivity, noise and the filter is orthogonally

tunable. The performance of the filter has been evaluated through simulation results

by employing a triple well 0.13μm CMOS process. This filter design can be

implemented in the Bluetooth devices used for the biomedical applications.

Index Terms: Low voltage devices, Analog integrated filters, Bulk-driven circuits,

Weak Inversion, Operational Transconductor Amplifiers (OTA), Leapfrog technique,

Complex filters.

xi

ΠΕΡΙΛΗΨΗ

Η βιομηχανία της ηλεκτρονικής έχει αναπτυχθεί απίστευτα τα

τελευταία χρόνια και η ανάπτυξη αυτή συνδυάζεται με την ανάγκη για

συσκευές που λειτουργούν σε χαμηλή τάση και με χαμηλή κατανάλωση

ενέργειας. Σε ότι αφορά την εμπορική τιμή, μια μικρή αύξηση της διάρκειας

ζωής της μπαταρίας μπορεί να αντανακλάται σε μια αύξηση κατά μία τάξη

μεγέθους της τιμής. Όλες οι εφαρμογές, από τις συσκευές πολυμέσων (όπως

κινητά τηλέφωνα, φορητούς υπολογιστές, notebook κ.λπ.) έως και τις

βιοϊατρικές συσκευές έχουν δει μια ταχεία πρόοδο. Όλες αυτές οι συσκευές,

για να συνδέονται με ασύρματα δίκτυα, χρειάζονται πομποδέκτη χαμηλής

τάσης και χαμηλής κατανάλωσης ισχύος. Η παρούσα διδακτορική διατριβή

επικεντρώνεται στην ανάπτυξη νέων τεχνικών σχεδιασμού για ολοκληρωμένα

κυκλώματα με έμφαση στα αναλογικά κυκλώματα, χαμηλής τάσης και

χαμηλής ισχύος.

Η συντριπτική πλειοψηφία των δομικών βαθμίδων αναλογικών

κυκλωμάτων υψηλών επιδόσεων πραγματοποιείται σε τεχνολογία μετάλλου

οξειδίου ημιαγωγού τρανζίστορ φαινομένου πεδίου (MOSFET) και

εκμεταλλεύεται τα τρανζίστορ που παραδοσιακά λειτουργούν σε κόρο.

Ωστόσο, υπάρχει η περιοχή ασθενούς αναστροφής, η οποία αφέθηκε

ανεκμετάλλευτη μέχρι πρόσφατα, όπου η συμπεριφορά των τρανζίστορ MOS

είναι παρόμοια με αυτήν των διπολικών τρανζίστορ. Αυτή η περιοχή θα

μπορούσε να αξιοποιηθεί για τις συσκευές που απαιτούν λειτουργία με

χαμηλή τάση τροφοδοσίας. Αντί να λειτουργούν στην περιοχή κόρου, τα

τρανζίστορ MOS που χρησιμοποιούνται σε αυτό το σχεδιασμό, λειτουργούν

σε ασθενή αναστροφή. Τα τρανζίστορ MOS στα προτεινόμενα κυκλώματα

είναι ελεγχόμενα από το υπόστρωμα (bulk-driven). Στο συμβατικό τρόπο

οδήγησης το υπόστρωμα παραμένει αχρησιμοποίητο και συνδέεται με την

χαμηλότερη τάση τροφοδοσίας ή τη γείωση, ενώ η πύλη συνήθως, επιλέγεται

για την εισαγωγή σήματος εισόδου και οδηγεί το κύκλωμα. Το υπόστρωμα

μπορεί να χρησιμοποιηθεί ως είσοδος για το σήμα, μπορεί να μειώσει την

τάση κατωφλίου (threshold voltage) των τρανζίστορ, και τελικά, χαμηλώνει

την τάση λειτουργίας του τρανζίστορ. Σε αυτήν την διδακτορική διατριβή

xii

χρησιμοποιείται ως διαγωγός (transconductor) ένα τροποποιημένο κύκλωμα

Nauta, ο οποίος λειτουργεί σε πολύ χαμηλές τάσεις. Οι ελεγχόμενοι διαγωγοί

χρησιμοποιούνται για το σχεδιασμό των προτεινόμενων συντονιζόμενων

φίλτρων. Τα κατασκευασμένα φίλτρα μπορούν να συντονιστούν στην περιοχή

των λίγων MHz. Τα προτεινόμενα φίλτρα λειτουργούν χρησιμοποιώντας τάση

τροφοδοσίας 0.5V και η συχνότητα αποκοπής τους μπορεί εύκολα να

προσαρμοστεί. Όλα τα κυκλώματα σχεδιάζονται και εξομοιώνονται

χρησιμοποιώντας μία τεχνολογία CMOS triple well 0.13μm.

Ο υπό μελέτη τελεστικός ενισχυτής διαγωγιμότητας (Operational

Transconductor Amplifier - OTA) έχει τροποποιηθεί περαιτέρω, για να

επιτευχθεί καλύτερη απόδοση και να εφαρμοστεί σε ένα μιγαδικό φίλτρο. Η

μετατροπή σήματος από τις μεσαίες συχνότητες (IF) στις χαμηλές συχνότητες

παρουσιάζεται ένα σημαντικό πρόβλημα όπου μαζί με το επιθυμητό σήμα

εμφανίζεται και το σήμα εικόνας στην ίδια συχνότητα. Τα μιγαδικά (complex)

φίλτρα μπορούν να αφαιρέσουν εύκολα το σήμα εικόνας, εφαρμόζοντας μια

διαδικασία μετατόπισης συχνότητας. Ένα μιγαδικό Leapfrog φίλτρο έχει

σχεδιαστεί χρησιμοποιώντας διαφορικούς ενισχυτές διαγωγιμότητας. Το

τελικό μιγαδικό φίλτρο δωδέκατης τάξης έχει σχεδιαστεί για να καλύψει τις

απαιτήσεις του προτύπου Bluetooth και Zigbee. Το φίλτρο λειτουργεί με τάση

τροφοδοσίας 0.5V και έχει πολύ καλά αποτελέσματα στην απόρριψη εικόνας,

την ευαισθησία και το θόρυβο. Επίσης, η κεντρική συχνότητα και το εύρος

συχνοτήτων είναι ανεξάρτητα ρυθμιζόμενα. Η απόδοση του φίλτρου έχει

επαληθευτεί μέσω προσομοίωσης χρησιμοποιώντας μοντέλα τρανζίστορ μιας

τεχνολογίας CMOS triple well 0.13μm. Φίλτρα που σχεδιάζονται με την

προτεινόμενη μέθοδο μπορούν να εφαρμοστούν σε συσκευές Bluetooth που

χρησιμοποιούνται και σε βιοϊατρικές εφαρμογές.

Όροι ευρετηρίου: συσκευές χαμηλής τάσης, αναλογικά

ολοκληρωμένα φίλτρα, Bulk-driven κυκλώματα, ασθενής αντιστροφή (weak

inversion), Operational Amplifiers transconductor (OTA), τεχνική leapfrog,

μιγαδικά φίλτρα.

xiii

ACKNOWLEDGMENT

Someone wise had once said, “If the destination is beautiful, don’t ask about

the pains of the journey, and if the journey is beautiful don’t ask to which destination

it will lead.” And I have a lot of people to thank who have made my journey and

destination both beautiful. This dissertation is the result of work of almost four years,

whereby I have been accompanied and supported by many people, to whom I would

like to express my gratitude.

With a deep sense of gratefulness, I wish to express my sincere thanks to my

supervisor, Prof. Ioannis Haritantis, for his immense help in planning and executing

the work in a timely manner. I am truly grateful to Prof. Costas Psychalinos and Prof.

Spiros Vlassis for providing me with endless support and supervision. Their technical

and editorial advice was essential to the completion of this dissertation and they

taught me innumerable lessons and insights on the workings of academic research.

I am also obliged to Dr. George Souliotis for his immense support and

guidance. Inspite of his busy schedule he has provided his help and guidance, without

his support this quest would not have been easy. Also I would like to thank Dr. Costas

Laoudias and Dr. George Raikos for the help they have provided in understanding

many technical things.

I would like to thank Prof Vassilis Anastassopoulos, Prof George Economou,

Prof. Dimitrios Bakalis and Prof. Evangelos Zigouris for reviewing my thesis.

I thank all the teachers that I have had in my life, who have imparted the

wisdom that has resulted in this work.

I would like to take this opportunity to express my appreciations to all my

friend and colleagues from the University of Patras and from Greece, who have

helped in many ways during last three and half years. There will be many unnamed

Greek people whom I have come across in these last three and half year, whose

kindness and hospitality has made me feel at home in a foreign land, I would like to

thank all of them.

xiv

I would like to express my gratitude to State Scholarship Foundation (IKY),

Greece, for the financial support they have provided, without which this odyssey

would not have be possible.

The two people to whom I believe I owe all and saying just ‘Thanks’ will be

insufficient, are my parents. Still I would like to thank them for believing in me and

supporting me. Also I would like to thank my brother for his love and for standing by

my side every time I needed. Last but not least I would like to thank my friend Anant

Kumar for accompanying me in our journey to pursue our goals together. I am

thankful to many advises he has provided to me.

xv

PUBLICATIONS

JOURNAL

[1] R. Arya, G. Souliotis, S. Vlassis, C. Psychalinos, “A 0.5V 3rd

order tunable

gm-C filter,” Radioengineering, Vol.1, No.1, pp. 174-178, July 2013.

Abstract - This paper proposes a 3rd-order gm-C filter that operates with the

extremely low voltage supply of 0.5 V. The employed transconductor is

capable for operating in an extremely low voltage power supply environment.

A benefit offered by the employed transconductor is that the filter’s cut-off

frequency can be tuned, through a dc control current, for relatively large

ranges. The filter structure was designed using normal threshold transistors of

a triple-well 0.13μm CMOS process and is operated under a 0.5V supply

voltage; its behavior has been evaluated through simulation results by utilizing

the Analog Design Environment of the Cadence software.

[2] R. Arya, G. Souliotis, S. Vlassis, C. Psychalinos, “A 0.5V Tunable Complex

Filter for Bluetooth and Zigbee using OTAs,” Analog Integrated Circuits

Signal Processing Journal, 2013, DOI 10.1007/s10470-013-0241-5.

Abstract - A 12th

-order low voltage tunable differential complex filter for

Bluetooth and Zigbee applications is proposed in this paper. The filter is based

on improved controllable transconductors operating in ultra low supply

voltage of 0.5V. Simulation results using a standard 0.13μm CMOS

technology verify the filter operation fulfilling all the requirements for the

complex filtering stage embedded in Bluetooth/Zigbee receivers. The in-band

group delay variation is 0.79μs for Bluetooth and 0.46μs for Zigbee. The

Image Rejection Ratio is less than 71dB and the achieved in-band SFDR is

42dB.

CONFERENCE

[1] R. Arya, G. Souliotis, I. Haritantis, “Integrated Active Filters using low gain

modules,” ACEEE Int. J. on Control System and Instrumentation, Vol. 03, No.

02, March 2012.

xvi

Abstract - New integrated filters in CMOS technology are presented which

use current mirror based amplifiers to create low gain modules as structural

active blocks. The simplest current amplifiers are purposely chosen. Wave

techniques are used for obtaining high reliability and low sensitivity filters of

any type. The derived filters are modular, simple in structure and easy to

design. Examples in simulation level are given.

xvii

TABLE OF CONTENTS

Abstract .................................................................................................................. ix

Περίληψη ................................................................................................................ xi

Acknowledgment .................................................................................................. xiii

Publications .......................................................................................................... xv

Table of Contents ................................................................................................ xvii

List of Tables........................................................................................................ xxi

List of Figures .................................................................................................... xxiii

1. CHAPTER 01 INTRODUCTION ................................................................................. 1

1.1 Low Voltage Analog Integrated Circuits .......................................................... 2

1.2 Subject and Target of Ph.D. Thesis .................................................................. 6

1.3 Organization of Ph.D. Thesis ............................................................................ 7

1.4 References ......................................................................................................... 8

2. CHAPTER 02 LOW VOLTAGE TECHNIQUES ......................................................... 13

2.1 Introduction ..................................................................................................... 13

2.2 Technology Modification ............................................................................... 14

2.2.1 Thick/Thin Oxide Devices ..................................................................... 14

2.2.2 Low/Zero Threshold Devices ................................................................ 15

2.2.3 Floating Gate Devices............................................................................ 16

2.3 Design Modification ....................................................................................... 16

2.3.1 Input Level Shifting ............................................................................... 17

2.3.2 Switched Operational Amplifier ............................................................ 18

2.3.3 Rail to Rail Input ................................................................................... 19

2.3.4 Bulk Driven MOS .................................................................................. 19

2.4 Bulk driven Technique ................................................................................... 19

2.4.1 Area of Operation .................................................................................. 20

a) Strong Inversion ................................................................................. 21

b) Moderate Inversion ............................................................................ 21

xviii

c) Weak Inversion ................................................................................... 22

2.4.2 Mode of Operation ................................................................................. 23

a) Gate Driven MOSFET ....................................................................... 24

b) Bulk Driven MOSFET ........................................................................ 25

2.5. Advantages and Disadvantages of Bulk Driven MOS .................................. 29

2.5.1 Advantages ............................................................................................ 29

2.5.2 Disadvantages ........................................................................................ 30

2.6 Conclusions..................................................................................................... 31

2.7 References ....................................................................................................... 31

3. CHAPTER 03 A 0.5V OPERATIONAL TRANSCONDUCTOR AMPLIFIER (OTA) ... 37

3.1 Introduction ..................................................................................................... 37

3.2 Nauta’s Transconductor .................................................................................. 38

3.3 Techniques to Improve Nauta’s Transconductor ............................................ 39

3.3.1 Floating gate Method ............................................................................. 39

3.3.2 Input Common Mode Rejection Method ............................................... 40

3.3.3 Pseudo Differential Amplifier with CMFB ........................................... 41

3.3.4 Inverter Based Fully Differential OTA .................................................. 42

3.3.5 Bulk -Controlled Transconductor & Control Circuit............................. 44

3.4 Choice of Nauta’s Transconductor for Bulk Controlled OTA ....................... 49

3.5 Conclusion ...................................................................................................... 49

3.6 References ....................................................................................................... 50

4. CHAPTER 04 DESIGN OF A 0.5V LEAPFROG FILTER .......................................... 53

4.1 Introduction ..................................................................................................... 53

4.2 The Leapfrog Technique ................................................................................. 54

4.3 Filter Design Example .................................................................................... 57

4.4 Simulation Results .......................................................................................... 61

4.4.1 Modification of Aspect Ratio of OTA ................................................... 66

4.5 Conclusions..................................................................................................... 68

4.6 References ....................................................................................................... 68

xix

5. CHAPTER 05 COMPLEX FILTER FOR BLUETOOTH AND ZIGBEE ........................ 71

5.1 Introduction ..................................................................................................... 71

5.1.1 Receiver Architecture ............................................................................ 71

5.1.2 Low IF Receiver Architecture ............................................................... 72

5.1.3 Architectures to Remove Image Signal ................................................. 76

a) Hartley Architecture ............................................................................. 77

b) Weaver Architecture ............................................................................. 77

c) Polyphase/Complex Filters ................................................................... 78

5.2 Theory of Complex Filter ............................................................................... 79

5.3 Complex Integrator ......................................................................................... 82

5.4 Filter Design Example .................................................................................... 86

5.4.1 Bluetooth ................................................................................................ 88

5.4.2 Zigbee .................................................................................................... 90

5.5 Simulation Results .......................................................................................... 91

5.6 Conclusion .................................................................................................... 102

5.7 References ..................................................................................................... 102

6. CHAPTER 06 CONCLUSION ................................................................................ 105

6.1 Summary of this Research Work .................................................................. 105

6.2 Future Proposal ............................................................................................. 107

6.3 References ..................................................................................................... 107

APPENDIX – A ........................................................................................................ 109

Common Mode Rejection Ratio ........................................................................ 109

Power Supply Rejection Ratio .......................................................................... 109

Group Delay ..................................................................................................... 110

Total Harmonic Distortion (THD) ................................................................... 110

Dynamic Range ................................................................................................ 111

Image Rejection Ratio ...................................................................................... 111

Third Order Intercept Point ............................................................................. 112

Spurious Free Dynamic Range......................................................................... 113

APPENDIX – B ........................................................................................................ 115

VITA .................................................................................................................... 117

xxi

LIST OF TABLES

Table 3.1 Performance Comparison of OTAs ............................................................. 48

Table 4.1 Parameter values of the filter with corner variations ................................... 62

Table 4.2 Comparison with other filter topologies ...................................................... 65

Table 4.3 Parameter values of the 3rd

order filter with different aspect ratios ............. 67

Table 5.1 Table of Tuning Current and Capacitance for Bluetooth and Zigbee.......... 89

Table 5.2 Performance characteristics of the proposed complex filter ........................ 98

Table 5.3 Comparison with recent works .................................................................... 99

Table 5.4 Table for Worst Case Performance (Corner Analysis) for Bluetooth ....... 100

Table 5.5 Table for Worst Case Performance (Corner Analysis) for Zigbee ............ 101

xxiii

LIST OF FIGURES

Figure 1.1 Basic model of OTA lossy integrator ........................................................... 4

Figure 2.1 The conventional level shifter. ................................................................... 17

Figure 2.2 Typical output characteristics of a MOSFET ............................................. 20

Figure 2.3 MOS configurations: a) common source, b) common drain and c) common

gate........................................................................................................................ 24

Figure 2.4 Cross sectional view of a) a pMOS with single well and n-well CMOS

technology with b) triple well process and c) buried n-well process ................... 25

Figure 2.5 NMOS Transistor a) with base connected to source so body-source not

forward biased, b) with body-source forward biased, hence decreased depletion

and increased channel charge. .............................................................................. 26

Figure 2.6 a) CMOS device pair, b) Cross section demonstrating the parasitic bipolar

transaction, and c) Schematic of parasitic bipolar transistors creating a positive

feedback. ............................................................................................................... 28

Figure 3.1 Nauta’s Transconductor.............................................................................. 38

Figure 3.2 Balanced Circuit for Linear Conversion ..................................................... 41

Figure 3.3 a) Inverter based fully differential transconductor and b) Nauta’s

Transconductor ..................................................................................................... 43

Figure 3.4 Bulk Controlled Nauta’s Transconductor ................................................... 45

Figure 3.5 a) Amplifier used in the Control Circuit and b) Control Circuit used to

control the tuning Current of Nauta’s Transconductor. ........................................ 46

Figure 3.6 Input Transconductance gm and GBW as function of IT1 ........................... 47

Figure 4.1 The Leapfrog Topology .............................................................................. 53

Figure 4.2 a) Third Order Passive Leapfrog b) Lossy Integrator, c) Lossless Integrator

.............................................................................................................................. 55

Figure 4.3 a) Block Diagram of the Active Ladder Simulating the 3rd

order filter b)

Leapfrog topology for the same filter using an opamp ........................................ 56

xxiv

Figure 4.4 Leapfrog topology for the 3rd

order filter using an OTA ............................ 56

Figure 4.5 The Double Input differential OTA ............................................................ 57

Figure 4.6 a) The Circuit of Differential Amplifier and b) Schematic diagram of the

control circuit ........................................................................................................ 59

Figure 4.7 Filter Topology a) passive prototype and b) active implementation .......... 60

Figure 4.8 a) Passive 3rd

order filter and b) its Signal Flow Graph. ............................ 60

Figure 4.9 Cutoff Frequency of the Filter as function of IT1 ........................................ 61

Figure 4.10 Frequency Response for a range of IT1 from 10μΑ to 80μA .................... 63

Figure 4.11 Monte Carlo simulation results for the filter cutoff frequency ................. 64

Figure 4.12 Transconductance of the OTA with respect to Tuning Current ............... 66

Figure 5.1 Front end stage of a Low IF receiver .......................................................... 72

Figure 5.2 Down-conversion of signal with a real LO sinusoidal signal..................... 73

Figure 5.3 Down-conversion of signal with a single exponential ............................... 75

Figure 5.4 Front end diagram of basic Low IF Architecture ...................................... 76

Figure 5.5 Block Diagram of the Hartley Receiver Architecture ................................ 77

Figure 5.6 Block Diagram of the Weaver Receiver Architecture ................................ 78

Figure 5.7 Front-end stage block diagram of low-IF receiver using a complex filter . 79

Figure 5.8 Frequency Shifter of a complex mixer. a) Before complex mixing and b)

After Complex Mixing ......................................................................................... 80

Figure 5.9 Frequency shifting effect on a) Transfer Function b) Pole locus of a real

low-pass filter ....................................................................................................... 81

Figure 5.10 Diagram showing frequency shifting to convert LPF to Complex BPF .. 82

Figure 5.11 Block Diagram of Lossless Integrator ...................................................... 84

Figure 5.12 Block Diagram of Lossy Integrator .......................................................... 84

Figure 5.13 Double differential Input transconductor ................................................. 85

Figure 5.14 Passive 6th

order filter ............................................................................... 85

Figure 5.15 Signal Flow Graph for 6th order complex filter ....................................... 86

xxv

Figure 5.16 a) Block Diagram of the Active Ladder Simulating 6th

order Leapfrog

filter topology b) Leapfrog topology for the 3rd

order filter using OTA .............. 87

Figure 5.17 12th

order complex filter. .......................................................................... 88

Figure 5.18 a) Amplifier of the tuning circuit and b) Tuning Circuit used in the OTA

.............................................................................................................................. 90

Figure 5.19 Frequency Response of Signal and Image frequency for Bluetooth ........ 91

Figure 5.20 Frequency Response of Signal and Image frequency for Zigbee ............. 92

Figure 5.21 Group Delay for Bluetooth ....................................................................... 92

Figure 5.22 Group Delay for Zigbee ............................................................................ 93

Figure 5.23 Tuning of Center Frequency with tuning current ITB for Bluetooth ......... 94

Figure 5.24 Tuning of Bandwidth with tuning current ITA for Bluetooth .................... 94

Figure 5.25 IIP3 Curve for in-band linearity for Bluetooth filter ................................ 95

Figure 5.26 IIP3 Curve for in-band linearity for Zigbee filter ..................................... 95

Figure 5.27 Monte Carlo analysis responses for Bluetooth ......................................... 96

Figure 5.28 Monte Carlo analysis responses for Zigbee.............................................. 96

Figure 5.29 Monte Carlo analysis for bandwidth of Bluetooth filter .......................... 97

Figure 5.30 Monte Carlo analysis for bandwidth of Zigbee filter ............................... 97

1

1. CHAPTER 01 INTRODUCTION

INTRODUCTION 01

In the last 100 years the technology has evolved from the simple passive filters

which were used in radios to the vast variety of active filters VLSI circuits, employed

from space engineering to biomedical applications. From huge vacuum tubes the

circuits have evolved to small silicon chips, which are now entering in the phase of

nanotechnology. Along with this the obligation towards the smaller consumption of

power and supply voltage has also increased. The miniaturization of circuits has made

it a necessity that they consume smallest possible amount of voltage and power. The

decrease in channel length and increase in the number of components per chip has

made the advent of low voltage low power circuits unavoidable [1.1]. In the last two

decades the portable devices such as laptops, mobile, smart phone have become a part

of daily life, the technology is evolving at a very rapid rate and with this the demand

of low power low voltage circuits has also inflated. Since almost all of these devices

are battery operated, it has become an urgency to produce circuits which consume

least of supply voltage and current. A small decrease in supply voltage or current

consumption mean an increased battery life it will be reciprocated in the price of the

product and will increase chances of survival in case of a bio-medical application.

These devices need to be connected to the wireless network WLAN, and at this stage

they need a transceiver. With this the development of transceiver device which may

operate at low voltage has become a call of time.

Chapter 01 Introduction

2

1.1 LOW VOLTAGE ANALOG INTEGRATED CIRCUITS

In VLSI circuits with increased number of transistors integrated on a single chip,

the digital and analog circuits can be integrated together resulting in the reduced cost

of production [1.2]. While digital circuits have their importance because of their faster

speed and smaller production cost, the analog circuits have their important role as an

inevitable interface between the analog/physical and digital world. Eventually the

performance of the digital technology depends upon the appropriately designed

analog circuits. With miniaturization of technology the requirement of smaller power

and supply voltage is fated. The demand of low power low voltage supply has become

urgent in recent years [1.3]. It is requisite to design analog circuits which operate with

low supply voltage and power analogous to the digital circuits.

The main obstacle to the high performance analog circuits design is the low power

supply voltage and relatively higher device threshold voltages. The circuit power

consumption must be increased to reduce errors from thermal noise and offset

voltages along with it there exists another issue of smaller swing for smaller voltage.

Typically the devices are biased in moderate or strong inversion, and they provide

little voltage headroom, making it a challenge to design low voltage devices. The

supply and power requirements of a circuit can be reduced by two methods, first by

the improvement in technology (technology modification) and second by innovating

the circuit design (circuit design solutions) [1.4].

The first method to achieve technology modification is to introduce thick oxide

devices; they can work without breaking down with larger supply voltage but these

devices are relatively slower.[1.5]. In the second method, the voltage headroom can

be increased by introducing low threshold VT or zero threshold devices, this process

may decrease the required operating voltage but it does not help with the widening the

voltage range [1.6]. Third method is to use Floating gate devices, in this method the

gate is surrounded by a high quality insulator to prevent leaking off of the charge by

floating node, by creating a potential barrier [1.7]. Due to parasitic capacitance

between the floating gate and drain, source, bulk terminal, the effective

transconductance of floating gate device decreases. Also floating gate MOSFETs

1.1 Low Voltage Analog Integrated Circuits

3

have lower gain than the conventional transistors, because of increased output

conductance arising from feedback between drain potential and potential at the

floating gate [1.8]. This technology may cause additional device stress because the

internal gate voltages may become higher than supply rails [1.4].

Another way to lower the required supply voltage is by design modification. It

should be noted that the innovated new design techniques for low voltage circuits will

have their applicability and significance even if the low voltage technology will

become standard [1.9]. Several design modification techniques have been proposed to

obtain low supply low power devices without undergoing technological changes.

[1.9]-[1.18] First among these is input level shifting technique which although

promises ultra-low voltage operation by different designs, but suffers from the

drawback of the complexity of the design [1.11]. Switched opamp/ switched capacitor

technique offers a solution to the challenge encounter in operating circuits at low

voltage [1.14]. In this techniques On/Off switching opamps, replace the critical

switches of a switched capacitor circuit [1.12]. The technique is quite effective to

implement low voltage discrete time filter and [1.14] ΣΔ modulator [1.13], although it

suffers from limited slew rate and low signal input range,[1.14][1.15]. The rail to rail

architecture also promises to work with low supply. The traditional approach of

connecting p-channel and n-channel in parallel suffers from variation in small signal

and large signal behaviors [1.16]. The other methods either suffer from circuit

complexity and/or are subjected to process and temperature tolerance because of the

limitations of implementing matching gm values of devices used in the circuit [1.9],

[1.17]. Multipath Nested Miller Compensation (MNMC) is another method which

promises to operate with low supply. While Nested Miller Compensation (NMC)

causes a bandwidth reduction, MNMC offers increased bandwidth but at the cost of

increased complexity at the technology and circuit level both [1.18]. Another

technique employing current mirror based low gain modules may be improvised to

operate at low voltages.[1.19].

Another simpler method is to use bulk driven MOS. In the conventional manner of

biasing a MOS the input is fed through the gate and bulk is connected to the most

negative voltage or ground. In a bulk driven circuit the input signal is feed in the


4

circuit through the bulk or substrate terminal. The basing with bulk serving as input

for signal also removes or reduces the possibilities of phenomenon like body effect

and latch-up, alongside reducing the threshold voltage thus lowering the supply

voltage requirement to drive the transistor [1.21].

In this method the device works in weak inversion i.e. for a NMOS device

operating in weak inversion

VGS-Vth ≤ 0 V

At room temperature VDS of 0.1 V to 0.125 V is sufficient to keep the device in

saturation, so a VDS (drain-source voltage) of 0.15 is sufficient to keep a NMOS in

saturation. This allows sufficient headroom for operation in voltage as low as 0.5 V.

Also transconductance verses current (i.e. gm/I) efficiency is higher in weak inversion

operation, making it a suitable choice for low power application [1.4].

The main circuit block used in this work is an Operational Transconductor

Amplifier more commonly known as OTA. The OTA designs are simpler,

programmable and have lesser number of components compared to an opamp and the

transconductance gain is tunable by an external control. Simplified form of an all

OTA integrator design, employed in the circuits is shown in Figure 1.1, as it contains

no passive components/resistor, its gain can be adjusted in a wider range, and since all

OTAs are on a single chip, they suffer less from mismatch variation.

Figure 1.1 Basic model of OTA lossy integrator

1.1 Low Voltage Analog Integrated Circuits

5

The OTA allows more flexibility, the pole frequency of the filter can be adjusted

by the input OTA i.e. by gm1 while dc gain by feedback OTA i.e. by gm2, to control

circuit/system parameters, setting voltage gain of amplifiers or for compensating the

tolerances due to temperature or process variations.

Since many designs don’t use resistance and only use capacitors they are attractive

for integration and are independently tunable [1.20]. The gmC integrators which have

minimal or zero node, and use negative resistance, like the Nauta’s transconductor

[1.10] used in this research, allow the design to achieve higher bandwidth and better

DC gain. To improve the linearity of the designed circuits and because of

requirements of filter circuit design, a fully differential OTA is chosen. The fully

differential OTA are less susceptible to interference, also offer greater range of the

signal. The CMOS devices in the circuits are biased to work in weak inversion. With

this the requirement to operate in ultra-low voltage is achieved, and the OTA is

employed to design filters of higher order and complexities.

The OTA is further utilized to design a complex filter operating for very low

supply of 0.5 volts, suitable for Bluetooth and Zigbee. In the low IF receivers, image

signal down-converted at the same frequency as the wanted signal imposes a serious

problem. The image frequency is an undesired input frequency equal to the station

frequency plus twice the intermediate frequency resulting in two stations being

received at the same time, thus producing interference. Various methods like Hartley

Architecture, Weaver Architecture, passive polyphase filter and active polyphase

filter are proposed to remove the image signal [1.22]. An active complex filter is a

suitable option among these, considering the requirement of low supply voltage and

power consumption. An OTA with bulk controlled MOS is employed to design the

complex filter using leapfrog technique. The designed complex filter is suitable to

operate for Bluetooth and Zigbee standards. Considering that it can operate for the

ultra-low voltage of 0.5V, this complex filter may be used for application in

biomedical devices.


6

1.2 SUBJECT AND TARGET OF PH.D. THESIS

The main goal of this research is to design low voltage analog circuits. In this

thesis fully differential OTA are employed to design low voltage filters. As the fully

differential designs offer better linearity and wider tuning range, they are preferred for

low voltage circuits.

The thesis starts with analyzing and comparing various low voltage techniques,

and bulk driven circuits. The bulk driven circuits are further discussed and the

technique is employed to improve Nauta’s transconductor, which is an important

building block of the filters designed later. In the design of Nauta’s transconductor the

improvements are made in the form of adding the bulk node with newly designed

tuning circuit. Being operated in weak inversion this design offer implementation in

very low voltage of 0.5 V and because of the absence of internal nodes a good tuning

range is observed. These qualities make this OTA a perfect choice for its

implementation in low voltage circuits as will be discussed in the later parts of this

thesis. In the next part of thesis, the implementation of the improved Nauta’s

transconductor in a third order low pass filter is discussed.

The last part of the thesis deals with complex filters technique and its application

for designing a 12th

order filter suitable for Bluetooth and Zigbee implementations.

An image signal is a serious problem in the low IF architectures. The real filters are

unable to remove image signal, hence the complex filters are employed to remove

them from the required signal. A complex filter simply acts as frequency shifter,

shifting the central frequency of a low pass filter to the Intermediate frequency, and

hence transforming a low pass filter into a band pass filter rejecting the image signal.

A 12th

order complex filter suitable for Bluetooth and Zigbee standards operating

with 0.5V supply voltage is designed and tested. All the circuits are designed using

triple well 0.13μm CMOS technology. The design, simulation and analysis of the

circuits presented in this thesis were performed using the Virtuoso Platform of

Cadence.

1.3 Organization of Ph.D. Thesis

7

1.3 ORGANIZATION OF PH.D. THESIS

In this section each chapter of this thesis will be discussed in brief. The second

chapter is about the low voltage techniques, and is focused on the bulk driven circuits.

Various low voltage techniques are discussed and their pros and cons are compared.

Later the bulk driven MOS designs are discussed in detail. The conventional way of

operating a transistor is driving it through the gate. The low power supply voltages

and the relatively large device threshold voltages are an obstacle to high performance

analog circuit design. Back gate or body driven circuit technique is one of the several

circuit techniques which have been proposed to allow circuit design at low voltages.

The main benefits of a bulk driven circuit are linear and constant gm

(transconductance) and rail to rail input, which makes them perfect for building rail to

rail operational amplifiers.

In the third chapter the operation of Nauta’s transconductor is discussed. The

Nauta’s transconductor is very robust design which is based on six CMOS inverters

connected in differential mode [1.10]. The transconductor was meant for high-

frequency gmC filter, because of absence of internal node it can be implemented in the

low-frequency applications as well. However the design suffers from bad CMRR and

PSRR results. Various designs, proposed to improve the CMRR performance and

lower the supply voltage are discussed. The transconductor is modified and the bulk

of the CMOS in the inverters of the transconductor are connected to a new tuning

circuit. The original Nauta’s transconductor was tuned by voltage, while this

transconductor is tuned by current through a tuning circuit based on master slave

operation technique.

The fourth chapter is about a 3rd

order tunable gmC filter, designed using the

modified Nauta’s transconductor, employing leapfrog technique. The filter operated

for extremely low voltage of 0.5V and is tunable through a dc control current for a

relatively large range and has good linearity results as well. The design is further

modified to achieve better gain and linearity.


8

Complex filters are one of the various methods like Hartley architecture, weaver

architecture complex ΣΔ-ADC architecture and active polyphase filter, to remove

image signals in the low IF receivers [1.22]-[1.26]. The previously discussed

transconductor is further modified to have differential inputs and is implemented in

designing a 12th

order complex filter using leapfrog technique. The filter is applicable

for the Bluetooth and Zigbee standards. In the fifth chapter the proposed complex

filter is discussed.

In the sixth and the final chapter the conclusion of this research and the future

prospective are presented. On the basis of presented designs and technology in this

research, the basic objectives of this work are analyzed and the future chances of

evolving and implementing it further are discussed.

Concluding the thesis in Appendix-A basic concepts and definitions of design

parameters used for analyzing the filters designed in this work are presented, and in

Appendix-B, some basic operations of an OTA are summarized.

1.4 REFERENCES

[1.1] C. J. B. Fayomi, M. Sawan and G. W. Roberts, “Reliable circuit

techniques for low voltage analog design in deep submicron standard

CMOS: A Tutorial”, Analog Integrated Circuits and Signal Processing,

Vol.39, pp. 21-38, April 2004.

[1.2] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and

Design of Analog Integrated Circuits”, 4th edition, John Wiley and Sons,

New York, 2001.

[1.3] “The International Technology Roadmap for Semiconductors ITRS, 2011,

Tech. Rep.” http://public.itrs.net.

[1.4] S. Chatterjee, K. P. Pun, N. Stanic, Y. Tsividis and P. Kinget, “Analog

circuit Design Techniques at 0.5V”, Springer, ISBN. 0387699538, 2007.

1.4 References

9

[1.5] A. J. Annema, B. Nauta, R. Van Langevelde, H. Tuinhout, "Analog

circuits in ultra-deep-submicron CMOS," IEEE Journal of Solid-State

Circuits, vol.40, no.1, pp.132-143, Jan. 2005.

[1.6] S. S. Bazarjani, W. M. Snelgrove, "Low voltage SC circuit design with

low -Vt MOSFETs," IEEE International Symposium on Circuits and

Systems, vol.2, no.30, pp.1021-1024 Apr-3, May 1995.

[1.7] V. Srinivasan, D. W. Graham, P. Hasler, "Floating-gates transistors for

precision analog circuit design: an overview," 48th Midwest Symposium on

Circuits and Systems, vol.1, pp.71-74, 2005.

[1.8] S. Sharma, S. S. Rajput, S. S. Jamuar, “Floating-gate MOS Structure and

Applications” IETE Tech Rev; vol. 25, pp. 338-45, 2008.

[1.9] S. Karthikeyan, S. Mortezapour, A. Tammineedi, E. K. F. Lee, "Low-

voltage analog circuit design based on biased inverting opamp

configuration," IEEE Transactions on Circuits and Systems II: Analog and

Digital Signal Processing, vol.47, no.3, pp.176-184 Mar 2000.

[1.10] B. Nauta, "A CMOS transconductance-C filter technique for very high

frequencies," IEEE Journal of Solid-State Circuits, vol.27, no.2, pp.142-

153, Feb 1992.

[1.11] J. L. Ceballos, “The differential floating level shifter: application

examples” IBERCHIP, 2002.

[1.12] J. Crols, M. Steyaert, "Switched-opamp: an approach to realize full CMOS

switched-capacitor circuits at very low power supply voltages," IEEE

Journal of Solid-State Circuits, vol.29, no.8, pp.936-942, Aug 1994.

[1.13] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, W. Sansen, "A 900

mV 40 μW switched opamp ΔΣ modulator with 77 dB dynamic range,"

IEEE International Solid-State Circuits Conference, Digest of Technical

Papers. pp. 68-69, Feb. 1998.

[1.14] Α. Baschirotto, R. Castello, "A 1-V 1.8-MHz CMOS switched-op-amp SC

filter with rail-to-rail output swing," IEEE Journal of Solid-State Circuits,

vol.32, no.12, pp.1979-1986, Dec 1997.


10

[1.15] Α. Baschirotto, "A low-voltage sample-and-hold circuit in standard CMOS

technology operating at 40 ms/s," IEEE Transactions on Circuits and

Systems II: Analog and Digital Signal Processing, vol.48, no.4, pp.394-

399, Apr 2001.

[1.16] J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, J. L. Aus n, "Constant-gm

constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input

stage for VLSI cell libraries," IEEE Journal of Solid-State Circuits,

vol.38, no.8, pp.1364-1372, Aug. 2003.

[1.17] W. R. White, "A high bandwidth constant gm and slew-rate rail-to-rail

CMOS input circuit and its application to analog cells for low voltage

VLSI systems," IEEE Journal of Solid-State Circuits, vol.32, no.5, pp.701-

712, May 1997.

[1.18] R. G. H. Eschauzier, L. P. T. Kerklaan, J. H. Huijsing, "A 100-MHz 100-

dB operational amplifier with multipath nested Miller compensation

structure," IEEE Journal of Solid-State Circuits, vol.27, no.12, pp.1709-

1717, Dec 1992.

[1.19] R. Arya, G. Souliotis, I. Haritantis, “Integrated Active Filters using low

gain modules,” ACEEE Int. J. on Control System and Instrumentation,

Vol. 03, No. 02, pp. 35-37, March 2012.

[1.20] R. L. Geiger and E. S. Sinencio, “Active Filter Using Operational

Transconductor Amplifiers: A tutorial,” IEEE Circuits and Devices

Magazine, Vol. 1, pp. 20-32, March 1985.

[1.21] R. L. Geiger, P. E. Allen, N. R. Strader, “VLSI Design Techniques for

Analog and Digital Circuits,” McGraw-Hill Publishing Company, 1990.

[1.22] B. Razavi, RF Microelectronics, Englewood Cliff’s NJ: Prentice-Hall,

1998.

[1.23] A. A. Emira, E. S. Sinencio, "A pseudo differential complex filter for

Bluetooth with frequency tuning," IEEE Transactions on Circuits and

Systems II: Analog and Digital Signal Processing, vol.50, no.10, pp.742-

754, Oct. 2003.

1.4 References

11

[1.24] F. Behbahani, Y. Kishigami, J. Leete, A. A. Abidi, "CMOS mixers and

polyphase filters for large image rejection," IEEE Journal of Solid-State

Circuits, vol.36, no.6, pp.873-887, June 2001.

[1.25] K. Philips, "A 4.4mW 76dB complex ΣΔ ADC for Bluetooth receivers,"

IEEE International Solid-State Circuits Conference Digest of Technical

Papers. ISSCC, vol.1, pp.64,478, Feb 2003.

[1.26] W. Sheng, B. Xia, Α. Α. Emira, C. Xin, Α. Υ. Valero-Lopez, S. T. Moon,

Ε. S. Sinencio, "A 3 V, 0.35 μm CMOS Bluetooth receiver IC," IEEE

Radio Frequency Integrated Circuits (RFIC) Symposium, pp.107-110,

2002.


12

13

2. CHAPTER 02 LOW VOLTAGE TECHNIQUES

LOW VOLTAGE

TECHNIQUES

02

2.1 INTRODUCTION

The technology today has invaded every part of life. Today entertainment

doesn’t mean a huge television sitting in the corner of a room, neither does

information means just an early morning newspaper, health care has also not

remained limited to mechanical instruments only. The miniaturization and

advancement of technology has not just improved the life style, but life span as well.

With invasion of technology in every part of life the challenges to evolve it have also

increased. An important field of innovation is in reduction of supply and power

consumption of the circuit employed in the various devices. The desired to increase

battery life, decrease in channel length, and increase in number of components per

chip have led to advent of circuits of low supply.

The advent of technology has made sure that analog and digital circuits can be

fabricated on the same chip. This advancement has created the requirement of low

voltage analog circuits which can complement the digital circuits, which is indeed a

difficult task to accomplish for analog circuits. The supply voltage requirements have

decreased from 5V to 1.2 V in the last two decades, although a further lowering of

supply voltage for analog circuits is much desired but equally difficult task for the

designers. As discussed earlier the supply voltage and power consumption of a circuit

can be decreased by two methods, technology modification and design modification.

Chapter 02 Low Voltage Techniques

14

Which of these techniques will be chosen by a designer largely depends on the

requirements of the circuits and the application cost.

2.2 TECHNOLOGY MODIFICATION

The supply requirement of a circuit can be reduced by making changes in the

designs or material employed in the manufacturing of the transistor this process is

categorized as Technology Modification. The decrease in signal headroom with

lowering of supply and problem of gate leakage are the issues to be dealt with while

making advance technologies for low supply voltage [2.1]. The methods which come

under this category are discussed here.

2.2.1 THICK/THIN OXIDE DEVICES

The threshold voltage Vth, [2.2] when substrate bias is present, of a NMOS

transistor is given by

(2.1)

where Vt0 is threshold voltage for zero substrate bias, 2φf is the surface potential, Vsb is

the source-to-body substrate bias and ‘γ’ is threshold voltage parameter, given by

(2.2)

where q is the charge of electron, ε is the permittivity of silicon, NA is a doping

concentration and Cox is oxide capacitance, expressed by

(2.3)

where εox is oxide permittivity and tox is oxide thickness parameter.

2.2 Technology Modification

15

From the equations given above, it is evident that threshold voltage Vth is

directly proportional to γ and tox, which is parameter for oxide thickness. It can be

observed that thinner will be the oxide layer thickness, smaller will be the threshold

voltage. A hybrid use of thick and thin film oxide device can be used to gain a balance

between speed and voltage capability [2.3], solving the low voltage and gate leakage

problem. Although this seems a promising option, this method is not very cost

effective.

2.2.2 LOW/ZERO THRESHOLD DEVICES

The challenge faced in reducing the supply voltage of an analog device is the

fact that to operate the device the supply voltage must be higher than threshold

voltage and there must be a difference between them to provide sufficient headroom

for the operation of the device. An effective way to reduce supply voltage of a circuit

is to reduce the threshold voltage of the device. Low-Vth MOSFET called “natural”

transistor with threshold voltage around 0.2V-0.3V, are possible to make in some

n+/p

+ poly gate processes [2.4].

This process deals with the problem of leakage current in the off phase of a

transistor. The sub-threshold off-current [2.5] for a transistor operating in saturation is

given by

(2.4)

where ID0 is the off current for VGS set at Vth, and S is sub-threshold swing. From eq.

(2.4) it can be seen that off current increases with decrease in threshold voltage Vth.

This sub-threshold off current further causes parasitic voltage which is non-linear

function of Input signal and reduces the dynamic range of the analog operation. By

reducing the signal swing the error due to sub-threshold off current can be reduced.

Another issue of process variation and variation of Vth with temperature is also a

major problem with Low threshold MOSFET. This can be solved with back biasing,

which uses negative feedback to keep drain, source and bulk reverse biased all the

time [2.5]. Although low-threshold device gives increased headroom by lowering the


16

threshold voltage, it requires extra circuitry to manage the sub-threshold off-current,

which is a big drawback.

2.2.3 FLOATING GATE DEVICES

The Floating Gate MOS’s (FGMOS) structure is similar to a conventional

MOSFET. The difference is the gate which is electronically isolated, creating a

floating node in DC, and a number of secondary gates electrically isolated from the

floating gate (FG), above which they are deposited. There exist only capacitive

connection between inputs and FG [2.6]. This FG which is completely surrounded by

highly resistive material serves as charge storage device. Therefore the first

application of the FGMOS was to store digital data in EEPROM, EPROM and flash

memories. Along with this these devices show easy addition and compression of

voltage signals, as well as allow a reduction of the effective threshold voltage. The

threshold voltage of a floating gate transistor can be controlled by the amount of the

static charge stored in the floating gate. This property has prompted their use in low

voltage low power analog circuits [2.7]. However, the programming techniques

require high voltage or currents to inject charge, and also they need complex circuits

[2.9]. The floating gate MOS give a promising result as a suitable device for low

voltage low power circuits, but they are poor in terms of gain, output impedance

because of parasitic capacitance, and their frequency response is limited to the small

frequencies [2.8] - [2.10].

Some other technological innovations are done to reduce the voltage and

power of an analog circuit like Multi-threshold process, Bi-CMOS technology,

Octagonal MOS [2.11]. Although these processes give some promising results but

they come at the expense of more processing steps and hence higher production cost

[2.9].

2.3 DESIGN MODIFICATION

While technology modification give propitious new technologies which will

find their way in application even with the new circuits, but the technology

modifications have their limitations in terms of applications as well and they are not

2.3 Design Modification

17

Figure 2.1 The conventional level shifter.

cost effective also. The other way of reducing voltage and power requirements of a

circuit is to modify the circuit design. Some of these design modifications are to be

pointed here.

2.3.1 INPUT LEVEL SHIFTING

Voltage Level Shifters are the circuit used to communicate between low

voltage level and high voltage level. In conventional Level Shifter the shifting is

achieved by cross coupled PMOS and NMOS Latches, shown in Figure 2.1 where the

complementary inputs In and InB drive PMOS and NMOS transistors. Conventional

Level Shifters have problems when voltage difference between low supply voltage

and high supply voltage becomes large [2.12].

Various circuit modifications are proposed to solve the above mentioned

problem, like the use of Wilson Current Mirror [2.13], PMOS diodes [2.14], Clustered

Voltage Scaling (CVS) [2.15], bootstrapping of gate nodes [2.16] [2.17], using a

second threshold voltage [2.18], and by adding PMOS and NMOS additional devices

and providing non-conflicting rise and fall path by a feedback loop [2.19]. These

circuits are complex and require large area because of capacitors used in them or

require extra programming circuitry.


18

2.3.2 SWITCHED OPERATIONAL AMPLIFIER

The MOSFET switches which need to pass voltage in the mid-range of the

supply are the main problem in the operation of switch capacitor circuits at low

voltages. Switched capacitor filters are very accurate, linear and have low distortion

even at low supply voltages. However their performance degrades at very low

voltages due to signal swing reduction caused by the switches. Switched opamp

technique in which capacitors are replaced with opamps., switching on and off, is an

effective solution to this problem. The minimum supply voltage for an OTA [2.20]

can be approximately given as

(2.5)

The minimum supply voltage for n-switch is

(2.6)

By comparing eq. (2.5), it can be seen that a rail-to rail operation with CMOS

OTA can be achieved if VTn or │VTp│<Vswing/2. According to eq. (2.6) and extra

voltage drop VTn is required to have a rail-to rail operation, which cannot be reached

with a single NMOS switch. But eq. (2.6) does not hold true for all the switches in a

switched capacitor circuit. Most switches do not require power supply more than an

OTA or an opamp, and hence switchable opamps can replace those switches which

require more power supply. The technique is quite effective to implement low voltage

discrete time filter [2.21] and ΣΔ modulator [2.22], although it suffers from limited

slew rate and low signal input range [2.21],[2.23].

2.4 Bulk driven Technique

19

2.3.3 RAIL TO RAIL INPUT

A rail to rail i/o opamp is an opamp where the inputs and the output can swing

between the full power supply range. The devices with rail-to rail inputs are designed

especially for low power supply operation. Designing a rail-to-rail output stage with a

class A or AB output is easier comparing to rail-to-rail input stage. A simple p and n-

channel differential pair, rail-to rail input suffers from decreased effective

transconductance and large signal output current [2.24]. Methods with improved gm

and slew rate and low supply are proposed [2.25][2.26]. However the complexity of

the design is a serious drawback of this method.

A multi-stage amplifier with nested miller compensation (MNMC) structure is

another version of this technique which offers better linearity for a given power

consumption [2.27][2.28]. MNMC structure overcomes the bandwidth reduction of

nested miller compensation. In NMC a miller capacitor is introduced for every gain

stage closing a wider feedback loop. While in MNMC structure the intermediate stage

of high frequencies is by-passed and the multipath stage directly drives the output

transistor. This method also suffers from increased use of circuits and hence

consumes greater surface area for integration

2.3.4 BULK DRIVEN MOS

The bulk/body can play a significant role in lowering the threshold voltage of

a MOS. The voltage requirement of a circuit can be reduced by operating a MOS in

sub-threshold region. The bulk driven technique is discussed in details in the next

section of the chapter.

2.4 BULK DRIVEN TECHNIQUE

The conventional way of biasing a MOSFET is applying the supply voltage at

gate. In this method the bulk or body of the MOS is left unused or is connected to

source. An unconventional way to control the operation of a MOS is by controlling it

through the bulk. According to the equation given below, the threshold voltage is


20

Figure 2.2 Typical output characteristics of a MOSFET

(2.7)

where VBS is the bulk source voltage, Vth0 is the threshold voltage for VBS=0, γ is the

bulk threshold parameter and Φ is the strong inversion surface potential. It is evident

from the equation that the bulk voltage also plays a role in controlling the threshold

voltage of MOS [2.29]. By increasing VBS the threshold voltage can be reduced which

will play a role in lowering the supply voltage of the circuits. Along with this supply

voltage can be considerably affected by the choice of the region of operation of MOS.

2.4.1 AREA OF OPERATION

Depending on the voltage at the terminal the MOSFET can be operated in

different regions, namely cut-off, sub-threshold or weak inversion, saturation and

linear region. When VGS<Vth, where, VGS is gate-to-source bias and Vth is the threshold

voltage of the device the MOS is said to be operating in cut-off region. The transistor

is turned off and there is no current between drain and source. However this is the

ideal situation, but in practice there exists a weak inversion current called sub-

threshold current which is exponentially dependent upon VGS. The transistor is

http://en.wikipedia.org/wiki/Threshold_Voltage

http://en.wikipedia.org/wiki/Threshold_Voltage


21

supposed to be working in ohmic or linear mode when VGS>Vth and VDS<(VGS – Vth ).

In this region transistor is turned ON, and a current flows between drain and source.

When VGS>Vth and VDS≥( VGS – Vth ) the switch is turned ON allowing a current

between drain and source, this region is called saturation or active region, as shown

in Figure 2.2. The on-set of this region is called pinch-off. It is the region in which

MOS is operated for linear applications. The characteristic transition of transistor

from ohmic to cut-off region and vice-versa is utilized in digital circuits, while in

analog circuits the circuit operates in the active region.

In a DC model of a MOS, for the sake of theoretical study, it is assumed that drain

current is zero for VGS<Vth and non-zero for VGS>Vth. However in practical application

the situation is quite different, there exists a small current for VGS<Vth, which is small

enough to be assumed as zero for majority of application [2.29]. But this small value

of current can prove useful for applications where small supply voltage is required.

Thus the region where an analog circuit may be operated is divided in three, strong

inversion, moderate inversion and weak inversion.

a) STRONG INVERSION

If the device is working for VGS>Vth, then it is said to be operating in strong

inversion [2.29]. Here, current is stable with respect to the changes in VDS, giving a

designer to achieve stable behavior of the circuit for a wide range of supply voltage. It

is the reason why majority of conventional analog devices operate in this region.

b) MODERATE INVERSION

Moderate inversion is the transition region between weak and strong

inversion, here both diffusion and drift currents are significant [2.1]. While strong

inversion region provides good frequency response, speed and smaller area, and weak

inversion has benefit of small supply voltage, moderate inversion region appears to

provide a good state of compromise between them, with finer results for power, speed

and area. However defining the circuit behavior in this region is very difficult for

designers, limiting their choice between either strong or weak inversion [2.9].


22

c) WEAK INVERSION

If the device is working for VGS<Vth, then it is operating in sub-threshold region.

The region where transition between weak and strong inversion takes place is called

moderate inversion. In terms of Inversion level if which is defined as if = ID/IS, where

ID is drain current and IS is given by

(2.8)

where Φt is thermal voltage, Cox is oxide capacitance, n is slope factor, μ is mobility

and W/L is aspect ratio, for if < 1 is weak inversion, for if > 100 is strong inversion

and between them is moderate inversion [2.9].

In the region of weak inversion, there exists a small value of current which

varies with VDS, this current is although assumed equal to zero in digital and

conventional analog circuits, but it proves to be of great importance when low supply

circuits are concerned. The drain current of the transistor working in weak inversion is

given by [2.30]

(2.9)

where, (2.10)

(2.11)

and n is given by

(2.12)


23

Using eq. 2.9, the transconductance in weak inversion can be defined as

(2.13)

This equation shows that the gm/ID is independent of W/L in weak inversion, because

ID is an exponential function of VGS in weak inversion.

The transconductance of a MOS in weak inversion can be expressed as

(2.14)

where

(2.15)

Except for the voltage divider factor 1/n the transconductance of MOS

operating is weak inversion is similar to a bipolar transistor [2.1]. It can be said that

the behavior of a MOS operating in weak inversion is similar to a bipolar transistor in

qualitative term. This region has maximum gm/ID, allowing the designer to create

circuits with minimum power [2.9]. The operation in weak inversion is a very strong

option to achieve low supply, low power application, but the circuit is very sensitive

to current mismatch between identically designed devices [2.32], because the drain

current ID in weak inversion is exponentially dependent on them, and also the devices

show difference between the sub threshold slope parameter [2.31].

2.4.2 MODE OF OPERATION

Characteristics of a circuit are defined by its biasing; the conventional MOS

Configurations are Common Source, Common Drain and Common Gate as shown in

Figure 2.3. But apart from this, the bulk or substrate terminal may also play a

significant role in controlling the characteristics of a MOS.


24

Figure 2.3 MOS configurations: a) common source, b) common drain

and c) common gate

a) GATE DRIVEN MOSFET

The conventional method of biasing a MOS is the configuration of Gate driven

MOS, in which either gate, drain or source terminal will be connected to input and

output and the remaining terminal is common, the input signal is usually administered

through the gate terminal. Among these common source is the most commonly used

configuration in electrical circuits. In earlier technology connecting terminal to the

bulk was not present, in new technologies where the bulk terminal is available; it is

connected to the most negative voltage while biasing the circuit. Commonly the

circuit operates in the strong inversion in this type of biasing. Although used

conventionally in most of the analog application, this biasing technique limits a

design to be operated for low values of supply voltage. Adding to this the technique is

susceptible to the problem related with body effect and Latchup. Special cautions

must be taken while designing and biasing the circuits to avoid these problems.


25

Figure 2.4 Cross sectional view of a) a pMOS with single well and n-well CMOS

technology with b) triple well process and c) buried n-well process

b) BULK DRIVEN MOSFET

In the conventional analog circuits the bulk terminal of a MOS is used just for

the biasing of the transistor, it is usually connected to the lowest supply voltage, and it

was not treated as a terminal which can modulate and control the channel of the

transistor. However the bulk (body or substrate) can play a role in controlling the

threshold voltage of the MOS [2.29], but this idea is utilized only in recent years


26

when circuits have emerged which have exploited the bulk terminal to control the

behavior of MOS while gate terminal is used only for polarization. Figure 2.4 shows a

cross sectional view of a standard n well CMOS transistor, the modern devices offer

access to the body terminal in a separate well or with buried deep n-well layer, in a

nMOS device, which was earlier available in only pMOS devices. The access to the

body terminal of a nMOS device comes at the expense of increased area, but this can

be limited by other large components like capacitors or inductors in the circuits and

also several nMOS device connected to the same potential can be grouped together to

reduce the area [2.34].

Body Effect

A block representation of comparison between nMOS in conventional biasing,

where it is connected with smallest supply voltage shown in Figure 2.5.a, and bulk

being biased using a small voltage shown in Figure 2.5.b. Using a small voltage, the

bulk-source junction can be forward biased, which will eventually decrease the

depletion region and increases the charge across channel, and hence decreases the

threshold voltage of the transistor.

Figure 2.5 NMOS Transistor a) with base connected to source so body-source not

forward biased, b) with body-source forward biased, hence decreased depletion and

increased channel charge.


27

Threshold voltage VT [2.33] of a MOS device for VSB > 0 is given by

(2.16)

where, Vth0 is threshold voltage for zero body source bias, γ is the body effect

coefficient, and Φ0 is given by

(2.17)

where ΦF is the Fermi-potential and ΔΦ is 6kT/q, i.e. about 150mV at room

temperature. According to eq. (2.16), threshold voltage increases with increasing

positive VSB (or negative VBS i.e. reversed biased base-source). For VSB > 0 (or positive

VBS i.e. forward biased base-source) the eq.(2.16) will become

(2.18)

It shows that threshold voltage Vth decreases with increasing the forward bias

VBS. This modulation of threshold voltage through VBS is called Body Effect, and

causes a problem in reverse biased bulk-source situation by increasing threshold

voltage. Although the bulk can be utilize to decrease the threshold voltage of a

transistor as well by applying a forward bias to the bulk-source, and hence making it a

suitable option for low voltage circuit applications.

Latch-up Phenomenon

The devices in standard CMOS technology are made of pnpn sandwich of

layers. In Figure 2.6.a, a schematic of CMOS device pair is shown; in Figure 2.6.b

cross section of the device is shown. As shown in Figure 2.6.b two pairs of bipolar

transistors, lateral npn and vertical pnp, are formed. These parasitic transistors can

create a positive feedback as shown in Figure 2.6.c. In normal circumstances all pn

junction of the structure are reverse biased, but if due to any circumstance the junction


28

Figure 2.6 a) CMOS device pair, b) Cross section demonstrating the parasitic bipolar

transaction, and c) Schematic of parasitic bipolar transistors creating a positive

feedback.

voltage of 0.7V is crossed and the transistor enter the active region, the circuits could

display large amount of positive feedback, and will start conducting heavily resulting

in a destructive breakdown phenomenon called Latchup [2.1].

However the activation probability is very small if the supply voltage is

smaller, thus for a supply voltage of 0.5V the phenomenon is almost impossible to

occur [2.33].

Transconductance [2.34] of a bulk driven transistor is

gmb = ηgm

2.5. Advantages and Disadvantages of Bulk Driven MOS

29

where η is given by

(2.19)

It shows that transconductance of bulk driven transistor is smaller than

transconductance of gate driven transistor. For VBS ≥ 2ΦF - 0.25γ2 ≈ 0.5V,

transconductance of bulk driven MOSFET can exceed the gate-driven MOSFET

transconductance [2.35].

2.5. ADVANTAGES AND DISADVANTAGES OF BULK DRIVEN

MOS

The technique of driving a MOS by bulk has both benefits and limitation

[2.32] - [2.37]. While there are significant advantages, the designs need to overcome

the limitations of this technique as well. In this section the advantages and

disadvantage of a bulk driven technique are summarized.

2.5.1 ADVANTAGES

Driving a transistor by bulk has various benefits compared to the transistor

driven by gate, like

This is an ideal choice for low supply and low power consuming devices.

The circuit with bulk driven transistor operating in weak inversion can

operate for supply as low as 0.5V.

In this process the signal with a wider range of voltage swing can be

operated.

Since the supply voltage could be low as 0.5V, by this fact the chances of

observing Latchup are sincerely reduced.

It shows better linearity in transconductance circuits and the

transconductance is stable for a wider frequency range.

Large input common mode signal can be processed in bulk driven circuits.


30

This technique is most suitable for rail-to-rail operation.

Signal processing is independent of threshold voltage restrictions.

For the circuit operating in weak inversion gm/ID is maximum, which

means smaller power consumption by the circuit.

A theoretical possibility of bulk driven transistor’s transconductance

becoming higher than that of a gate driven transistor also exists.

2.5.2 DISADVANTAGES

The disadvantages related with a bulk driven circuit, which need to be

overcome can be summarized as

The value of transconductance is 4-5 times smaller in a bulk driven MOS

compared to a gate driven MOS.

The smaller transconductance is the reason for smaller voltage gain of a

bulk driven transistor.

The bulk driven transistor have higher noise than gate driven transistor,

most of this noise is thermal noise. The bulk sheet resistance of a bulk

driven MOS contributes to the thermal noise. And the gain factor referring

the channel noise current to input increases the noise in the bulk driven

transistor in comparison to the gate driven transistors.

The frequency response of a bulk driven MOS is bad compared with a gate

driven MOS because of the input capacitance in bulk driven MOS.

The application of bulk driven MOS technique is technology limited.

There exists a probability that source and substrate may form a forward

bias, resulting in a Latchup.

The mismatch of transistor is another serious issue with bulk driven

transistor operating in weak inversion.

As it can be seen in Figure 2.4, relatively larger surface area is required to

implement bulk driven circuits on a chip. However this area can be

compensated and minimized with the choice better designing.

2.6 Conclusions

31

2.6 CONCLUSIONS

Various low voltage circuit techniques are discussed in this chapter. Options of

technology modification and circuit design modification which can operate for low

supply voltage and power are discussed. All these options have their pros and cons,

technology modification appears promising but its primary and biggest demerit is that

the method is not cost effective. Meanwhile among the circuit modifications are

various techniques with which the supply voltage demand and power consumption

may be decreased, however most of them come with complex circuit modification to

overcome the problems like linearity, frequency response bandwidth, noise, which

comes with low supply. Compared to others, bulk driven MOS technique does not

increase the complexity of the circuit an offers benefits of stable transconductance,

wider voltage swing, linearity, but the circuit must be appropriately designed to

overcome the challenge of low transconductance, low gain, reduced bandwidth,

higher noise and mismatches. With the choice of suitable circuit and parameters, the

bulk driven MOS may play an effective role in lowering the supply voltage of a

circuit. In the end it is the specifications of the filter or circuits, design requirements,

available resources and effective cost of implementation, that eventually decides

which of these techniques may be implemented to obtain a low supply low power

circuit. In the following chapter circuit implementing bulk driven technique to obtain

a transconductor operating for 0.5V supply voltage is presented.

2.7 REFERENCES

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no.1, pp.132-143, Jan. 2005.

[2.2] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and Design of

Analog Integrated Circuits”, 4th edition, John Wiley and Sons, New York,

2001.


32

[2.3] P. I. Mak and R.P. Martins, “High-Mixed-Voltage Analog and RF Circuit

Techniques for Nanoscale CMOS,” Analog Circuits and Signal Processing,

Springer, 2012.

[2.4] S. W. Sun, P. G. Y. Tsui, B. M. Somero, J. Klein, F. Pintchovski, J. R.

Yeargain, B. Pappert, R. Bertram, "A fully complementary BiCMOS

technology for sub-half-micrometer microprocessor applications," IEEE

Transactions on Electron Devices, vol.39, no.12, pp.2733- 739, Dec 1992

[2.5] S. S. Bazarjani, W. M. Snelgrove, "Low voltage SC circuit design with low -

Vt MOSFETs," IEEE International Symposium on Circuits and Systems,

ISCAS '95, vol.2, pp.1021-1024, 1995.

[2.6] V. Srinivasan, D. W. Graham, P. Hasler, "Floating-gates transistors for

precision analog circuit design: an overview," 48th Midwest Symposium on

Circuits and Systems, vol. 1, pp.71-74, 2005.

[2.7] E. O. R. Villegas, A. Rueda, A. Yufera, “ Low Voltage Analog Filters using

Floating gate MOSFETs” IEEE Solid State Circuits Conference, pp 29-32,

2000.

[2.8] S. Sharma, S. S. Rajput, S. S. Jamuar, “Floating-gate MOS Structure and

Applications” IETE Tech Rev, vol. 25, pp. 338-345 2008.

[2.9] S. Yan and E. S. Sinencio, “Low voltage analog circuit design techniques: A

Tutorial”, IEICE Trans. Analog Integrated Circuits and Systems, Vol. EOO-A

No.2 February 2000.

[2.10] S. Vlassis and S. Siskos, “Differential-voltage attenuator based on Floating-

gate MOS transistors and its applications”, IEEE transactions on Circuits and

Systems – I: Fundamental Theory and Applications, Vol.48, No. 11, pp. 1372-

1378, Nov. 2001.

[2.11] Y. Joly, L. Lopez, J.-M. Portal, H. Aziza, P, Masson, J. Ogier, Y. Bert, F.

Julien, P. Fornara, "Octagonal MOSFET: Reliable device for low power

analog applications," Solid-State Device Research Conference (ESSDERC),

2011 Proceedings of the European, pp.295-298, Sept. 2011.

[2.12] Y. Osaki, T. Hirose, N. Kuroki, M. Numa, "A level shifter circuit design by

using input/output voltage monitoring technique for ultra-low voltage digital

2.7 References

33

CMOS LSIs," IEEE 9th International New Circuits and Systems Conference

(NEWCAS), pp. 201-204, June 2011.

[2.13] S. L tkemeier, U. Ruckert, "A Sub threshold to Above-Threshold Level

Shifter Comprising a Wilson Current Mirror," IEEE Transactions on Circuits

and Systems II: Express Briefs, vol.57, no.9, pp.721-724, Sept. 2010.

[2.14] H. Shao and C. Y. Tsui, "A robust, input voltage adaptive and low energy

consumption level converter for sub-threshold logic," 33rd European Solid

State Circuits Conference, ESSCIRC, pp.312-315, Sept. 2007.

[2.15] F. Ishihara, F. Sheikh, B. Nikolic, "Level conversion for dual-supply systems

[low power logic IC design]," Proceedings of the 2003 International

Symposium on Low Power Electronics and Design, ISLPED '03, pp.164-167,

Aug. 2003.

[2.16] J. M. Baek, J. H. Chun, K. W. Kwon, "A Power-Efficient Voltage

Upconverter for Embedded EEPROM Application," IEEE Transactions on

Circuits and Systems II: Express Briefs, vol. 57, no. 6, pp. 435-439, June

2010.

[2.17] S. C. Tan, X. W. Sun, "Low power CMOS level shifters by bootstrapping

technique," Electronics Letters, vol. 38, no. 16, pp. 876-878, Aug 2002.

[2.18] A. U. Diril, Y. S. Dhillon, A. Chatterjee, A. D. Singh, "Level-shifter free

design of low power dual supply voltage CMOS circuits using dual threshold

voltages," IEEE Transactions on Very Large Scale Integration (VLSI)

Systems, vol. 13, no. 9, pp. 1103-1107, Sept. 2005.

[2.19] M. Ashouei, H. Luijmes, J. Stuijt, J. Huisken, "Novel wide voltage range level

shifter for near-threshold designs," 17th IEEE International Conference on

Electronics, Circuits, and Systems (ICECS), pp. 285-288, Dec. 2010.

[2.20] J. Crols, M. Steyaert, "Switched-opamp: an approach to realize full CMOS

switched-capacitor circuits at very low power supply voltages," IEEE Journal

of Solid-State Circuits, vol. 29, no. 8, pp. 936-942, Aug 1994.

[2.21] A. Baschirotto, R. Castello, "A 1 V 1.8 MHz CMOS switched-opamp SC filter

with rail-to-rail output swing," . 43rd IEEE International Solid-State Circuits

Conference, ISSCC Digest of Technical Papers, pp. 58-59, Feb. 1997.


34

[2.22] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, W. Sansen, "A 900 mV

40 μW switched opamp ΣΔ modulator with 77 dB dynamic range," IEEE

International Solid-State Circuits Conference, Digest of Technical Papers, pp.

68-69, Feb. 1998

[2.23] Α. Baschirotto, "A low-voltage sample-and-hold circuit in standard CMOS

technology operating at 40 ms/s," IEEE Transactions on Circuits and Systems

II: Analog and Digital Signal Processing, vol. 48, no. 4, pp. 394-399, Apr

2001.

[2.24] J N Babnezhad, “A rail-to-rail CMOS opamp,” IEEE Journal of Solid-State

Circuits, Vol. 23, pp. 1414–1417, Dec. 1988.

[2.25] W. R. White, “A high bandwidth constant gm and slew rate rail-to-rail CMOS

input circuit and its application to analog cells for low voltage VLSI systems,”

IEEE Journal of Solid State Circuits, Vol. 32, no. 5, pp. 701-712, May 1997.

[2.26] J. M. Carrillo, J. F. D. Carrillo, G. Torelli, and J. L. Ausín, “Constant gm

Constant slew rate High Bandwidth Low Voltage Rail-to Rail CMOS Input

Stage for VLSI Cell Libraries,” IEEE Journal of Solid State Circuits, Vol. 38,

no. 8, pp. 1364-1372, Aug.2003.

[2.27] S. Pemici, G. Nicollini, and R. Castello, “A CMOS low distortion fully

differential power amplifier with double nested miller compensation,” IEEE

Journal of Solid State Circuits, Vol. 28, no. 7 pp. 758-763, July 1993.

[2.28] R. G. H. Eschauzier, L. P. T. Kerklaan, and J. H. Huijsing, “A 100 MHz

100dB Operational Amplifier with multipath nested Miller Compensation

Structure,” IEEE Journal of Solid State Circuits, Vol. 27, no. 12 pp. 1709-

1717, Dec 1992.

[2.29] R. L. Geiger, P. E. Allen, N. R. Strader, “VLSI Design Techniques for Analog

and Digital Circuits,” McGraw-Hill Publishing Company, 1990.

[2.30] Y. P. Tsividis, “Operation and Modeling of the MOS transistor,” McGraw-Hill

International Edition, 1988.

[2.31] R. J. Baker, H. W. Li and D. E. Boyce, “CMOS Circuit Design, Layout, and

Simulation”, IEEE Press Series on Microelectronic Systems.

2.7 References

35

[2.32] M. J. Chen; J. S. Ho; T. H. Huang, "Dependence of current match on back-

gate bias in weakly inverted MOS transistors and its modeling," IEEE Journal

of Solid-State Circuits, vol. 31, no. 2, pp. 259-262, Feb 1996.

[2.33] S. Chatterjee, K. P. Pun, N. Stanic, Y. Tsividis and P. Kinget, “Analog circuit

Design Techniques at 0.5V,” New York: Springer, ISBN : 0387699538, 2007.

[2.34] E.S. Sinencio, “Bulk Driven Transistors”, ELEN-607 Course notes, Texas

A&M University, 2003.

[2.35] B. J. Blalock, P. E. Allen and G. A. R. Mora, "Designing 1-V opamps using

standard digital CMOS technology," IEEE Transactions on Circuits and

Systems II: Analog and Digital Signal Processing, vol. 45, no. 7, pp. 769-780,

Jul 1998.

[2.36] A. Khateb, V. Musil, R. Prokop, “Rail-to-rail Bulk Driven Amplifier”,

Electronics, 2005.

[2.37] F. Khateb, D. Biolek, N. Khatib and J. Vavra, "Utilizing the Bulk-driven

technique in analog circuit design," IEEE 13th International Symposium on

Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 16-

19, April 2010.


36

37

3. CHAPTER 03 A 0.5V OPERATIONAL TRANSCONDUCTOR AMPLIFIER (OTA)

A 0.5V

OPERATIONAL

TRANSCONDUCTOR

AMPLIFIER (OTA)

03

3.1 INTRODUCTION

The bulk driven technique as discussed in the previous chapter has advantage

of low supply, stable and linear transconductance, large voltage swings while at the

same time it has disadvantages like low transconductance, smaller gain, higher noise

and limited frequency response. An appropriate choice of circuit design and elements

may reduce the undesired consequences of demerits related with bulk driven circuits.

In this chapter Nauta’s transconductor amplifier and various techniques to improve its

performance are discussed. The majority of circuits driven by substrate consist of

transconductance amplifier where transistors are driven by bulk in the differential pair

input stage and gate is used for the biasing of the circuit [3.1]. A new technique of

utilizing bulk terminal of MOS to lower the supply voltage requirement is employed

in this research work. Nauta’s Transconductor is used as the basic circuit in this

thesis, because of the properties like absence of internal nodes and use of negative

resistance, it helps to overcome the problems with bandwidth, and smaller gain of

bulk driven circuits. The final target is to design a low voltage transconductor which

will be used in filtering applications.

Chapter 03 A 0.5V Operational Transconductor Amplifier (OTA)

38

Figure 3.1 Nauta’s Transconductor

3.2 NAUTA’S TRANSCONDUCTOR

Nauta’s Transconductor [3.2] is a very robust design and was initially

designed for high frequency application. The absence of internal nodes has ensured

that there will be no parasitic poles, which influence the transfer function of the

integrator, and loading the transconductor with a negative resistance increases its dc

gain. Theoretically an integrator with infinite dc gain, infinite bandwidth, eventually

an infinite quality factor is possible with the use of these two techniques.

The transconductor shown in Figure 3.1 is based on six CMOS inverters in

differential configuration. Inv1 and Inv2 form the main differential transconductor

driven by a differential input voltage VID, and Inv3-Inv6 control the common-mode

level of the output voltage. The transconductor is tuned by supply voltage VDD. Even

if the inverters are nonlinear, the differential transconductance of this transconductor

is linear. Inv5 and Inv6 virtually load node Vo1 with resistance 1/(gm5+gm6), and Inv3

and Inv4 load node V02 with resistance 1/(gm3+gm4), with common mode output

voltage. Similarly in differential mode Inv5 and Inv6 load Vo1 with 1/(gm5-gm6) and

Inv3 and Inv4 load Vo2 with 1/(gm3-gm4) virtual resistance. Thus for equal gm of all

3.3 Techniques to Improve Nauta’s Transconductor

39

inverters, Inv3 and Inv4 form a low-ohmic node for common signal and high ohmic

node for differential signal, leading to a controlled common-mode output voltage. By

choosing gm3>gm4 and gm5=gm4 and gm6=gm3, Inv1 and Inv2 are implemented with

a negative resistance without adding any extra internal node, this technique increases

the dc gain of transconductor. To achieve a fine tuning, Inv4 and Inv5 can be

connected to a separate supply VDD’. This is a major drawback with Nauta’s

Transconductor, to attain frequency and Q tuning, two independent supply voltages are

required. Hence to achieve a good PSRR, the filter must be accompanied with two

independent on-chip supply voltages. This requirement of tunable power supply

restricts the application of Nauta’s Transconductor for low voltage and low power

consuming circuits. Also in this transconductor the dc gain is subjected to the error

related mismatch, which can be kept small by proper layout techniques, like choosing

large area transistors and keeping length of nMOS and pMOS equal.

3.3 TECHNIQUES TO IMPROVE NAUTA’S TRANSCONDUCTOR

Nauta’s transconductor inspite of being a very robust model capable of

operating in high frequencies and with a wider bandwidth suffer from the

disadvantage of high power supply requirement and need of special supply voltage

buffer circuit to overcome its poor CMRR and PSRR. Also it has issue related with

the matching of nMOS and pMOS transistors. Alternative circuits and methods to

overcome and improve Nauta’s transconductor performance are analyzed.

3.3.1 FLOATING GATE METHOD

In this method [3.3] the MOS transistors in the inverter used in Nauta’s

Transconductor are replaced with Multiple Input Floating Gate Transistors (MIFGTs).

An n-MIFGT is a floating gate MOS with ‘n’ input, where each input is connected to

the floating gate by a polyII-polyI capacitor. The biasing voltage Vbiasn and Vbiasp

added to the quiescent gate source voltage of the transistor gates, allow the rail-to-rail


40

operation of the transistor. The differential output current in Nauta’s Transconductor

may be defined as

(3.1)

and the differential input current in the transconductor with MIFGT is

(3.2)

Comparing the equation it can be concluded that the transconductance is

controlled by the bias voltage 2XVbias, where X is a capacitance related with the

channel type of MIFGT. The multiple input floating gate is biased to a voltage higher

than the threshold voltage of transistor, which keeps the transistor in saturation for

any voltage within supply rails. The biasing voltages Vbiasn and Vbiasp are use to tune

the transconductor. This method lowers the supply voltage requirement, allows rail to

rail input voltage swing and allows tuning of common mode voltage and output

resistance by bias voltage giving a control over frequency and Q tuning of the

transconductor. Although because of capacitive dividers in MIFGT and parasitic

capacitance associated with polyII-polyI, bandwidth of the transconductor is reduced.

3.3.2 INPUT COMMON MODE REJECTION METHOD

In this method a ‘balanced circuit’, shown in Figure 3.2 is proposed to perform

V-I conversion [3.4]. The circuit solves the linearity, power supply rejection,

matching and high supply requirement problems of Nauta’s OTA. In this circuit all n-

transistors and p-transistors are matched respectively to eliminate the parasitic poles.

The differential output current of this circuit is given as


41

(3.3)

where Vid is differential signal and VC is common mode voltage, showing that gm and

hence frequency is tunable with common mode voltage VC. The common mode output

current IOC=βnVid2/4 is negligible for small values of Vid

Four differential amplifiers of the transconductor DA3-DA6, control the

common mode output voltage. The transconductance of this OTA is tunable by means

of bias voltage Vf and Vq. Like Nauta this transconductor also uses the negative

resistance to improve its DC gain. By biasing the differential amplifier with two

different voltages, the poles are shifted to higher frequencies and hence the cutoff

frequency. The gate of transistors in this OTA must be connected to positive and

negative supply for pMOS and nMOS respectively to avoid Latchup.

3.3.3 PSEUDO DIFFERENTIAL AMPLIFIER WITH CMFB

Another method with a CMOS inverter based class AB pseudo differential

amplifier (PDA) using a common mode feedback (CMFB) consisting of a current

mirror and transimpedance amplifier is employed to lower the supply voltage [3.5].

Figure 3.2 Balanced Circuit for Linear Conversion


42

Pseudo differential amplifier unlike fully differential amplifier (based on a differential

pair with a tail current) is based on two independent inverters without tail current

source. However to suppress the common mode signal and common mode voltage at

high impedance mode, pseudo differential amplifier require extra common mode

feedback. In this circuit, the common mode amplifier amplifies the common mode

output signal and negative feedback it to the bulk terminal of the transistor of pseudo

differential OTA, so that the common mode output voltage is suppressed, on the other

hand it does not respond to the differential mode signal and hence it remains constant.

In the common mode amplifier voltage mode signal is converted to current mode

using the matching resistors, these current mode signals are further added or

subtracted utilizing their phase, and hence amplified or left unchanged by the

transimpedance amplifier for the differential and common mode signals respectively.

This design promises better CMRR and low voltage operation which were major

setbacks of Nauta’s transconductor, but unlike Nauta’s circuit this circuit is not

independently tunable.

3.3.4 INVERTER BASED FULLY DIFFERENTIAL OTA

An alternative OTA design [3.6] based on inverters shown in Figure 3.3.a, has

lower common mode transconductance gain and better linearity than Nauta’s OTA

Figure 3.3.b. By providing a shortcut between Inv3 and Inv7, this OTA achieves

better frequency performance and better DC output common mode stability than

Nauta’s OTA. This shorted node provides a DC common mode voltage of VDD/2 at

both output nodes, hence this circuit does not require any additional circuitry to

control DC output voltage as was required in Nauta’s OTA.

The current-to-voltage transfer function of the OTA in Figure 3.3.a is given as

(3.4)

(3.5)


43

From eq.(3.5) it can be concluded that differential mode transconductance GMD = gm/2

and common mode transconductance GCM = 2gd, where gd is output transconductance

of inverters.

Similarly, the current-to-voltage transfer function for Nauta’s OTA in Figure 3.3.b is

(3.6)

where Z’=Z/(Z+3gd). From eq.(3.6) it follows that GMD=gm/2 and

GCM=gm/(1+2gmZ’).

Figure 3.3 a) Inverter based fully differential transconductor and

b) Nauta’s Transconductor


44

For capacitive load GCM=gm for ω→∞, and GCM=3gd/2 for ω→0, showing that

in Nauta’s circuit, transconductance depends on the frequency and increases rapidly

with it, also common mode transconductance is twice that differential

transconductance. It is visible that this improved OTA is better than Nauta’s in terms

of linearity, stability, it provides lower CMRR, PSRR, and higher output swing.

However this circuit is employing larger number of inverter compared to Nauta’s, its

current consumption is large, and it is working in saturation region for a supply of

2.5V and hence it is not suitable for low voltage supply application.

3.3.5 BULK -CONTROLLED TRANSCONDUCTOR & CONTROL CIRCUIT

In this method a Nauta’s Transconductor, whose transconductance is

controlled by a tuning current added to its bulk terminal is demonstrated [3.7]. As

shown in Figure 3.4 the transconductor is improved by adding the bulk terminal with

a tuning circuit. The differential input signal VDD±VID is given to Inv1 and Inv2,

through the gate terminal of the MOS. This design operates in weak inversion with a

supply voltage VDD of 0.5V.

The tuning or control circuit of transconductor shown in Figure 3.5.b, is based

on master-slave approach of CMOS inverter operating in weak inversion. The

Inverters in the transconductor serve as a slave device while the control circuit is the

master. An input CM equal to VDD/2 and input voltage Vin are applied at the common

gate input of the inverters. The bulk voltages Vfp and Vfn are adjusted in order to bias

the inverter with the desired quiescent current. The aspect ratio of the master device is

m times smaller than the slave devices, and hence the quiescent current of the slave

device (mIT) is m times larger than those of the master devices (IT). The control circuit

uses two negative feedback loops; p-FB and n-FB loop. Due to these feedback loops,

the differential amplifiers (amp) shown in Figure 3.5.a modify the feedback voltages

Vfp, Vfn, and ensue that ID,p.m and ID,n.m will stay equal to IT i.e tuning current and drain

voltages of transistors Mp.m and Mn.m will be equal to VDD/2.

In the slave inverter, the value of quiescent current and the output common

mode voltage are maintained at mIT and VDD/2 respectively, by the feedback voltages

Vf.p and Vf.n applied to the bulk terminals of Mp.s and Mn.s transistor respectively. By


45

this method eventually the transconductance gm.p.s and gm.n.s of transistors Mp.s and Mn.s

respectively, are controlled by tuning current IT. The common mode voltage is kept

constant at VDD/2 by the feedback loop. Accordingly the transconductance of the slave

inverter, assuming that the circuit works in weak inversion, is given by

(3.7)

where n is the slope factor, m is the scaling factor and Vt = kT/q is the thermal

voltage. The differential amplifier in Figure 3.5.a is formed of pMOS devices M1, M2

and M3, where M3 is biased by current IB. The three transistors act as a current mirror

with gate voltage equal to VDD/2 and quiescent drain current, IB.

The output current of the transconductor in Figure 3.4 is

(3.8)

Figure 3.4 Bulk Controlled Nauta’s Transconductor


46

Figure 3.5 a) Amplifier used in the Control Circuit and

b) Control Circuit used to control the tuning Current of Nauta’s Transconductor.

The transconductor circuit shown in Figure 3.4 has tuning circuits namely

‘Control Circuit 1’ and ‘Control Circuit 2’, which controls the differential

transconductor through Inv1,2; differential output load through Inv3,6; and common

mode output load through Inv4,5. Using different tuning current IT2 for Inv4,5 allows

independent frequency and Q tuning in filter applications without affecting the output

CM voltage.

The effectiveness of the proposed technique was simulated using a triple well

0.13 μm CMOS process with VDD=0.5V. The transistor’s aspect ratio were

(W/L)p.s1,2=100/0.5 μm, (W/L)n.s.1,2=50/0.5 μm for Inv1,2, (W/L)p.s.3–6=25/0.5 μm,


47

(W/L)n.s.3–6=12.5/0.5 μm for Inv3-6 and (W/L)1–3=10/0.5 μm, (W/L)4,5=30/0.5 μm for

the differential amplifier. The scale factor was m = 4 and the bias current of amp was

IB=1μA. In Figure 3.6 variation of transconductance with respect to the tuning current

is shown. In Table 3.1 a comparative analysis of all the discussed techniques is

presented.

This modified bulk driven transconductor operates for the minimum supply

voltage compared with other discussed designs. This design has highest value of

transconductance and has widest gm/IDD ratio compared with other designs. Gain

bandwidth (GBW) of this OTA is although not largest, but is appreciable considering

the fact the design operates in weak inversion for a supply voltage of just 0.5V. This

smaller GBW can be considered as a price paid for the advantage of small supply

voltage. Common Mode Rejection Ratio (CMRR) and Power Supply Rejection Ratio

(PSRR) of this OTA are also discernible. In the matter of linearity the behavior of this

OTA is comparable with other work, as displayed by the Total Harmonic Distortion

(THD) results. The brightest feature of this OTA is its small supply voltage

requirement and a simple circuit.

Figure 3.6 Input Transconductance gm and GBW as function of IT1


48

Table 3.1 Performance Comparison of OTAs

Unit [3.3] [3.5] [3.6] [3.7]

Process 0.8 μm 0.18 μm 0.18 μm 0.13μm

VDD (V) 1.2 1 2.5 0.5

gm (μA/V) 110 -- 108.4 797

IDD (μA)

-- 96 320 120

@IT1=40μΑ

Tuning

VFG

[1.2-1.05]V

--

--

VDD

[2-2.5]V

IT1

[10-40]μA

Δgm (μA/V) 110-165 -- 72-108 235-797

Ao (dB) -- 36 31.3 37

GBW (MHz) 450 800 3560 530

CMRR (dB)

-- 51 31 31

At each output node

PSRR (dB) -- -- 37.45 90

THD

@ Vpp in (V)

@RL

(dB)

-46

1V, 10.7MHz

1KΩ

--

--

-46.6

1V

20KΩ

-40

0.1V, 100MHz

1.25KΩ

3.4 Choice of Nauta’s Transconductor for Bulk Controlled OTA

49

3.4 CHOICE OF NAUTA’S TRANSCONDUCTOR FOR BULK

CONTROLLED OTA

The Bulk Driven circuits as discussed in the previous chapter have their own

limitations in spite of their ability to work in low supply with good linearity and stable

transconductance over a range of tuning voltage/current. Nauta’s Transconductor in

spite of being initially designed for high frequency application can be used for low

frequency filters with high order because of the absence of internal nodes. Nauta’s

Transconductor has a restriction imposed by its tuning power supply, which restricts it

to be implemented for low supply voltage applications. Techniques like input

common mode voltage and Floating gate MOS (FGMOS) have been applied to

overcome this limitation by tuning circuit.

In this research work Bulk Driven MOS technique and Nauta’s

Transconductor are used such that they complement each other and help to beat the

other’s disadvantage. The transconductor used in this research work employs a

Nauta’s Transconductor, whose transconductance is controlled by a tuning current

added to its bulk terminal. By this technique the power and supply requirements of the

transconductor are reduced. At the same time since Nauta’s transconductor has no

internal node, the filter is expected to overcome the bandwidth limitations posed by

bulk driven circuits. Negative resistance in this transconductor will help to increase

the gain of the transconductor and the uses of differential inputs are expected to

improve linearity and to reduce noise. Because of the output resistance being

compensated the distortion due to channel-length modulation is reduced in this

transconductor.

3.5 CONCLUSION

In this chapter Nauta’s Transconductor, its circuit design, advantages and

limitations were discussed. Nauta’s OTA is meant for high frequency applications,

utilizing features like negative resistance and absence of internal node. However it is


50

not very good in terms of PSRR. Various methods to improve the performance and

overcome the limitations of this transconductor are discussed. The transconductor is

further modified in order to control it through the bulk terminal of the transistors use

in it, which are added with a bulk controlled tuning circuit. The tuning circuit has

ensured the application of this transconductor for the low voltage circuits. This OTA

operates in weak inversion for a supply voltage of 0.5V for an appreciable tuning

range. In the next chapters the aspect ratios of this transconductor will be further

modified to improve its performance for application in more complex and higher

order filter circuits.

3.6 REFERENCES

[3.1] S. Chatterjee, Y. Tsividis, P. Kinget, "0.5-V analog circuit techniques and

their application in OTA and filter design," IEEE Journal of Solid-State

Circuits, vol. 40, no. 12, pp. 2373-2387, Dec. 2005


frequencies," IEEE Journal of Solid-State Circuits, vol. 27, no. 2, pp. 142-153,

Feb 1992.

[3.3] F. Munoz, A. Torralba, R. G. Carvajal, J. Tombs, J. R. Angulo, "Floating-gate

based tunable CMOS low-voltage linear transconductor and its application to

HF gm-C filter design," Proceedings of The 2000 IEEE International

Symposium on Circuits and Systems, ISCAS Geneva., vol. 4, pp. 465-468

2000.

[3.4] T. S. Lee, H. Y. Pan, "A low-voltage CMOS transconductor for VHF

continuous-time filters," Proceedings of IEEE International Symposium on

Circuits and Systems, ISCAS '97, vol. 1, pp. 213-216 Jun 1997.

[3.5] A. Suadet, V. Kasemsuwan, "A CMOS inverter-based class-AB pseudo

differential amplifier for HF applications," IEEE International Conference of

Electron Devices and Solid-State Circuits (EDSSC), pp. 1-4, Dec. 2010.

[3.6] H. Barthelemy, S. Meilere, J.Gaubert, N. Dahaese, and S. Bourdel, “OTA

based on CMOS inverters and application in the design of tunable bandpass

3.6 References

51

filter,” Analog Integrated Circuits and Signal Processing, vol. 57, no. 3, pp.

169-178, Dec 2008.

[3.7] S. Vlassis, “0.5 V CMOS inverter-based tunable transconductor,” Analog

Integrated Circuits and Signal Processing, Vol. 72,Issue 1,pp 289-292, July

2012.

[3.8] P. Andreani, S. Mattisson, "On the use of Nauta's transconductor in low-

frequency CMOS gm-C bandpass filters," IEEE Journal of Solid-State

Circuits, vol. 37, no. 2, pp. 114-124, Feb 2002.

http://link.springer.com/journal/10470


http://link.springer.com/journal/10470/72/1/page/1


52

53

4. CHAPTER 04 DESIGN OF A 0.5V LEAPFROG FILTER

DESIGN OF A 0.5V

LEAPFROG FILTER

04

4.1 INTRODUCTION

In this chapter, the focus will be placed on the discussion of low supply

voltage analog filter. The techniques and designs employed to design the filter with

voltage supply as low as 0.5V using an Operational Transconductance Amplifier

(OTA) will be discussed. An OTA is a voltage controlled current source (VCCS)

where differential input voltage produces an output current [4.1]. Similar to an

opamp, it has both inverting and non-inverting inputs, power supply lines and output,

although unlike an Operational Amplifier, it has additional biasing inputs as well.

Like an opamp, an OTA has a high impedance differential input stage and it may be

used with negative feedback, however unlike an opamp, the output is voltage not

current. Because of the resistance at its output controls an OTA is usually used ‘open

loop’ without negative feedback in linear applications.

Figure 4.1 The Leapfrog Topology

Chapter 04 Design of A 0.5V Leapfrog Filter

54

The OTAs have been used in various applications of analog signal processing

like filters and oscillators. Some simple applications like Voltage Amplification,

Voltage Variable Resistor (VVR), Voltage Summation, Integration, Gyrator

Realization, and Current Conveyer are summarized in Appendix A. OTAs have

higher bandwidth than opamp, which facilitate their application in the design of active

filters operating at higher frequencies. At the same time OTAs have simpler circuitry

and the gm of an OTA is tunable. Unlike an opamp, and OTA does not require

frequency compensation for its stability and therefore it does not include low

frequency poles, and they have wide dynamic range. However the OTA suffer from

the drawback of limited range of input voltage for linear operations. The linear

performance of an OTA is worsened due to the restriction for operation in small

signal conditions. An active RC filter cannot work for higher frequencies because of

frequency limitations of an opamp, an OTA or gmC based continuous filter is a

solution to it.

4.2 THE LEAPFROG TECHNIQUE

In this chapter a 3rd

order filter is designed based on the leapfrog topology.

The leapfrog topology is useful in the functional simulation of an LC ladder. The

circuit structure [4.1] as shown in Figure 4.1 resembles a children’s game and hence

was named ‘Leapfrog’ after that.

The 3rd

order Low pass passive filter is shown in Figure 4.2.a, where all the

nodes, voltage and currents are suitably named. Applying Kirchhoff’s law to the

node1, we obtain,

(4.1)

(4.2)

4.2 The Leapfrog Technique

55

Figure 4.2 a) Third Order Passive Leapfrog b) Lossy Integrator,

c) Lossless Integrator

Equation 4.2 suggests that V1 may be obtained at the output of an inverting lossy

integrator, as shown in Figure 4.2.b. Similarly I2 may be written as

(4.3)

In the same manner a voltage analogous to I2 can be obtained at the output of the

inverting lossless integrator, shown in Figure 4.2.c. The voltage across C3 can be

written as

(4.4)

From equation 4.4 it can be again visualized that V3 can also be realized with an

inverting lossy integrator.

An active block diagram of the 3rd

order filter is shown in Figure 4.3.a. The

overall filter is made by replacing one by one the block with the integrators and other

corresponding components; the complete filter is shown in Figure 4.3.b. This circuit

uses resistor which does not allow independent tunability of the filter. The integrators


56

Figure 4.3 a) Block Diagram of the Active Ladder Simulating the 3rd

order filter

b) Leapfrog topology for the same filter using an opamp

Figure 4.4 Leapfrog topology for the 3rd

order filter using an OTA

4.3 Filter Design Example

57

using opamp in this circuit may be replaced by the gmC lossy and lossless integrators

and then the filter will take form of the active gmC filter shown in Figure 4.4.

4.3 FILTER DESIGN EXAMPLE

The filter design in this chapter uses a Modified Nauta’s Transconductor. The

Nauta’s Transconductor as described in the previous chapter, is very robust building

block which was initially designed to be implemented for high frequency filter,

because it did not had internal nodes [4.2]. The filter is modified to overcome the

limitation associated with use of low power supply and bad common mode input

[4.3]. The transconductance of OTA is controlled with a tuning circuit IT which feeds

the voltage Vfp and Vfn to the bulk of the pMOS and nMOS transistors respectively, in

the inverters used in OTA. The OTA operates in weak inversion with a supply of

0.5V only. To realize a fully differential operation and to facilitate its employment in

the designed 3rd

order filter, this OTA is equipped with double differential inputs, as

shown in Figure 4.5.

Figure 4.5 The Double Input differential OTA


58

To reduce the current consumption and chip area of OTA, only one control

circuit is used to tune the gm of OTA. Although the use of two different tuning circuits

in this OTA would have meant a better, independent control over frequency and Q

tuning, but in order to make a tradeoff between the current consumption and linearity,

the OTA used in this filter employs only one control circuit. The tuning circuit, shown

in Figure 4.6.b, is based on master-slave technique, with transistor operating in weak

inversion. The control circuit used two negative feedback loop n-FB and p-FB, with

which the differential amplifiers (amp) modify the feedback voltage Vfp and Vfn and

ensure that both Drain currents, IDpm and IDnm will be equal to IT and drain voltages of

Mp.m and Mn.m equal to VDD/2, and the stability of feedback loop is ensured by

capacitors Cn and Cp.

The transconductance of the slave inverter, assuming that the circuit works in

weak inversion, is given by

(4.5)

Where ‘n’ is the slope factor, ‘m’ is the scaling factor and Vt = kT/q is the

thermal voltage. It is expected that the OTA will have linear transconductance gm

which will depend linearly on the tuning current IT. The differential amplifier in

Figure 4.6.a is formed of PMOS devices M1, M2 and M3, where M3 is biased by

current IB. The three transistors act as a current mirror with gate voltage equal to

VDD/2 and quiescent drain current, IB.

The output current of the transconductor in Figure 4.5 is

(4.6)


59

Figure 4.6 a) The Circuit of Differential Amplifier and

b) Schematic diagram of the control circuit

The topology of the LC ladder passive prototype filter is shown in Figure 4.7.a. The

third order Butterworth filter function is given as

(4.7)

The function for Figure 4.7.a is normalized with values C1p=C3p=1F, L2p=2H

and RS=RL=1Ω. The passive 3rd

order low pass filter with normalized values and its

signal flow graph are shown in Figure 4.8 The active gmC technique is employed

using leapfrog technique in the filter, as shown in Figure 4.7.b. The modified double

differential OTA form the core of this filter. It has ability to operate with very low

power supply of 0.5V and its transconductance can be controlled linearly with tuning

current IT1.


60

Figure 4.7 Filter Topology a) passive prototype and b) active implementation

Figure 4.8 a) Passive 3rd

order filter and b) its Signal Flow Graph.

4.4 Simulation Results

61

4.4 SIMULATION RESULTS

The effectiveness of the proposed filter technique was simulated using a triple

well 0.13 μm CMOS process with VDD=0.5V [4.4]. The transistors used in the

simulations have a normal threshold voltage. The third order Butterworth filter in

Figure 4.7.b has a cutoff frequency equal to 1MHz for IT1=10μΑ. The capacitors in the

filter have values C1=C3=74.31pF and C2=148.63pF and the capacitors in the control

circuit Cp and Cn are both 1pF.

The transistor’s aspect ratio were (W/L)p.s1-4 = 100/0.5 μm, (W/L)n.s.1-4 = 50/0.5

μm for Inv1-4, (W/L)p.s.5–8 = 25/0.5 μm, (W/L)n.s.5–8 = 12.5/0.5 μm for Inv5-8 and

(W/L)1–3 = 10/0.5 μm, (W/L)4,5 = 30/0.5 μm for the differential amplifier. The scale

factor was m=4 and the bias current of amp was IB = 1μA.

The cutoff frequency of the filter as a function of tuning current is plotted in

Figure 4.9. Frequency response for tuning current IT1 ranging between 10μA and

80μA are plotted in Figure 4.10. The lowest and highest frequencies are 0.97MHz and

5.1MHz corresponding to tuning currents 10μA and 80μA respectively. Considering

that the filter operates in weak inversion, this can be considered as a good range.

Figure 4.9 Cutoff Frequency of the Filter as function of IT1


62

Table 4.1 Parameter values of the filter with corner variations

Unit Typical Fast-best Slow-worst

Temperature oC 27 -25 80

Cutoff frequency MHz 0.970 1.165 0.819

Power Consumption

@IT1 =10uA

μW -339.2 -328.5 -338.7

Consumption Current μA -678.4 -657.0 -677.5

DC differential gain dB -8.1 -8.6 -7.4

CMRR dB -31.3 -31.0 -31.5

Dynamic Range dB 63.13 65.44 60.49

Integrated Noise

(1KHz-1MHz)

μVrms 9.4 7.0 12.8

Input Referred Noise

(1KHz – 1MHz)

μVrms 25.5 19.5 34.6


(Spot Noise@1KHz)

nV/Hz 217.51 193.12 242.85


(Spot Noise@1MHz)

nV/Hz 27.56 16.75 46.44

DC Output Voltage mV 249.9 249.7 251.4

Input Offset mV -0.06 -0.331 1.359


63

Figure 4.10 Frequency Response for a range of IT1 from 10μΑ to 80μA

The relation between tuning current and cutoff frequency is not completely

linear, especially at higher value of tuning current, unlike what is expected from the

eq. 4.5. The tuning range of the OTA and thus of the filter is defined by relatively

high drain current variation, by increasing the drain current of a MOS drain source

conductance is decreased, which influences the behavior of the gm with respect to IT,

which affects the accuracy of the eq.4.5 , and eventually the graph of gm with respect

to IT does not remain linear for high values of tuning current. THD of the filter is

40dB for an input signal with amplitude 51.74mV and Dynamic Range of the filter is

63.13. For an input voltage supply of 0.5V the filter consumes 339.2μW of power and

678.4μA of current.

The process and mismatch variations on the cutoff frequency are analyzed by

monte-carlo simulation. The result is shown in Figure 4.11, the mean value is at

0.97MHz with a standard deviation σ=17.4KHz, indicating a 1.7% deviation from the

nominal value. Corner analysis simulation is performed keeping tuning current

IT1=10μA and input amplitude 51.75mV, the results are summarized in Table 4.1.


64

Figure 4.11 Monte Carlo simulation results for the filter cutoff frequency

In the corner analysis, most of the parameter remained unaffected, instead of

the cutoff frequency, which could have been mostly due to capacitor variation. To

avoid the deviation of fully integrated filter from nominal frequencies with corner

variations, an automatic tuning is required. The proposed filter is capable of automatic

tuning, because of its ability for electronic tuning.

The performance of this filter is compared with some other implementations

of the gm-C filters and summarized in Table 4.2. Remarkably the supply voltage and

power consumption of this filter is lowest. Other parameters like THD, Dynamic

Range, noise, operating frequency and tuning range are comparable with other works.

Considering the filter operates in weak inversion using transistor of typical threshold,

for a very low supply voltage, the frequency tuning range offered by this filter is

appreciable.


65

Table 4.2 Comparison with other filter topologies

Unit This Filter [4.5] [4.6] [4.7] [4.8] [4.9]

Process 0.13μm

CMOS

0.35μm

CMOS

0.35μm

CMOS

0.18 μm

CMOS

0.18μm

CMOS

0.35μm

CMOS

Supply/VDD V 0.5 1.1 1.2 1.8 1 2.7

Filter Order 3 2 2 4 3 4

Bandwidth MHz 0.9705 2.66 3 -- -- 2.5

Frequency

/Tuning

range

MHz 0.97 – 5.1 0.05 – 2.6 -- 0.5 - 12 0.135 - 2.2 0.2 – 2.5

Linearity/

THD

dB THD -40dB

@

51.75mVpp

THD -38dB

(0.4Vp-p@

2.6MHz)

THD -40dB

@

1.8Vp-p

-- IM3 < 68.5

dB @ 2 MHz

Linearity 1

dB Comp

620 mVp-p

diff

Power

Consumption

μW 332 720 382 1100-4700 2000 1674

Spot noise nV/ Hz

@1MHz 27.56 -- -- -- 65 41

Integrated

noise

μVrms 9.44# -- 210 * -- -- --

Dynamic

Range

dB 63.13 -- 69.6 -- -- --

Type of

Driving

Bulk

Driven

Gate

Driven

Bulk

Driven

Gate

Driven

Gate

Driven

Gate

Driven

Application Bluetooth GSM, UMTS,

WCDMA

2nd

order

FD OTA-C

low pass filter

IEEE802.1

W-LANs,

W-CDM,

Bluetooth

GSM,

Bluetooth,

CDMA 2000,

wide-band

CDMA

GSM, IS-95,

UMTS

*Integrated input referred Noise (100Hz – 4MHz)

#Total Summarized Noise (Output Noise 1KHz-1MHz)


66

Figure 4.12 Transconductance of the OTA with respect to Tuning Current

4.4.1 MODIFICATION OF ASPECT RATIO OF OTA

To improve the performance of the OTA, the aspect ratio of the transistors

were further modified and increased from the previous values. The new aspect ratios

were (W/L)p.s1-4=100μm/0.2μm, (W/L)n.s.1-4=50μm/0.2μm for Inv1-4, (W/L)p.s.5-8 =

100μm/0.2μm, (W/L)n.s5-8=50μm/0.2μm for Inv5-8. In Figure 4.6.a, the aspect ratio of

the transistors used in the amplifier were (W/L)1-3 = 100μm/0.5μm, (W/L)4,5 =

30μm/0.2μm. Scale factor was m=1, the bias current was IB = 1 μA and the supply

voltage was 0.5V. With these new aspect ratios, the parameters of the 3rd

order filter

were recalculated again.

The third order Butterworth filter with modified aspect ratio has a cutoff

frequency equal to 1MHz for IT1=10μΑ. The capacitors in the filter have values

C1=C3=86pF and C2=172pF and the capacitors in the control circuit Cp and Cn are

both 1pF. In Table 4.3 the parameters of the filter with new aspect ratio and old aspect

ratio are listed.

As expected, the transconductance of OTA has increased with increase in

aspect ratio as shown in Figure 4.12. The frequency range and power consumption of

the filter has remained almost unchanged, the bandwidth is increased by the increase

in gm, for which the capacitance value are altered to make the cutoff frequency equal

to 1MHz.


67

Table 4.3 Parameter values of the 3rd

order filter with different aspect ratios

Unit Before Modifying

Aspect Ratio

After Modifying

Aspect Ratio

Supply Voltage V 0.5 0.5

Cutoff frequency MHz 0.970 1

Bandwidth MHz 0.970 1

Frequency Tuning Range MHz 0.97-5.1 1.00-5.13

Power Consumption

@IT1 =10uA

μW -339.2 -347.872

Current Consumption μA -678.4 -695.743

DC differential gain dB -8.1 -1.695

CMRR dB 31.3 39.17


(Spot Noise@1KHz) nV/Hz 217.51 21.77


(Spot Noise@1MHz) nV/Hz 27.56 23.28

Integrated Noise

@(1KHz-1MHz)

μVrms 9.4 14.13


(1KHz–1MHz)

μVrms 25.5 17.44

THD dB [email protected] 40@231mVpp

Dynamic Range dB 63.13 79.43

DC Output Voltage mV 249.9 250

Input Offset mV -0.06 0

Standard Deviation KHz 17.414 14.586


68

There is a significant improvement of 6.4dB in DC gain by the reduction of

channel length of the MOS. The reduction in channel length of MOS has resulted in

the increase of transconductance. Increase in DC gain can be explained by the fact

that in Nauta’s Transconductor the DC gain enhancement depends upon the

transconductance of the Inv5-Inv8 in the transconductor [4.2]. Noise is also reduced

with new aspect ratios and the dynamic range has improved from 63.13dB to

79.43dB. CMRR has improved from -31.3 dB to 39.17dB. Standard deviation of the

filter has also improved from 17.41 to 14.586, indicating only 1.5% deviation from

the nominal value.

4.5 CONCLUSIONS

This chapter presents a low voltage filter operating at ultra-low voltage of

0.5V. OTA employed in this filter is bulk-controlled and its transconductance gm can

be tuned by a single current control. Eventually the filter is tunable with an

appreciable tuning range. The filter shows low power consumption, good

performance in terms of noise, linearity, tunability and dynamic range. The aspect

ratio of the OTA is further changed to improve the performance of the transconductor.

With new aspect ratio gm of the OTA is increased and eventually the filter has better

gain, CMRR, noise, and dynamic range. Meanwhile the frequency range and power

consumption have remained almost unaffected. This OTA used has no internal node

and thus can also be used for the filters of higher order for low IF filter which will be

discussed in the following chapter.

4.6 REFERENCES

[4.1] T. Deliyannis, Y. Sun, J. K. Fidler, “Continuous-Time Active Filter Design,”

CRC Press 1998.

4.6 References

69


frequencies," IEEE Journal of Solid-State Circuits, vol. 27, no. 2, pp. 142-153,

Feb 1992.


Integrated Circuits and Signal Processing, Vol. 72,Issue 1, pp. 289-292, July

2012.

[4.4] R. Arya, G. Souliotis, S. Vlassis, C. Psychalinos, “A 0.5V 3rd

order tunable

gm-C filter,” Radioengineering, Vol. 22, No. 1, pp. 174-178, April 2013.

[4.5] M. Santhanalakshmi, P. T. Vanathi, “An improved OTA for a 2nd

order gm-C

low pass filter,” European Journal of Scientific Research, vol. 66, no. 1, pp.

75–84, 2011.

[4.6] J. M. Carrillo, M. A. Dominguez, J. F. D. Carrillo, “1.2V fully differential

OTA-C low-pass filter based on bulk-driven MOS transistors,” In Proc. of the

20th European Conf. on Circuit Theory and Design (ECCTD), pp. 178-181,

2011.

[4.7] S. Hori, T. Maeda, N. Matsuno, H. Hida, “Low-power widely tunable gm-C

filter with an adaptive DC-blocking, triode biased MOSFET transconductor,”

In Proceeding of the 30th

European Solid-State Circuits Conference

(ESSCIRC), pp. 99-102, 2004.

[4.8] T. Y. LO, C. C. Hung, “Multi-mode Gm-C channel selections filter for mobile

applications in 1V supply voltage,” IEEE Transactions on Circuits and

Systems-II: Express briefs, 2008, vol. 55, no. 4, pp. 314-318.

[4.9] U. Stehr, F. Henkel, L. Dalluge, P. Waldow, “A fully differential CMOS

integrated 4th order reconfigurable GM-C low pass filter for mobile

communication,” In Proceeding of the 11th

IEEE International Conference on

Circuits and Systems (ICECS). 2003, vol. 1, pp. 144-147.



http://link.springer.com/journal/10470/72/1/page/1


70

71

5. CHAPTER 05 COMPLEX FILTER FOR BLUETOOTH AND ZIGBEE

COMPLEX FILTER FOR

BLUETOOTH AND

ZIGBEE

05

5.1 INTRODUCTION

In the previous chapter a 3rd

order low pass filter is described. The filter has

used an OTA which is tunable and operates for ultra-low voltage of 0.5V. In this

chapter this OTA will be utilized to build a 6th

order complex filter suitable for

Bluetooth and Zigbee operations. Complex filter were invented by Sedra in 1985. It

was a frequency shifted version of a low pass filter response, it can pass the signal at

ω=ωIF, while attenuate the signal at ω=-ωIF. That filter was named complex because

its time domain response was complex, as its frequency response was unsymmetrical

around the jω axis [5.1]. However, the frequency response of a complex filter is

symmetrical around jω axis. Before discussing complex filters, it is necessary to have

an overview of the RF architecture in order to understand the reason for the

requirement of the complex filters.

5.1.1 RECEIVER ARCHITECTURE

Choosing receiver architecture is a challenging job, keeping in mind the

requirements like highest level of integration, lowest power consumption and at the

same time aiming for the most optimum performance. Achieving all these

requirements in a single architecture is a goal quite difficult to accomplish and

obviously several tradeoffs are made to find an architecture that meets the standard

Chapter 05 Complex Filter for Bluetooth and Zigbee

72

specifications. The parameters of wireless standards like bandwidth sensitivity,

selectivity, blocking specification also play an important role in making the choice of

the most suitable architecture.

Several architectures like high Intermediate Frequency (IF), low IF and direct

conversion are employed in RF receivers.[5.2][5.3] For Bluetooth and Zigbee

architecture a low IF structure is most suitable. Low IF structures offer relaxed Image

rejection requirements, while on the other hand high IF structure require increased

channel selectivity and power consumption although it improves the demodulator

performance. On the other hand in direct conversion architecture, flicker noise and

DC offset significantly degrade the signal to noise ratio (SNR).

5.1.2 LOW IF RECEIVER ARCHITECTURE

Low IF receiver are widely use in mobile phones, and other small devices

where tiny receivers are incorporated [5.4] In a low IF receiver, the RF signal is

down converted to a low or moderate intermediate frequency of few megahertz by

multiplying it with a sinusoidal signal, as shown in Figure 5.1 However the technique

suffers from a serious flaw of the presence of unwanted ‘image signal’ along with the

wanted signal. An image frequency is an undesired input frequency equal to the

station frequency plus twice the intermediate frequency. The image frequency results

in two stations being received at the same time, thus producing interference.

Figure 5.1 Front end stage of a Low IF receiver

5.1 Introduction

73

Figure 5.2 Down-conversion of signal with a real LO sinusoidal signal

In Figure 5.2 down-conversion of a signal with sinusoidal signal from local

oscillator signal is shown. When the RF signal is multiplied by the sinusoidal signal

from the local oscillator, it is equivalently multiplied by both the exponents

and [5.3][5.5]. Mathematically it may be expressed as

(5.1)

(5.2)

(5.3)

Multiplying sinusoidal signal from local oscillator to the input RF frequency

(5.4)


74

(5.5)

From equation 5.5, it can be seen that the RF spectrum is down-converted to

IF frequency and up-converted to higher IF as well. The up-converted elements can be

removed easily by using a low-pass filter, and do not pose a serious problem, and

hence can be ignored. But down-converted element has the desired frequency as well

as image frequency at the same IF. By means of a band-pass RF filter this signal is

suppressed before down-conversion of the RF signal. The quality factor of such filter

is proportional to fRF/fIF. For this purpose high quality factor external SAW or ceramic

filters are used which increase the complexity as well as the power consumption of

the whole receiver.

The solution to this image problem is that the RF signal must be multiplied by

an exponential instead of a sinusoidal signal. But an exponential means a real and

complex signal together. Now the equation will take the form as

(5.6)

(5.7)

Again in this equation the up-converted terms may be ignored. And xsig and xim

can be considered as signal and image amplitudes of the signal and image

respectively. And also

(5.8)

(5.9)

So, equation 5.7 may be expressed as

5.1 Introduction

75

Figure 5.3 Down-conversion of signal with a single exponential

(5.10)

(5.11)

From equation 5.11 it can be concluded that the desired signal is easily

obtained with real part centered at ωIF and the imaginary part is shifted to -ωIF, as

shown in Figure 5.3. However implementing this complex multiplication is a tricky

part! But this can be achieved simply by using two quadrature input branches I and Q

so that RF signal is multiplied by (cosωLO) in I branch and by (–sinωLO) in Q branch

as shown in Figure 5.4. The resulting image signal can be rejected using a complex

filter, whose principles will be discussed in the next section.

The quality factor of complex filter is proportional to ωIF/BW where BW is the

bandwidth of the filter, which is small in low IF receivers. The mismatch of I and Q is

very significant in the complex filter because it may lead a limited Image Rejection

Ratio (IRR) This IRR depends upon the phase and gain imbalances [5.2] can be

mathematically expressed as


76

Figure 5.4 Front end diagram of basic Low IF Architecture

(5.12)

where ε denotes the relative gain mismatch, θ denotes the phase imbalance between I

and Q branches, and gain of local oscillator is assumed unity for simplification. For

ε<<1 and θ <<1, equation 5.12 may be rewritten as

(5.13)

For typical matching in the integrated circuits, image suppression falls in the

range of 30-40dB, indicating a 0.2 to 0.6 dB gain mismatch and 1o to 5

o of phase

mismatch. However in most RF applications the overall suppression must be around

60 to 70 dB.

5.1.3 ARCHITECTURES TO REMOVE IMAGE SIGNAL

Low IF structures suffer from the problem of image signal appearing at the

same IF as the wanted signal. Several architectures like Hartley architecture, Weaver

Architecture, Passive and Active polyphase filters are proposed to remove this

undesired image signal.

5.1 Introduction

77

Figure 5.5 Block Diagram of the Hartley Receiver Architecture

a) HARTLEY ARCHITECTURE

The Hartley architecture [5.2] in Figure 5.5 mixes the RF input with

quadrature phases of local oscillator, the resulting signals are treated with a low-pass

filter to reject the up-converted signal, and then one of the signals is shifted by 90o,

later the two signals are added together. Upon adding signals at B and C, the image

signal is removed and the RF signal is down-converted without the corruption of

image signal.

However the Hartley architecture is extremely sensitive to mismatches, if the

quadrature LO inputs are not exactly 90o phase apart, then the resultant signal will

contain some image signal. Also the monolithic implementation of this architecture

has issues with the low pass filter’s incapability to suppress interference from the

neighboring channels, linearity of the adder and noise as well, eventually affecting the

overall performance of the design.

b) WEAVER ARCHITECTURE

In the Weaver architecture [5.2], the signal after passing through the low-pass

filter is again subjected to multiplication by a quadrature signal as shown in Figure

5.6. Assuming ω2<<ω1 the spectrum at point A will be convolved with

j[δ(ω+ω2)-δ(ω-ω2)]/2


78

Figure 5.6 Block Diagram of the Weaver Receiver Architecture

yielding translated replicas at point C with no factor j. Similarly at point B is

convolved with

[δ(ω+ω2)-δ(ω-ω2)]/2

which is translated both up and down in frequency. Subtracting the signals at C and D

will yield an IF output which will be free from image signal, since the image replica

will cancel each other. By using one more low-pass filter at output the image at

ω2+ωIF and –ω2+ωIF may be removed. Also this architecture cannot remove the

interference appearing at the second mixer, for this reason the low-pass filters are

replaced with band-pass filters in this architecture.

Both Hartley and Weaver architectures suffer from incomplete rejection of

image signal due to gain and phase mismatches. To implement the weaver

architecture requires extra mixers, frequency synthesizers and high order band-pass

filter and hence the power consumption as well as chip area is considerably large.

c) POLYPHASE/COMPLEX FILTERS

Polyphase filters are more commonly called complex filters, come in two forms–

a) Passive Polyphase Filter and b) Active Polyphase Filter. Passive filters can be used

in front of the ADC or can be embedded in ΣΔ ADC loop [5.6]. Passive RC polyphase

filters have high image rejection ratio [5.7], but they cannot achieve required

attenuation of the adjacent channel interference, due to their limited selectivity, also

5.2 Theory of Complex Filter

79

they have finite input impedance, which load the RF mixers. While active polyphase

filters offer good image rejection and adjacent channel interference rejection without

the complexities imposed by passive polyphase filter. In the next sections the theory

of complex filter and its implementation will be described.

5.2 THEORY OF COMPLEX FILTER

The basic model of operation for a complex filter is that it uses the down-

converted I and Q signals which are obtained after multiplying a local oscillator’s

quadrature signal to RF signal, as shown in Figure 5.7. The complex filter shifts the

image part to ω = -ωIF and hence remove it from the wanted signal obtained at

ω=ωIF. [5.8], [5.9], [5.10].

As discussed earlier the RF input is multiplied with the LO signals which are

90o phase apart. From equation 5.11

After applying this signal to complex mixing the result [5.3] will be

(5.14)

Figure 5.7 Front-end stage block diagram of low-IF receiver using a complex filter


80

Figure 5.8 Frequency Shifter of a complex mixer. a) Before complex mixing and

b) After Complex Mixing

where BI and BQ are the real and imaginary part of the output obtained from the

mixer.

(5.15)

(5.16)

From equation 5.16 it can be seen that the image and signal are 90o apart and

the separation of 2ωIF is still maintained after down-conversion as can be seen in

Figure 5.8. It happens so, since the complex filter has an unsymmetrical response

around the jω axis while at the same time it is symmetrical around ωIF i.e.

intermediate frequency. So, in complex domain the complex band-pass filter is a

frequency shifted version of a low-pass filter.

This frequency shifting can be mathematically explained as

5.2 Theory of Complex Filter

81

Figure 5.9 Frequency shifting effect on a) Transfer Function

b) Pole locus of a real low-pass filter

(5.17)

where ωIF is the frequency shift in the transfer function.

Eventually the transfer function of the low-pass filter will transform into the transfer

function of a band-pass filter, given as

(5.18)

The shift in transfer function will result in the shift of the poles around the jω

axis, as shown in Figure 5.9. Since in this work the ladder filters are used therefore

this transfer must be applied to the lossy and lossless integrators used in that filter.

The transfer function of the integrator will transform from low pass to high pass filter.

(5.19)


82

Figure 5.10 Diagram showing frequency shifting to convert LPF to Complex BPF

and,

(5.20)

will become

(5.21)

and,

(5.22)

The topology of a low pass integrator can be transformed to a band-pass

integrator which is shown in Figure 5.10. To make the integrator lossy, one more gmC

unit is added in a negative feedback loop. The details of the complex integrator will

be discussed in the next section.

5.3 COMPLEX INTEGRATOR

Block diagrams of the complex lossless and lossy integrators used in this filter

are shown in Figure 5.11 and Figure 5.12, respectively. The modified Nauta’s

transconductor discussed in the previous chapter [5.11], [5.12] are used as core in

these integrators. For other transconductor used in the integrator, two inverters Inv1

and Inv2, from the input of transconductor shown in Figure 5.13 are removed, such

5.3 Complex Integrator

83

that now it will have only single differential input. To obtain the lossy integrator as in

Figure 5.12 a negative feedback is applied to the input transconductors of the lossless

integrators Figure 5.11.

Expressing the quadrature input and output signal as,

xi = (vI1I+ - vI1I- + vI2I+ - vI2I-) + j (vI1Q+ - vI1Q- + vI2Q+ - vI2Q-) (5.23)

and xo= (vOI+ - vO1-) + j (vOQ+ - vOQ-) (5.24)

and after an analysis for the lossless integrator circuit in Figure 5.11, the frequency of

the quadrature output signals I and Q, may be expressed as,

(5.25)

(5.26)

where, ωο = C/gmo and ωIF = ωο (gmIF /gmo).

Currents ITA, ITB and ITC in Figure 5.11 and Figure 5.12 are used to control the

transconductance value of each transconductor as given by (5.27)-(5.29),

gmo = 2ITA / nVt (5.27)

gmIF = 2ITB / nVt (5.28)

gmo’ = 2ITC / nVt (5.29)

where, n is the slope factor and Vt=kT/q is thermal voltage. The bandwidth and center

frequency of filter are controlled by controlling gmo and gmIF respectively. Although

the transconductance gmo’ has the same value with the value of gmo , the ability for

independent control through the current ITC can be used for compensation reasons.


84

Figure 5.11 Block Diagram of Lossless Integrator

Figure 5.12 Block Diagram of Lossy Integrator

The functioning of the transconductor is discussed in previous chapters. For

the double differential input transconductor is modified to incorporate four input

terminals, as shown in Figure 5.13. It operates in weak inversion and the

transconductance of this OTA [5.12] is given by eq. 5.30.

(5.30)

5.3 Complex Integrator

85

Figure 5.13 Double differential Input transconductor

As evident the transconductance is dependent upon the tuning current IT. Upon

employing these OTAs in the integrator and further in the complex filter each tuning

current has a specific impact on the behavior of the filter. While ITA and ITB control

bandwidth and center frequency respectively, ITC controls the DC gain of the filter,

however ITC must be kept equal to ITA in order to achieve balanced filter

characteristics. The output current of the OTA in Figure 5.13 is given as

(5.31)

Figure 5.14 Passive 6th

order filter


86

Figure 5.15 Signal Flow Graph for 6th order complex filter

5.4 FILTER DESIGN EXAMPLE

In this work a 12th order complex filter is presented. A Butterworth

approximation is chosen for this filter design because it has small group delay

variation within pass-band and all the poles will have same angular frequency leading

to a better matching in cross-coupled OTA in the filter [5.13]. The poles of a

Butterworth filter are evenly spaced around the circumference of a half-circle of

radius ωc centered upon the origin of the s-plane. With the advent of technology,

decreasing size and demand in increase of battery life has made low voltage operation

very important in the portable device. Many topologies of complex filter have been

proposed based on current mirror [5.5], Active RC bi-quads [5.14], second generation

current conveyors [5.15]. Other topologies use quadrature receivers with gmC filter

[5.16], gyrator low pass filter [5.17], log domain filter [5.18], and current feedback

operational amplifier [5.19]. The passive filter prototype used to design the complex

filter is shown in Figure 5.14. The Butterworth function for this filter is

(5.32)

The normalized element values for this function are C1p=0.518F, L2p=1.414H,

C3p=1.932F, L4p=1.932H, C5p=1.414F, and, L6p=0.518H. The 12th

order complex filter

is realized by employing the signal flow graph shown in Figure 5.15 for the leapfrog

design technique, with the lossy and lossless integrators from Figure 5.11and Figure

5.12. The block diagram of leapfrog filter will come out to be like as shown in Figure

5.16.a, which take form of the active filter once the blocks are replaced by the


87

Figure 5.16 a) Block Diagram of the Active Ladder Simulating 6th

order Leapfrog

filter topology b) Leapfrog topology for the 3rd

order filter using OTA

integrators as shown in Figure 5.16.b. Treating the lossy and lossless integrators as a

core, and employing leapfrog topology to them, 12th

order filter is obtained as shown

in Figure 5.17

The complex filter is designed to meet the requirements of the Bluetooth and

Zigbee standards. For the switching the function of filter from Zigbee to Bluetooth

two options are available, 1) the transconductance of the OTA can be doubled by

using the tuning currents and 2) the capacitance of the filter can be halved. In this

work second method is used, considering that the increase in gm depends on the


88

Figure 5.17 12th

order complex filter.

increase in tuning current, which must be kept in the operational limits and also

increase in current will mean increase in power consumption. To facilitate the simpler

operation capacitors are connected with a simple switch which can easily double or

half the effective net capacitance while being set in ON or OFF state. The critical

requirements of the two standards with complex filter implementations are Image

Rejection Ratio (IRR), blocker attenuation, linearity, and in-band group delay

variation. The filter is designed and tested for these standards of Bluetooth and Zigbee

5.4.1 BLUETOOTH

Bluetooth was developed by Ericsson to be implemented for short range

wireless network voice and data link between devices such as PC mobiles, notebooks,

PDAs and digital cameras, creating a personal area network (PAN) with high levels of

security. It can connect several devices, overcoming problems of synchronization. A

Bluetooth transceiver is a frequency-hopping spread-spectrum device that uses the

unlicensed (worldwide) 2.4 GHz ISM (Industrial, Scientific, and Medical) frequency


89

Table 5.1 Table of Tuning Current and Capacitance for Bluetooth and Zigbee

Unit Bluetooth Zigbee

ITA (μA) 12.7 12.7

ITC (μA) 12.7 12.7

ITB (μA) 13.8 13.8

ITB1,6 (μA) ITB ITB

ITB2,5 (μA) 3.2* ITB 3.2*ITB

ITB3,4 (μA) 4* ITB 4* ITB

C (pF) 180 90

C1 (pF) 0.6*C 0.6*C

C2 (pF) 1.6*C 1.6*C

C3 (pF) 1.9*C 1.9*C

C4 (pF) 1.9*C 1.9*C

C5 (pF) 1.7*C 1.7*C

C6 (pF) 0.6*C 0.6*C

band. There are 79 channels available, where the nominal bandwidth for each channel

is 1 MHz, while the effective data rate is at 723.2 Kbit/s. For the operation of the

complex filter with Bluetooth standards the filter bandwidth must be 1MHz, which is

equal to the channel bandwidth, and the center frequency must also be 1MHz.

Blocking attenuation of the adjacent channels for Bluetooth standards must be 11, 41

and 51 dB attenuation at 1, 2 and 3 MHz away from the center frequency for the 1st,

2nd

, and 3rd

blocker attenuation respectively. IRR must be 20-30dB and in-band group

delay variation must be ≤1 μs.


90

5.4.2 ZIGBEE

Zigbee is used in applications that require a low data rate, long battery life,

and secure networking. Zigbee devices often transmit data over longer distances by

passing data through intermediate devices to reach more distant ones, creating a mesh

network; i.e., a network with no centralized control or high-power transmitter/receiver

able to reach all of the networked devices. To implement complex filter with Zigbee

standards, the bandwidth must be 2MHz with central frequency also 2MHz. Blocking

attenuation are similar to that for Bluetooth but at the frequencies 2, 4 and 6 MHz.

IRR must be 20-30 dB like Bluetooth and also in-band group delay variation must be

≤1. As it can be seen, that requirements of bandwidth and center frequency can be

easily fulfilled by halving the capacitors of the filter used in Bluetooth. The de-

normalized values of capacitor and tuning currents for Bluetooth and Zigbee are

summarized in Table 5.1. Although the capacitors C2 and C5 should be identical, they

are slightly different to compensate internal parasitic capacitances which affect the

response of the filter.

Figure 5.18 a) Amplifier of the tuning circuit and b) Tuning Circuit used in the OTA

http://en.wikipedia.org/wiki/Mesh_network

http://en.wikipedia.org/wiki/Mesh_network


91

5.5 SIMULATION RESULTS

To verify the operation of the proposed filter, the circuit was designed and

simulated using a triple well 0.13μm CMOS process. The transistors with normal

threshold voltage (Vth) have been used in the simulations and not the recently offered

low Vth transistors. The transconductors used for cross coupling have three different

tuning currents (ITB) in all six stages. The relationship between the particular ITB in

each stage of the filter, is approximately same as the ratio of the normalized element

values of the passive filter. The tuning current for the six stages are, ITB for the 1st and

6th

stage, 3.2*ITB for 2nd

and 5th

stage, and 4*ITB for 3rd

and 4th

stage, where ITB

=13.8μA.

The aspect ratio of transistors of the transconductor in Figure 5.13 were

(W/L)p.s1-4 = 100μm/0.2μm, (W/L)n.s.1-4 = 50μm/0.2μm for Inv1-4, (W/L)p.s.5-8 =

100μm/0.2μm, (W/L)n.s5-8 = 50μm/0.2μm for Inv5-8. In Figure 5.18.a, the aspect ratio

of the transistors are (W/L)1-3 = 100μm/0.5μm, (W/L)4,5 = 30μm/0.2μm for the

amplifier. Scale factor was m=1, the bias current was IB=1μA, and supply voltage was

0.5V.

Figure 5.19 Frequency Response of Signal and Image frequency for Bluetooth


92

Figure 5.20 Frequency Response of Signal and Image frequency for Zigbee

Figure 5.21 Group Delay for Bluetooth


93

Figure 5.22 Group Delay for Zigbee

The filter is simulated for Bluetooth and Zigbee standards with supply voltage

VDD=0.5V. The Bandwidth of the filter is 1MHz and 2MHz for Bluetooth and Zigbee

respectively. Center Frequency is 1MHz and 2MHz for Bluetooth and Zigbee

respectively. Power consumption for both Bluetooth and Zigbee is 2.77mW. The

image rejection ratio for both configurations is better than 70dBc at their respective

center frequency, shown in Figure 5.19 and Figure 5.20. In-band group delay

variation is 0.8μs for Bluetooth and 0.46μs for Zigbee, shown in Figure 5.21 and

Figure 5.22.

The center frequency and bandwidth of the filter are independently,

orthogonally tunable. For the range of ITB from 10μA to 30μA the center frequency is

varied from 0.84MHz to 1.22MHz for Bluetooth as shown in Figure 5.23. In the

similar manner bandwidth is also controlled by tuning current ITA, for range of current

from 10μA to 22μA the bandwidth varies from 0.78MHz to 1.72MHz for Bluetooth as

shown in Figure 5.24. The DC gain of the filter is affected by ITC, which can be

observed in Figure 5.24, however ITC is kept equal to ITA in order to obtain balanced

characteristics of the filter. Similar orthogonal tuning is observed for the Zigbee


94

configuration as well. Center frequency can be varied in from 1.64MHz to 2.35MHz

for ITB 10μA to 30μA and bandwidth can be tuned in a range of 1.56MHz to 3.72MHz

for ITA 10μA to 22μA.

Figure 5.23 Tuning of Center Frequency with tuning current ITB for Bluetooth

Figure 5.24 Tuning of Bandwidth with tuning current ITA for Bluetooth


95

Figure 5.25 IIP3 Curve for in-band linearity for Bluetooth filter

Figure 5.26 IIP3 Curve for in-band linearity for Zigbee filter

In order to test the linearity of the filter third order intercept point (IIP3) and

Spurious Free Dynamic Range (SFDR) are simulated/calculated. The in-band IIP3 is

-4.4dBm for Bluetooth and -4.6dBm for Zigbee as shown in Figure 5.25 and Figure

5.26. In-band SFDR is 43.84dB for Bluetooth and 42.26 for Zigbee. Out-of-band IIP3

is 9.74dBm and 6.15dBm for Bluetooth and Zigbee respectively, and out-of-band


96

SFDR is 53.27dB and 49.36dB respectively for Bluetooth and Zigbee. Output noise is

15.96μVrms for Bluetooth and 21.09 μVrms for Zigbee. The common mode rejection

ration (CMRR) is better than 101dB and power supply rejection ratio (PSRR) is better

than -44.43 for both Bluetooth and Zigbee. The performance characteristics of the

filter for Bluetooth and Zigbee are listed in Table 5.2.

Figure 5.27 Monte Carlo analysis responses for Bluetooth

Figure 5.28 Monte Carlo analysis responses for Zigbee


97

Figure 5.29 Monte Carlo analysis for bandwidth of Bluetooth filter

Figure 5.30 Monte Carlo analysis for bandwidth of Zigbee filter


98

Table 5.2 Performance characteristics of the proposed complex filter

Performance Factor Unit Bluetooth Zigbee

Supply voltage (VDD) V 0.5 0.5

Power dissipation mW 2.77 2.77

Current consumption mA 5.54 5.54

Center frequency (fIF) MHz 1 2

Bandwidth MHz 1 2

In-band group delay variation μs 0.8 0.46

Spot Noise @Cen. Freq. V/sqrt(Hz) 59.7n 55.3n

Output noise μVrms 15.96 21.09

IRR @Cen. Freq. dB 71.90 72.58

First blocker attenuation (fIF+Δf) dBc 35.35 38.88

Second blocker attenuation (fIF+2Δf) dBc 72.84 74.50

Third blocker attenuation (fIF+3Δf) dBc 93.92 95.45

In-band IIP3 dBm -4.4 -4.65

Out-of-band IIP3 dBm 9.74 6.15

In-band SFDR dB 43.84 42.26

Out-of-band SFDR dB 53.27 49.36

CMRR @Cen. Freq dB 101.12 101.35

PSRR @Cen. Freq dB 44.34 44.34


99

Table 5.3 Comparison with recent works

Performance Factor Unit this work [5.16] [5.18] [5.19]

Technology CMOS (μm) 0.13 0.09 0.35 0.35

Order 12 6 12 12

Type gm-C gm-C log-domain Active RC

Supply Voltage (V) 0.5 1.2 1.2 1.2

Power Consumption (mW) 2.77 3.6 10.9LF

/15.4W

5.6

Center Frequency (MHz) 1BT

/

2ZB

2 0.92BT

/

1.9ZB

Bandwidth (MHz) 0.5-1.5BT

/

(& 1-3)ZB

IF band

1-3MHz

1.54-2.50LF

/

1.59-2.40W

0.92BT

/

1.9ZB

In-band group delay (μs) 0.8BT

/ 0.46ZB

-- -- 1BT

/

0.5ZB

Input Ref. Noise (μVrm

s) 69

BT/90

ZB -- -- 260

Image Rejection ratio (dBc) 71.9BT

/

72.6ZB

-- >45.7LF

/

>46.1W

41BT

/

40ZB

1st Blocker attenuation

(fIF+Δf)

(dBc) 35.3BT

/

38.9ZB

-- -- 37

2nd Blocker attenuation

(fIF+2Δf)

(dBc) 72.8BT

/

74.5ZB

-- -- 73.5BT

/

71.5ZB

3rd Blocker attenuation

(fIF+3Δf)

(dBc) 93.91BT

/

95.4ZB

-- -- 94.5BT

/

91ZB

In-band IIP3 (dBm) -4.4BT

/ -

4.65ZB

-12.5 (Prototype I)

-13 (Prototype II

coil free)

-- --

In-band SFDR (dBm) 43.84BT

/

43.67ZB

55.5 (Prototype I)

54.4 (Prototype II

coil free)

36.9LF

/ 36.7W

@1.950

&2.050MHz

45BT

/

44ZB

Out-of-band SFDR (dBm) 53.27BT

/

49.36ZB

-- 49LF

/43.2W

@3 &6 MHz

50.2BT

/

47.6ZB

Independent CF/BW

tuning

Yes No No No

BT → Bluetooth ZB → Zigbee LF → Leapfrog W → Wave


100

Table 5.4 Table for Worst Case Performance (Corner Analysis) for Bluetooth

Unit Fast Best Typical Slow Worst

Temp (oC) -25 27 80

Supply Voltage (V) 0.5 0.5 0.5

Current Consumption (mA) 5.5 5.5 5.3

Bandwidth (MHz) 1.026 1.001 0.9521

Center Frequency (MHz) 1.087 1.00 0.855

CMRR (dB) 100.2 101.1 102

Spot Noise@1MHz (V/sqrt(Hz) 54.9n 59.7n 64.7n


@ 0.5MHz-1.5MHz

(μVrms) 66.9 69.4 116.2

Output Noise

@ 0.5MHz-1.5MHz

(μVrms) 10.7 15.96 23.5

Monte Carlo simulations are performed in order to inspect the process and

mismatch influence on the filter. The mean value for Bluetooth is at 1.002MHz with

standard deviation of 17.9 KHz and for Zigbee the mean value is at 1.991MHz with

standard deviation 35.4 KHz. Monte-Carlo bandwidth response for Bluetooth and

Zigbee is shown in Figure 5.27 and Figure 5.28. The Monte-Carlo ac response for

Bluetooth is shown in Figure 5.29 and Zigbee is shown in Figure 5.30.

The performance of this filter is compared with recent works operating with

low supply voltage and a relative analysis is summarized in Table 5.3. This filer has

lowest supply voltage of 0.5V and also lowest power consumption. The Image

rejection ratio of this filter is highest. The SFDR for this filter is also comparable with

other works, considering the low supply voltage and low power consumption; it is

difficult to improve SFDR further. 1st 2

nd and 3

rd blocker attenuation of this filter for


101

Bluetooth and Zigbee is also comparable with other work. Also this filter exhibit

independent orthogonal tuning of both center frequency and bandwidth, which is

rarely available in the majority of the filter designs. Also the performance of this filter

is suitable for bluetooth and Zigbee application standard. Bandwidth, group delay,

Image rejection, and attenuation are within specified limits for bluetooth and Zigbee.

The filter is further tested for the worst case performance using corner analysis

for both Bluetooth and Zigbee standards. The bandwidth, center frequency and

current consumption show variations according to change in process parameters and

temperature. But the noise is seriously affected by these process variations, especially

in the slow worst situation. In Table 5.4and Table 5.5, the results of the corner

analysis for Bluetooth and Zigbee are summarized.

Table 5.5 Table for Worst Case Performance (Corner Analysis) for Zigbee

Unit Fast Best Typical Slow Worst

Temp (oC) -25 27 80

Supply Voltage (V) 0.5 0.5 0.5

Current Consumption (mA) 5.5 5.5 5.3

Bandwidth (MHz) 2.034 1.989 1.903

Center Frequency (MHz) 2.1 2.0 1.7

CMRR (dB) 100.2 101.4 102.3

Spot Noise

@ 2MHz

(V/sqrt(Hz) 49.7n 55.3n 61.0n


@ 1MHz-3MHz

(μVrms) 84.0 90.2 175.5

Output Noise

@ 1MHz-3MHz

(μVrms) 13.8 21.1 31.7


102

5.6 CONCLUSION

In this chapter design of a 6th

order complex leapfrog filer is presented. The

filter is designed for both Bluetooth and Zigbee standards and can choose to operate

in either standard by simply switching the capacitors. The filter works for ultra-low

supply voltage of 0.5V and consumes comparatively small power. The filter employs

gm-C transconductors which are tunable with a tuning current, eventually this filter

also displays orthogonal tuning property, which means its center frequency and

bandwidth can be tuned by tuning current independently. Considering that the MSO

in this OTA operate in weak inversion, the frequency range offered by this filter is

appreciable. The filter shows good IRR and CMRR results, and the SFDR linearity

results of this filter are comparable with other works.

5.7 REFERENCES

[5.1] A. S. Sedra, W. M. Snelgrove, and R. Allen, "Analogue Bandpass Filters

Designby Linearly Shifting Real Low-Pass Prototypes," In Proceedings of

IEEE International Symposium of Circuits and Systems, pp. 1223-1226, 1985.

[5.2] B. Razavi, RF Microelectronics, Englewood Cliff’s NJ: Prentice-Hall, 1998.

[5.3] A. A. Emira, E. Sanchez-Sinencio, “A Pseudo Differential Complex Filter for

Bluetooth with Frequency Tuning,” IEEE Transactions on Circuits and

Systems II: Analog and Digital Signal Processing, Vol. 50, no. 10, pp. 742-

754, Oct. 2003.

[5.4] B. J. Minnis, P. A. Moore, “Wireless Communications Circuits and Systems”

IET Digital Library, 2004.

[5.5] C. Laoudias, and C. Psychalinos, “1.5-V Complex Filters using current

mirrors,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.

58, no. 9, pp. 575-579, 2011.

[5.6] K. Philips, "A 4.4mW 76dB Complex ΣΔ ADC for Bluetooth Receivers," In

proceedings of IEEE International Solid State Circuits Conference, Digest of

Technical Papers. ISSCC, vol.1, pp.64, 478, Feb. 2003.

5.7 References

103

[5.7] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, "CMOS Mixers and

Polyphase Filters for Large Image Rejection," IEEE Journal of Solid-State

Circuits, vol. 36, pp. 873-887, June 2001.

[5.8] W. M. Snelgrove, A. S. Sedra, “State-space synthesis of complex analog

filters,” Proceedings of European Conference of Circuit Theory and Design

(ECCTD), pp. 420-424, 1981.

[5.9] G. R. Lang, P. O. Brackett, “Complex Analogue Filters,” Proceedings of.

European Conference of Circuit Theory and Design (ECCTD), 412-419,1981

[5.10] K. Martin, “Complex signal processing is not complex,” IEEE Transactions

on Circuits and System –I: Regular papers, Vol. 51, no. 9, pp. 1823-1836,

2004.

[5.11] B. Nauta, “A CMOS transconductance-C filter technique for very high

frequencies,” IEEE Journal of Solid-State Circuits, Vol. 27, no. 2, pp. 142-

153, 1992.


Integrated Circuits and Signal Processing, Vol. 72, no. 1, pp. 289–292, 2012.

[5.13] W. Sheng, B. Xia, A.A. Emira, C. Xin, A. Y. Valero-Lopez, S. T. Moon, and

E. Sanchez, “A 3-V, 0.35μm CMOS Bluetooth receiver IC,” IEEE Journal of

Solid State circuits, Vol. 38, pp. 30-42, 2003.

[5.14] A. Balankutty, S. Yu, Y. Feng, and P. Kinget, “A 0.6-V Zero-IF/Low-IF

Receiver with Integrated Fractional-N Synthesizer for 2.4-GHz ISM-band

Applications,” IEEE Journal of Solid-State Circuits, Vol. 45, no. 3, pp. 538–

553, 2010.

[5.15] H. Alzaher, N. Tasadduq, and F. Al-Ammari, “Optimal Low power complex

filters,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.

60, no. 4, pp. 885-995, 2013.

[5.16] M. Tedeschi, A. Liscidini, R. Castello, “Low-Power Quadrature Receivers for

Zigbee (IEEE 802.15.4) Applications,” IEEE Journal of Solid-State Circuits,

Vol. 45, no. 9, pp. 1710-1719, 2010.

[5.17] B. Guthrie, J. Hughes, T. Sayers, A. Spencer, “A CMOS gyrator low-IF filter

for a dual-mode Bluetooth/Zigbee transceiver,” IEEE Journal of Solid-State

Circuits, Vol. 40, no. 9, pp. 1872-1879, 2005.


104

[5.18] C. Psychalinos “Low-Voltage Log-Domain Complex Filters,” IEEE

Transactions on Circuits and Systems I: Regular Papers, Vol. 55, no. 11, pp.

3404-3412, 2008.

[5.19] P. Samiotis and C. Psychalinos, “Low-Voltage Complex Filters Using Current

Feedback Operational Amplifiers,” ISRN Electronics, 2013, Article ID

915758, 7 pages, 2013, doi:10.1155/2013/915758.

105

6. CHAPTER 06 CONCLUSION

CONCLUSION 06

6.1 SUMMARY OF THIS RESEARCH WORK

Designing of Low voltage analog filters was the primary target of this research

work. Various methods for low voltage techniques are analyzed, from technology

modifications to design modification. While technology modification has promising

future, its implementation is limited by the cost effectiveness. Various design

modification offer the possibility of lowering the supply voltage as well. While there

exist some design which can work with low power supply, they have their limitations,

advantage and disadvantage as well.

In this research work bulk controlled MOS transistors, operating in weak

inversion are used to lower the supply voltage requirement of the filter design. In

contrast to the conventional circuits where gate is used to administer input signal and

the circuit usually operated in strong inversion, in bulk driven circuit the input signal

is administered through the bulk/substrate. This reduces the supply voltage

requirement by lowering the threshold voltage of the transistor, this process also

reduces the possibility of occurrence of phenomenon like Latch-up , which would

have required serious caution while biasing the circuit using the gate driven

technique. By operating the transistor in weak inversion, the supply voltage

requirement is lowered.

Chapter 06 Conclusion

106

The bulk controlled transistor is used in transconductor employed in this work,

which is a modified version of Nauta’s transconductor. Nauta’s design which was

meant for high frequency application, operating with high supply voltage is modified

such that it operates for supply voltage as low as 0.5V. The transconductance of this

design can be tuned with the help of a tuning current. This OTA is used to design a 3rd

order tunable gmC filter based on leapfrog technique. The filter operates supply

voltage of 0.5V and is tunable to a wide range, considering the design operates in

weak inversion. The power consumption of the filter is also low and it shows good

results in terms of noise, linearity, tunability and dynamic range.

To improve the performance of this filter the design is further modified and

the aspect ratios of the transistor in the OTA, tuning circuit and amplifier are changed.

The filter with new aspect ratios shows better gain, CMRR, noise and dynamic range.

While the frequency range and power consumption remained almost unchanged.

The OTA is further employed to create a complex filter which is designed to

operate for Bluetooth and Zigbee standards. While choosing receiver architecture a

low IF structure is preferred over high IF and direct conversion architectures.

However low IF structures impose a serious challenge of removing the image signal

which appears at the same frequency as the desired signal, after down-conversion in a

low-IF receiver. Among the various possible architectures to remove the image signal,

complex filter appears the most promising. The complex filter works as frequency

shifter, and doing so it shifts the image signal to ω=ω-IF and passes the desired signal

to frequency ω=ωIF, transforming the transfer function of a low pass filter as a band

pass filter.

The OTAs are used to create a 6th

order complex filter based on leapfrog

technique. The filter is suitable for Bluetooth and Zigbee standards. The filter works

for a supply voltage of 0.5V and has small power consumption as well. The designed

filter has good results with IRR and CMRR. Noise and linearity performance of the

filter are also comparable with the recent works. Apart from the low supply voltage

requirement another advantage of this filter is its tenability, the filter is orthogonally

tunable, meaning that its center frequency and bandwidth can be tuned independently.

6.3 References

107

6.2 FUTURE PROPOSAL

In this research work a tunable gm-C 12th

order complex filter is designed

which operates for ultra-low supply voltage of 0.5V. This filter has lowest values in

terms of the supply voltage and power consumption, IRR and CMRR of this filter are

also better than other works, however there exists some scope of improvements in

term of the linearity of the filter. It is known that OTA are not very good in linearity

because of parasitic capacitance. Although the SFDR of this filter is comparable with

other works but some scope for even better performance may be explored. After

investigating the possibilities of further improvements and implementing them on the

filter, the design can be further implemented on layout level and fabricated on chip.

The fabricated chip may be tested on PCB for more refined analysis of this filter

design.

The filter may be further employed in devices used for bio-medical

applications. For the obvious reasons of portability, durability and longer battery life,

the designs with low supply voltage and power consumption have become a call of

time. This filter may be implemented in bio-medical devices used for monitoring of

physiological parameters. Bluetooth technology is designed for creating wireless

network between the low power devices, therefore the Bluetooth technology seems

promising for the devices operating in the short distance like in an ICU or Emergency

care System or in home care.[6.1]. The bio-medical signals are not as precise as the

telecommunication signals, they exhibit different behavior with every individual, and

therefore the medical devices need adjustment accordingly [6.2]. The filter designed

in this work is orthogonally independently tunable, and therefore can easily fulfill this

requirement.

6.3 REFERENCES

[6.1] K. Penkala, “Biomedical applications of Bluetooth technology,” Pomiary

Automatyka Kontrola, pp. 79-82, 2006.

Chapter 06 Conclusion

108

[6.2] J. Lasa, A. Arnaud, M. Miduez, J. Gak, “On the design of micro power

practical gm-C filters for biomedical applications,” Proceesings of the 24th

symposium on Integrated Circuits and Systems Design, pp. 23-28, 2011.

109

APPENDIX – A

COMMON MODE REJECTION RATIO

The relative sensitivity of a differential amplifier (or other device) of a

differential signal to a common mode signal is called common mode rejection ratio

(CMRR). It is the tendency of the device to reject input signal common to both

inputs. The CMRR is defined as the ratio of the powers of differential gain over the

common mode gain measured in positive decibels –

or

Since the differential gain should exceed the common mode gain the CMRR

must be a positive number, and higher value signifies that the device is better in

rejecting common mode signal. To measure CMRR of a filter the dc gain is measured

for the differential input signal, and is subtracted from the dc gain measured for the

common mode input signal.

POWER SUPPLY REJECTION RATIO

The amount of noise from the power supply that a device could reject is

measured as power supply rejection ratio (PSRR). Expressed in decibels, PSRR is the

ratio of the change in supply voltage to the equivalent differential input voltage it

produces in the device. PSS can be defined mathematically as

Appendix – A

110

Where AV is the open loop gain of a regular feedback loop and AVO is the gain from

VIN to VOUT with regular feedback loop open.

GROUP DELAY

In signal processing a measure of time delay of the amplitude envelopes of

various sinusoidal components of a signal through a device is known as group delay.

It is a measure of time distortion and is calculated by differentiating the insertion

phase response of the device versus frequency. Group delay can be seen as a measure

of the slope of transmission phase response or in simpler terms it is rate of change of

phase around this point in frequency. Mathematically it is expressed as the first

derivative of phase verses frequency.

Where ‘φ’ is in radians and ‘ω’ is in radians/sec. In cadence a pre-defined function is

used to calculate group delay.

TOTAL HARMONIC DISTORTION (THD)

The THD is used to characterize the linearity of the audio systems and the power

quality of the electric power systems. The ratio of the power of the all harmonic

components to the power of the fundamental frequency is defined as the total

harmonic distortion of a signal. Mathematically, for a sine wave input, it may be

expressed as,

The THD is more commonly defined as an amplitude ratio in audio distortion

(percentage THD), the mathematical expression is,

Dynamic Range

111

The THD is usually expressed in percent as distortion factor or in dB relative to the

fundamental as distortion attenuation. In cadence the pre-defined THD function is

used to calculate the total harmonic distortion, measured at the output of the device

under specified conditions.

DYNAMIC RANGE

In a transmission system, the dynamic range is defined as the ratio of the

overload level i.e. the maximum signal power that the system can tolerate without

distortion of the signal to the noise level of the system. The dynamic range is

mathematically defined as

IMAGE REJECTION RATIO

The image frequency is an undesired input frequency equal to the station

frequency plus twice the intermediate frequency in heterodyne receivers. The image

frequency results in two stations being received at the same time, thus producing

interference. The image frequency can be eliminated by using various structures and

one of them is a complex filter. The ability of a receiver to reject interfering signals at

the image frequency is measured by the image rejection ratio. The image rejection

ratio, is the ratio of the intermediate-frequency (IF) signal level produced by the

desired input frequency to that produced by the image frequency. The image rejection

ratio is usually expressed in dB.

There are two methods to verify IRR are: 1) – AC and, 2) – Transient. For AC

method two complex stimulations which represent a complex wanted signal and a

http://en.wikipedia.org/wiki/Transmission_system

http://en.wikipedia.org/wiki/Overcurrent

http://en.wikipedia.org/wiki/Signalling_(telecommunication)

http://en.wikipedia.org/wiki/Distortion

http://en.wikipedia.org/wiki/Noise_level

http://en.wikipedia.org/wiki/Image_rejection_ratio

http://en.wikipedia.org/wiki/Ratio

http://en.wikipedia.org/wiki/Frequency

http://en.wikipedia.org/wiki/Signal_level

http://en.wikipedia.org/wiki/Image_frequency

http://en.wikipedia.org/wiki/Decibel

Appendix – A

112

complex unwanted signal ‘image signal’ must be run. If the complex signal path

suppress frequency components with negative frequencies, then the positive

frequencies with two AC sources is simulated first.

First –

Positive Frequency Stimulation (phasor rotates anti-clockwise)

Mag 1.0 Phase 0.0 for the in-phase component (signal name “I”)

Mag 1.0 Phase 90.0 for the quadrature-phase component (signal name “Q”)

Second –

Negative Frequency Stimulation (phasor rotates clockwise)

Mag 1.0 Phase 0.0 for the in-phase component (signal name “I”)

Mag 1.0 Phase -90.0 for the quadrature-phase component (signal name “Q”)

This give the frequency response for the positive and negative frequencies, where

negative is typically the image. The difference of the gain obtained for two signals at

central frequency will give the IRR at the central frequency for that filter.

For transient method of verification the process is same except that I=cosx,

Q=sinx for positive and vice-versa for the negative frequencies.

THIRD ORDER INTERCEPT POINT

Third order intercept point (IP3 or TOI) or Input third order intercept point

(IIP3) is based on the concept that the device linearity can be modeled using a low-

order polynomial, derived by Taylor Series expansion. The third-order intercept point

relates nonlinear products caused by the third-order nonlinear term to the linearly

amplified signal. Since the IIP3 is a mathematical concept and does not correspond to

a practical system, in many cases it lies far beyond the damage threshold of the

device.

IP3 can be defined in two ways –

Spurious Free Dynamic Range

113

In the harmonics based method the device is tested using a single input tone

and the non-linearity products caused by nth

order nonlinearity appear at n

times the frequency of the input tone.

The Second method is based on Inter-modulation products, in this method the

device is fed with two sine tone with a small frequency difference. The nth

order inter-modulation products then appear at n-times the frequency spacing

of the input tones. This method is used to measure the IIP3 for the complex

filter design in this research work. To measure IIP3 in cadence a two tone PSS

analysis is done.

SPURIOUS FREE DYNAMIC RANGE

Spurious free dynamic range is the strength ratio of the fundamental signal to

the strongest spurious signal in the output. It is an important specification to define

dynamic performance of a device/signal generator. In an ideal situation the frequency

domain of a pure analog signal has all power concentrated at the desired frequency.

However the real situation is not so, in real case due to the noise and the non-linearity

of the components, even the best signal generators generate contents at harmonics of

the desired frequency. SFDR specifies the relationship between the amplitude of the

fundamental frequency being generated and the amplitude of the most prominent

harmonic. SFDR is usually measured with respect to the carrier frequency amplitude

in dBc. Mathematically SFDR is given as

Appendix – A

114

115

APPENDIX – B

An OTA can be utilized in various manners to facilitate various applications.

Some of these basic applications using an ideal OTA are summarized below in the

table.

Application Circuit/Symbol Comments

V/I Converter

Inverting

Voltage Gain

Non-inverting

Voltage Gain

Voltage

Summation

Integrator

Appendix – B

116

Gyrator

Ideal Current

Conveyer

(Type I)

CCII realizing

an ideal VCVS

CCII+ realizing

an NIC

117

VITA

Richa ARYA was born in Muzffarnagar, Uttar Pradesh, India in 1983. She received

her B.Sc. degree in 2003 and M.Sc. degree in 2005, both in Physics, from M.J.P.

Rohilkhand University, Bareilly, India. She has worked as a Part-time Lecturer in

Vardhman College from 2005-2007.

She has worked towards her PhD degree at the Electronics Laboratory,

Department of Physics, University of Patras since January 2010. She has held

scholarship from State Scholarship Foundation (IKY), Greece since 2010. Her current

research interests include VLSI circuits, analog filter design, Complex filters, gm-C

filter, Low voltage devices.

synthesis of low voltage integrated circuits suitable for analog signal

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