Synthesis from VHDL 1. Layout synthesis 2. logic synthesis 3. RTL synthesis 4. High Level Synthesis 5. System Synthesis Behavioral synthesis of pieces

Download Synthesis from VHDL 1. Layout synthesis 2. logic synthesis 3. RTL synthesis 4. High Level Synthesis 5. System Synthesis Behavioral synthesis of pieces

Post on 21-Dec-2015

215 views

Category:

Documents

1 download

Embed Size (px)

TRANSCRIPT

<ul><li> Slide 1 </li> <li> Synthesis from VHDL 1. Layout synthesis 2. logic synthesis 3. RTL synthesis 4. High Level Synthesis 5. System Synthesis Behavioral synthesis of pieces Behavioral synthesis of systems </li> <li> Slide 2 </li> <li> Hardware describing languages (HDL) Describe behavior not implementation Make model independent of technology Model complete systems Specification of sub-module functions Speed up simulation of large systems Standardized text format CAE tool independent </li> <li> Slide 3 </li> <li> Design entry Text: Tool independent Good for describing algorithms Bad for getting an overview of a large design </li> <li> Slide 4 </li> <li> Add-on tools Block diagrams to get overview of hierarchy Graphical description of final state machines (FSM) Generates synthesizable HDL code Flowcharts Language sensitive editors Waveform display tools From Visual HDL, Summit design </li> <li> Slide 5 </li> <li> Synthesis Algorithm Architecture Register level Gate level Logic synthesis Behavioral synthesis For i = 0 ; i = 15 sum = sum + data[I] Data[0] Data[15] i Sum Data[0]Data[15] Sum MEM Clock Clear address Clear sum 0% technology dependent 10% technology dependent 20% technology dependent 100% technology dependent </li> <li> Slide 6 </li> <li> Layout Synthesis </li> <li> Slide 7 </li> <li> Example of VHDL code for layout synthesis entity adder is port (a :in bit_vector(7 downto 0); b :in bit_vector(7 downto 0); ci :in bit; s :out bit_vector(7 downto 0); co :out bit); end adder; architecture logic of adder is signal cw, cx :bit_vector(7 downto 0); begin cw(0) </li></ul>