synplify pro user guide

Synplify Pro™

User Guide and TutorialFebruary 2001

Synplicity, Inc.935 Stewart Drive

Sunnyvale, CA 94085408.215.6000 direct

408.990.0290 faxwww.synplicity.com

http://www.synplicity.com/support/index.html

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Preface

Disclaimer of WarrantySynplicity, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this manual, and shall not be liable for any implied warranties of merchantability or fitness for a partic-ular purpose of for any indirect, special or consequential damages.

Copyright NoticeCopyright © 1994-2001 Synplicity, Inc. All Rights Reserved.

Synplicity software products contain certain confidential information of Synplicity, Inc. Use of this copyright notice is precautionary and does not imply publication or disclosure. No part of this publication may be repro-duced, transmitted, transcribed, stored in a retrieval system, or trans-lated into any language in any form by any means without the prior written permission of Synplicity, Inc. While every precaution has been taken in the preparation of this book, Synplicity, Inc. assumes no respon-sibility for errors or omissions. This publication and the features described herein are subject to change without notice.

TrademarksSynplicity, the Synplicity “S” logo, Behavior Extracting Synthesis Technology, Embedded Synthesis, HDL Analyst, SCOPE, Simply Better Results, Simply Better Synthesis, Synplify, and Synthesis Constraint Optimization Environment are registered trademarks of Synplicity, Inc.

Amplify, B.E.S.T., Certify, DST, Direct Synthesis Technology, Partition-Driven Synthesis, and Physical Optimizer are trademarks of Synplicity, Inc.

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Verilog is a registered trademark of Cadence Design Systems, Inc. IBM and PC are registered trademarks of International Business Machines Corporation. Microsoft is a registered trademark of Microsoft Corporation. Sun, SPARC, Solaris, and SunOS are trademarks of Sun Microsystems, Inc. UNIX is a registered trademark of UNIX Systems Laboratories, Inc. All other product names mentioned herein are the trademarks or registered trademarks of their respective owners.

Restricted Rights LegendGovernment Users: Use, reproduction, release, modification, or disclosure of this commercial computer software, or of any related documentation of any kind, is restricted in accordance with FAR 12.212 and DFARS 227.7202, and further restricted by the Synplicity Software License Agree-ment. Synplicity, Inc., 935 Stewart Drive, Sunnyvale, CA 94086, U.S.A

Printed in the U.S.AFebruary 2001

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Synplify Pro Software License Agreement

Important! READ CAREFULLY BEFORE PROCEEDING

This is a legal agreement between you, the user (“Licensee”) and Synplicity, Inc. (“Synplicity”) regarding the software program that is attached to or enclosed with this software license agreement, or that is the subject of this documentation (the “SOFTWARE”). The term “SOFTWARE” also includes related documentation (whether in print or electronic form) and, if Licensee is obtaining an update, any pre-existing software and data provided within earlier software releases (to the extent such earlier software and data is retained by, embodied in or in any way used or accessed by the upgraded SOFTWARE provided with this Agreement). If Licensee is a participant in the University Program or has been granted an Evaluation License, then some of the following terms and conditions may not apply (refer to the sections entitled, respectively, Evaluation License and University Program, below). By opening the packaging of the SOFTWARE, or by installing or using the SOFTWARE, Licensee agrees to be bound by the terms of this Software License Agreement (the “Agreement”). If Licensee does not agree to the terms of this Agreement, then do not install the SOFTWARE and return the copy of the SOFTWARE to the place from which you obtained it. Evaluation License. The following applies, in addition to the other terms and conditions and as a limit on the license, if Licensee has obtained an Evaluation License. If Licensee has obtained the SOFTWARE pursuant to an evaluation license, then the following additional terms, conditions, and restrictions apply: (a) The license to the SOFTWARE terminates after 20 days (unless otherwise agreed to in writing by Synplicity); and (b) Licensee may use the SOFTWARE only for the sole purpose of tests and other evaluation to determine whether Licensee wishes to license the SOFTWARE on a commercial basis. Licensee shall not use the SOFTWARE to design any integrated circuits for production or pre-production purposes or any other commercial use including, but not limited to, for the benefit of Licensee’s customers. If Licensee breaches any of the foregoing restrictions, then Licensee shall pay to Synplicity a license fee equal to Synplicity’s standard license fee for the commercial version of the SOFTWARE. License. Synplicity grants to Licensee, a non-exclusive right to install the SOFTWARE and to use or authorize use of the SOFTWARE by up to the number of nodes for which Licensee has a license and for which Licensee has the security key(s) or authorization code(s) provided by Synplicity or its agents. All SOFTWARE must be used within the country for which the systems were licensed and at Licensee's site (contained within a one kilometer radius); however, remote use is permitted by employees who work at the site but are temporarily telecommuting to that same site from less than 50 miles away (for example, an employee who works at a home office on occasion). In addition, Synplicity grants to Licensee a non-exclusive license to copy and distribute internally the documentation portion of the SOFTWARE in support of its license to use the program portion of the SOFTWARE.

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Copy Restrictions. This SOFTWARE is protected by United States copyright laws and international treaty provisions and copying not in accordance with this Agreement is forbidden. Licensee may copy the SOFTWARE only as follows: (i) to directly support authorized use under the license and (ii) in order to make a copy of the SOFTWARE for backup purposes. Copies must include all copyright and trademark notices. Use Restrictions. This SOFTWARE is licensed to Licensee for internal use only. Licensee shall not (and shall not allow any third party to): (i) decompile, disassemble, reverse engineer or attempt to reconstruct, identify or discover any source code, underlying ideas, underlying user interface techniques or algorithms of the SOFTWARE by any means whatever, or disclose any of the foregoing; (ii) provide, lease, lend, or use the SOFTWARE for timesharing or service bureau purposes, on an application service provider basis, or otherwise circumvent the internal use restrictions; (iii) modify, incorporate into or with other software, or create a derivative work of any part of the SOFTWARE; (iv) disclose the results of any benchmarking of the SOFTWARE, or use such results for its own competing software development activities, without the prior written permission of Synplicity; or (v) attempt to circumvent any user limits, maximum gate count limits or other license, timing or use restrictions that are built into the SOFTWARE. Transfer Restrictions. Licensee shall not sublicense, transfer or assign this Agreement or any of the rights or licenses granted under this Agreement, except in the case of a merger or sale of all or substantially all of Licensee’s assets. Ownership of the SOFTWARE. Synplicity retains all right, title, and interest in the SOFTWARE (including all copies), and reserves all rights not expressly granted to Licensee. This License is not a sale of the original SOFTWARE or of any copy. Ownership of Design Techniques. “Design” means the representation of an electronic circuit or device(s), derived or created by Licensee through the use of the SOFTWARE in its various formats, including, but not limited to, equations, truth tables, schematic diagrams, textual descriptions, hardware description languages, and netlists. “Design Techniques” means the Synplicity-supplied data, circuit and logic elements, libraries, algorithms, search strategies, rule bases, and technical information incorporated in the SOFTWARE and employed in the process of creating Designs. Synplicity retains all right, title and interest in and to Design Techniques incorporated into the SOFTWARE, including all intellectual property rights embodied therein. Licensee acknowledges that Synplicity is in the business of licensing SOFTWARE which incorporates Design Techniques. Licensee agrees that in the event Licensee voluntarily discloses any design techniques to Synplicity without designating such as Licensee’s Confidential Information, Synplicity has an unrestricted, royalty-free right to incorporate those Design Techniques into its software, documentation and other products, and to sublicense third parties to use those incorporated design techniques. Protection of Confidential Information. “Confidential Information” means (i) the source code of the SOFTWARE, and any included trade secrets (including any technology, idea, algorithm or information contained in the SOFTWARE, and specifically including Design Techniques); (ii) either party’s product plans,

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designs, costs, prices and names; non-published financial information; marketing plans; business opportunities; personnel; research; development or know-how; (iii) any information designated by the disclosing party as confidential in writing or, if disclosed orally, designated as confidential at the time of disclosure and reduced to writing and given to the receiving party and designated as confidential in writing within 30 days; and (iv) the terms and conditions of this Agreement; provided, however that “Confidential Information” will not include information that: (a) is or becomes generally known or available by publication, commercial use or otherwise through no fault of the receiving party; (b) is known and has been reduced to tangible form by the receiving party at the time of disclosure and is not subject to restriction; (c) is independently developed by the receiving party without use of the disclosing party’s Confidential Information; (d) is lawfully obtained from a third party who has the right to make such disclosure; or (e) is released for publication by the disclosing party in writing. Each party will protect the other’s Confidential Information from unauthorized dissemination and use with the same degree of care that each such party uses to protect its own like information. Neither party will use the other’s Confidential Information for purposes other than those necessary to directly further the purposes of this Agreement. Neither party will disclose to third parties the other’s Confidential Information without the prior written consent of the other party. Termination. Synplicity may terminate this Agreement in the event of breach or default by Licensee. Upon termination Licensee will relinquish all rights under this Agreement, and must cease using the SOFTWARE and return or destroy all copies (and partial copies) of the SOFTWARE and documentation. Export. Licensee shall not allow the Synplicity SOFTWARE to be sent or used in any country except in compliance with applicable U. S. laws and regulations. Limited Warranty and Disclaimer. Synplicity warrants that the program portion of the SOFTWARE will perform substantially in accordance with the accompanying documentation for a period of 90 days from the date of receipt. Synplicity’s entire liability and Licensee’s exclusive remedy for a breach of the preceding limited warranties shall be, at Synplicity’s option, either (a) return of the license fee, or (b) providing a fix, patch, work-around, or replacement of the SOFTWARE that does not meet such limited warranty. In either case, Licensee must return the SOFTWARE to Synplicity with a copy of the purchase receipt or similar document. Replacements are warranted for the remainder of the original warranty period or 30 days, whichever is longer. Some states/jurisdictions do not allow limitations on duration of an implied warranty, so the above limitation may not apply. EXCEPT AS EXPRESSLY SET FORTH ABOVE, NO OTHER WARRANTIES OR CONDITIONS, EITHER EXPRESS OR IMPLIED, ARE MADE BY SYNPLICITY WITH RESPECT TO THE SOFTWARE AND THE ACCOMPANYING DOCUMENTATION (STATUTORY OR OTHERWISE), AND SYNPLICITY EXPRESSLY DISCLAIMS ALL WARRANTIES AND CONDITIONS NOT EXPRESSLY STATED HEREIN, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. SYNPLICITY DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THE SOFTWARE WILL MEET LICENSEE’S REQUIREMENTS, BE UNINTERRUPTED OR ERROR FREE, OR THAT ALL DEFECTS IN THE PROGRAM WILL BE CORRECTED. Licensee

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assumes the entire risk as to the results and performance of the SOFTWARE. Some states/jurisdictions do not allow the exclusion of implied warranties, so the above exclusion may not apply. Limitation of Liability. IN NO EVENT SHALL SYNPLICITY OR ITS AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, CONSEQUENTIAL OR INCIDENTAL DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTIONS, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OUT OF THE USE OF OR INABILITY TO USE THESE SYNPLICITY PRODUCTS, EVEN IF SYNPLICITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. In no event will Synplicity be liable to Licensee for damages in an amount greater than the fees paid for the use of the SOFTWARE. Some states/jurisdictions do not allow the limitation or exclusion of incidental or consequential damages, so the above limitations or exclusions may not apply. Intellectual Property Right Infringement. If a claim alleging infringement of an intellectual property right arises concerning the SOFTWARE (including but not limited to patent, trade secret, copyright or trademark rights), Synplicity in its sole discretion may elect to defend or settle such claim. Synplicity in the event of such a claim may also in its sole discretion elect to terminate this Agreement and all rights to use the SOFTWARE, and require the return or destruction of the SOFTWARE, with a refund of the fees paid for use of the SOFTWARE less a reasonable allowance for use and shipping. Miscellaneous. If Licensee is a corporation, partnership or similar entity, then the license to the Software that is granted under this Agreement is expressly conditioned upon acceptance by a person who is authorized to sign for and bind the entity. This Agreement is the entire agreement between Licensee and Synplicity with respect to the license to the SOFTWARE, and supersedes any previous oral or written communications or documents (including, if you are obtaining an update, any agreement that may have been included with the initial version of the Software). This Agreement is governed by the laws of the State of California, USA. This Agreement will not be governed by the U. N. Convention on Contracts for the International Sale of Goods and will not be governed by any statute based on or derived from the Uniform Computer Information Transactions Act (UCITA). If any provision of this Agreement is found to be invalid or unenforceable, it will be enforced to the extent permissible and the remainder of this Agreement will remain in full force and effect. Failure to prosecute a party’s rights with respect to a default hereunder will not constitute a waiver of the right to enforce rights with respect to the same or any other breach. Government Users. The Software contains commercial computer software and commercial computer software documentation. In accordance with FAR 12.212 and DFARS 227.7202, use, duplication or disclosure is subject to restrictions under paragraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at 252.227-7013, and further restricted by this Agreement. Synplicity, Inc., 935 Stewart Drive, Sunnyvale, CA 94085, U. S. A. University Program. The following section applies only if Licensee is a participant in Synplicity’s University Program; it does not replace the remainder of the Agreement and supersedes only those terms that directly conflict.

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University Program: License. Subject to the terms and conditions of this Agreement, Synplicity hereby grants to Licensee (a University) for the License Term (defined below), a non-exclusive license, only for purposes of course work or teaching in connection with a university-sponsored class, or for academic research either sponsored by or conducted under the auspices of Licensee, to (a) install and use the SOFTWARE, and (b) reproduce and distribute copies of the documentation included in the SOFTWARE subject only to payment for those copies (which may be based on the number of users, the number and type of copies, or both). If the SOFTWARE is licensed pursuant to a node-locked license, then the Licensee may install and use the SOFTWARE on the authorized workstations. If the SOFTWARE is licensed pursuant to a floating license, then the Licensee may install the SOFTWARE on the authorized server and use the SOFTWARE on up to the number of nodes for which Licensee has paid license fees and Synplicity has granted authorization. University Program: License Term and Termination. For purposes of the University Program, “License Term” means one year unless otherwise agreed to in writing. This Agreement will terminate at the end of the License Term, unless earlier terminated in accordance with this Agreement. University Program: License Restrictions. As Licensee, University may not (i) allow access to the SOFTWARE by any user not registered for a course or participating in an academic research project for which use of the SOFTWARE has been authorized; (ii) use the SOFTWARE to design any commercial products; or (iii) disclose the results of any benchmarking of the SOFTWARE, or use such results for its own competing software development activities, without the prior written permission of Synplicity. University Program: Technical Liaison. Licensee shall appoint a Technical Liaison who will serve as the single point of contact between Synplicity and Licensee with respect to the subject matter of this Agreement. The Technical Liaison will coordinate installation and maintenance of the SOFTWARE, communicate with Synplicity regarding license procedures, administer Licensee’s obligations under this Agreement and respond to inquiries by Synplicity related to the subject matter of this Agreement. University Program: Technical Support in North America. Unless otherwise agreed in writing, Synplicity will accept calls only from the appointed Technical Liaison. No technical support will be provided other than calls from the Technical Liaison relating to installation of the SOFTWARE. SOFTWARE upgrades may be obtained from the Synplicity Web Site. University Program: International Technical Support. Technical support is provided through Synplicity’s authorized distributors in accordance with their applicable policies. revised 02/01

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Contents

Chapter 1: IntroductionSynplify Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

About the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Supported Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Synplicity Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

The Generic FPGA Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4HDL Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Logic Optimization (Compilation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Technology Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Scope of the Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Starting the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Setting Up Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

User Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Chapter 2: Synplify Pro TutorialIntroduction to the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

The Tutorial Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Start the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

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Set up Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6Create a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6Check the Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9Resolve Source File Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10Examine the RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Altera Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Set Altera Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Set Altera Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Run Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Analyze the Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22Examine the Technology View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22Check Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24Analyze Critical Paths in the Technology View . . . . . . . . . . . . . . . . . . . . . . . 2-25

Rerun Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27Rerun Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27Check the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

Xilinx Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

Set Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30Set Xilinx Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

Run Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

Analyze the Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35Examine the Technology View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35Check Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37Analyze Critical Paths in the Technology View . . . . . . . . . . . . . . . . . . . . . . . 2-39

Rerun Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40Check the Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

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Chapter 3: Tasks and TipsThe Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Setting Up HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3Creating Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3Checking Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5Viewing and Editing Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6Crossprobing from the Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9Setting Editing Window Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Setting Up Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13Creating a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13Opening an Existing Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15Making Changes to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16Using Mixed Language Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17Setting Project View Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Setting Implementation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22Setting Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22Setting Constraint and Optimization Options . . . . . . . . . . . . . . . . . . . . . . . . . 3-25Specifying Result Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26Specifying Source Code Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

Setting Constraints with SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28Opening SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29Entering and Editing Constraints Directly in SCOPE . . . . . . . . . . . . . . . . . . . 3-30Entering Default Constraints with the Wizard . . . . . . . . . . . . . . . . . . . . . . . . . 3-33Defining Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35Setting SCOPE Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

Working in the RTL and Technology Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39Differentiating Between the Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40Opening the Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41Analyzing Your Design Graphically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42Selecting Objects in the RTL/Technology Views . . . . . . . . . . . . . . . . . . . . . . 3-42Finding Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43Traversing Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44Working with Multisheet Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49Setting Preferences from the UI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50Setting Preferences in the .ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51Managing Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53

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Crossprobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54Crossprobing within an RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . 3-55Crossprobing from the RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . 3-56Crossprobing from the Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57Crossprobing from the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60Crossprobing from the FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

Working with HDL Analyst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61Flattening Schematic Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62Filtering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64Extending Selected Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65Viewing Critical Paths in HDL Analyst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67Handling Negative Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

Checking the Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72Viewing the Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72Analyzing Results Using the Log File Reports . . . . . . . . . . . . . . . . . . . . . . . . 3-74Using the Log Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74Checking Results in the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76Handling Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

Using the Symbolic FSM Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82Choosing When to Use the FSM Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82Running the FSM Compiler on the Whole Design . . . . . . . . . . . . . . . . . . . . . 3-83Running the FSM Compiler on Individual State Machines . . . . . . . . . . . . . . . 3-85Specifying FSMs with Attributes and Directives . . . . . . . . . . . . . . . . . . . . . . . 3-87

Using the FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89Viewing FSM Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89Useful Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

Adding Attributes and Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95Adding Attributes and Directives in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95Adding Attributes and Directives in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96Adding Attributes in SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97Adding Attributes From the RTL and Technology Views . . . . . . . . . . . . . . . . 3-99

Optimizing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100Controlling Flattening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100Setting Fanout Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101

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Preventing Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102Preserving Objects from Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102Preserving Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103

Working with Multiple Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104

Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106General Optimization Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106Area Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107Timing Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

Generating Vendor-Specific Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-109

Chapter 4: Advanced TechniquesBatch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Running Batch Mode on a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2Running Batch Mode with a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Working with Tcl Scripts and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4Crossprobing from the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4Using Tcl Commands and Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4Generating a Job Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5Creating a Tcl Synthesis Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5Using Tcl Variables for Multiple Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6Running Bottom-up Synthesis with a Script . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Working with Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9When to Use Constraint Files over Source Code . . . . . . . . . . . . . . . . . . . . . . . 4-9General Tcl Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9Creating Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11Creating Constraint Files for Forward Annotation . . . . . . . . . . . . . . . . . . . . . 4-12

Defining Black Boxes for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15Instantiating Black Boxes and I/Os in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . 4-15Instantiating Black Boxes and I/Os in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 4-17Adding Black Box Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19Adding Other Black Box Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21Defining Black Boxes Using STAMP Models . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

Defining State Machines for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24Defining Verilog State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24Defining VHDL State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

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Using FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26Deciding When to Use the FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26Running the FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29Prerequisites for Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30Pipelining the Entire Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30Adding Pipelining Attributes in the Source Code . . . . . . . . . . . . . . . . . . . . . . 4-31Adding Pipelining Attributes Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34Retiming During Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35Retiming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37Retiming Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38

Inserting Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38Specifying Probes in the Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38Adding Probe Attributes Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40

Inferring RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41Inference vs. Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42Structuring RAMs for Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42Coding Altera RAMs for Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46Coding Xilinx Block RAMs for Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49Specifying RAM Implementation Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51

Classic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52

Working with Altera Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54APEX Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54FLEX Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55Instantiating LPMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55Inferencing ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56Working with Altera EABs and ESBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57Packing I/O Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58

Working with Xilinx Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59Designing for Xilinx Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59Instantiating CoreGen/PCI Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60Using Clock DLLs in Virtex Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60Packing Registers for I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62Controlling Placement with RLOCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64Instantiating Special I/O Standard Buffers for Virtex . . . . . . . . . . . . . . . . . . . 4-66Inferring Dynamic Shift Register Lookup (SRL) Tables . . . . . . . . . . . . . . . . . 4-67

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Using the Xilinx Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71Introduction to the Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71Initial Design Budgeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71Active Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80Design Files and Area Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81Synplify Pro and Amplify Modular Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86

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xvi Synplify Pro User Guide, February 2001


Chapter 1Introduction

This chapter contains an introduction to Synplify Pro, and describes the following:

• Synplify Pro on page 1-2

• The Generic FPGA Design Flow on page 1-4

• Audience on page 1-7

• Scope of the Document on page 1-7

• Starting the Software on page 1-8

• User Interface Overview on page 1-12


Chapter 1: Introduction Synplify Pro

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Synplify ProThis section briefly discusses the following topics:

• About the Software

• Supported Platforms

• Supported Standards

• Synplicity Product Family

About the SoftwareSynplify Pro� is a logic synthesis tool for FPGAs (Field Programmable Gate Arrays) and Complex PLDs (Programmable Logic Devices), developed by Synplicity® of Sunnyvale, California. Synplify Pro starts with high-level designs written in Verilog and VHDL hardware description languages (HDLs). Using proprietary Behavior Extracting Synthesis Technology (B.E.S.T.)�, the tool converts the HDL into small, high-performance, design netlists that are optimized for popular technology vendors. Option-ally, Synplify Pro can write post-synthesis VHDL and Verilog netlists that you can use for simulation to verify functionality.

Synplify Pro has the following built-in features:

• The HDL Analyst®, a graphical tool for analysis and crossprobing.

• The Synplify Pro Text Editor Window, with a language-sensitive editor for writing and editing HDL code.

• SCOPE� (Synthesis Constraint Optimization Environment�), which uses a spreadsheet-like interface to manage the timing constraints and attributes in the design.

• A symbolic FSM Compiler, which performs advanced state machine optimizations.

• The FSM Explorer, which tries different state machine optimizations before picking the best implementation.

• The FSM viewer, which lets you view the transitions in detail.

• A command line interface from which you can run TCL scripts.

1-2 Synplify Pro User Guide, February 2001


Synplify Pro Chapter 1: Introduction

Supported PlatformsSynplify Pro runs on these platforms:

• PC (Windows98/Windows 2000/NT 4.0/Windows ME)

• Sun (Sun OS 5.6 and 5.7/Solaris 2.6 and 2.7)

• HP-UX 10.20

Supported Standards• Verilog

Synplify Pro supports a synthesizable subset of Verilog95 (IEEE 1364).

• VHDL

Synplify Pro supports a synthesizable subset of VHDL93 (IEEE 1076), and the following IEEE library packages:

– std_logic_1164

– numeric_std

– numeric_bit

– std_logic_unsigned

– std_logic_signed

– std_logic_arith

Synplify Pro User Guide, February 2001 1-3


Chapter 1: Introduction The Generic FPGA Design Flow

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Synplicity Product FamilySynplicity products are based on core synthesis technology, and share a common look and feel. Synplify is the basic synthesis tool. Synplify Pro is an advanced version of Synplify, with many additional features and capabilities. You can also buy Amplify, the physical optimizer, as an option to Synplify Pro.

The Generic FPGA Design FlowThe following figure contains a generic design flow showing the typical steps a designer follows when implementing an FPGA. The shaded box shows the steps you can accomplish with Synplify Pro. This generic design flow complements the specific design flow used for the tutorial. Refer to The Tutorial Design Flow on page 2-3 for a description.

Synplify

Synplify Pro AmplifyCertify

SynthesisBoard Verification

Physical Optimization



The Generic FPGA Design Flow Chapter 1: Introduction

The following sections describe each step more fully.

HDL Design EntryThe starting point for FPGA design is to specify the logic of the FPGA circuit to be implemented. You can do this by drawing a schematic, writing an HDL description, or specifying Boolean expressions.

For Synplify Pro, design entry is the step in which you generate the input for the tool. The input must be Verilog or VHDL descriptions. Synplify Pro provides you with an environment in which you can write or edit HDL descriptions.

Logic Optimization (Compilation)This is the first stage of synthesis, in which the software restructures the original network into a set of combinational functions. In Synplify Pro, the combinational functions are represented as a Boolean network. At this point in the design process, you modify the initial logic design to optimize the area or speed of the final circuit, or both. The optimization is calcu-lated from the netlist and is independent of the target technology. It includes operations like redundancy removal and common subexpression elimination.

HDL Design Entry

Logic Optimization

Technology Mapping

Routing

Placement

FPGA Configuration

Synplify Pro



Chapter 1: Introduction The Generic FPGA Design Flow

LO

Technology MappingTechnology mapping is the second phase of optimization, in which the logic is optimized to a specific technology. During this phase, the compiled design is transformed into a circuit of optimized FPGA logic blocks. Depending on your design priorities, you might want to focus on area optimization (minimizing the total number of blocks), delay optimiza-tion (minimizing the number of logic block stages in time-critical paths), or both.

Synplify Pro uses architecture-specific mapping techniques to map the logic design. It has built-in tools to analyze critical paths, crossprobe, and check the RTL view. Synplify Pro outputs netlists in formats appropriate for the place and route tools that follow.

PlacementPlacement is the first step of the physical design process. During place-ment, the logic blocks are placed in an FPGA array. At this point, consid-erations like the total interconnect length become important.

This is the point at which Synplify Pro gives control of the design to another tool. However if you have the Amplify Physical Optimizer, you can use the results from an initial placement pass to further optimize your logic design.

RoutingRouting is the final step of the physical design process. At this stage, use the place-and-route tool to connect the placed logic blocks by assigning wire segments and choosing programmable switches.

FPGA ConfigurationIn this design phase, you configure the final FPGA chip and implement it.



Audience Chapter 1: Introduction

AudienceSynplify Pro is targeted towards the FPGA system developer. It is assumed that you are knowledgeable about the following:

• Design synthesis

• RTL

• FPGAs

• Verilog/VHDL

Scope of the DocumentThis user guide is part of a document set, and is intended for use with the other documents in the set. It concentrates on describing how to use Synplify Pro to accomplish typical tasks. This implies the following:

• The user guide only explains the options needed to do the typical tasks described in the manual. It does not describe every available command and option. For complete descriptions of all the command options and syntax, refer to the Synplify Pro Reference Manual.

• The user guide contains task-based information. For a breakdown of how information is organized, see Getting Help on page 1-11.



Chapter 1: Introduction Starting the Software

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Starting the SoftwareThis section shows you how to get started with Synplify Pro. It describes the following topics, but does not supersede the information in the instal-lation instructions about licensing and installation:

• Getting Started

• Setting Up Your License

• Getting Help

Getting Started1. If you have not already done so, install Synplify Pro according to the

installation instructions.

2. Start the software.

– If you are working on a PC, select Programs->Synplicity->Synplify Pro from the Start button.

– If you are working on a UNIX workstation, type this at the command line:

synplify_pro

The command starts the Synplify Pro synthesis tool, and opens the Project window. If you have run the software before, the window displays the previous project. For more information about the inter-face, see the Synplify Pro Reference Manual.



Starting the Software Chapter 1: Introduction

Setting Up Your LicenseThe most current and comprehensive licensing information is included in the installation instructions. This section describes how to set up node-locked licenses on the PC with the wizard. For other licensing information like trial licenses, or setting up license servers, refer to the installation instructions.

1. To enter license information,

– Select Help->License Wizard.

– Select the Edit or enter license information received from Synplicity button at the bottom of the form, and click Next.

– Follow the instructions.

2. To select a new floating license or change your current license,

– Pick Help->Preferred License Selection.

– Click on a license from the License Type list, and click Select.



Chapter 1: Introduction Starting the Software

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– To automatically start the selected license the next time you start Synplify Pro select Save as default license type at the bottom of the window.

– Click Save and restart the software.

3. For Windows 98, Windows ME, Windows NT, and Windows 2000, install the sentinel driver.

– Double click on the setupx86.exe file in the <installdrive>\Synplicity\sentinel directory.

– In the installation window that opens, click Functions (located in the upper left hand corner) to select Install Sentinel driver. A dialog box specifying the path for I386 pops up.

– Confirm that the path is correct.

– After the drive has been installed, restart the computer. You can now start Synplify Pro.



Starting the Software Chapter 1: Introduction

Getting HelpBefore you call Synplicity Support, look through the documented informa-tion. You can access the information online from the Help menu, or refer to the printed manual. The following table shows you how the information is organized.

For help with... Refer to the...

Licensing Installation Guide

Attributes and directives Synplify Pro Reference Manual

Synthesis features Synplify Pro Reference Manual

Language and syntax Synplify Pro Reference Manual

Tcl Online help (select Help->Tcl Help)

Using tool-specific features and attributes

Synplify Pro User Guide

How to... Synplify Pro User Guide, application notes on the Synplicity support web site

Flow information Synplify Pro User Guide, application notes on the Synplicity support web site



Chapter 1: Introduction User Interface Overview

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User Interface OverviewThe user interface (UI) consists of a main window, called the Project view, and specialized windows or views for different tasks. For details about each of the features, see the Synplify Pro Reference Manual. Synplify Pro gives you the choice of two UIs. It is recommended that you use the standard interface shown below and used in illustrations in the rest of the document.



User Interface Overview Chapter 1: Introduction

The other choice is shown below. In this interface, some features are only available from the menus. For information about using this interface, see Classic Interface on page 4-52.

Menu

Project View

Toolbars

Button Panel

Status Bar

TCL Script WindowView Tab Log Watch Window



Chapter 1: Introduction User Interface Overview

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Menus

Toolbars

Status

Project View

UI Buttons and Options

TCL Script Window

View Tab

Log Watch Window



Chapter 2Synplify Pro Tutorial

The tutorial shows you how to use Synplify Pro in the design process. Information is organized into these topics:

• Introduction to the Tutorial on page 2-2

• The Tutorial Design Flow on page 2-3

• Start the Software on page 2-4

• Set up Source Files on page 2-6

• Altera Flow on page 2-17

• Set Altera Constraints on page 2-17

• Run Synthesis on page 2-22

• Analyze the Synthesis Results on page 2-22

• Rerun Synthesis on page 2-27

• Xilinx Flow on page 2-29

• Set Constraints on page 2-30

• Set Xilinx Device Options on page 2-32

• Run Synthesis on page 2-35

• Analyze the Synthesis Results on page 2-35

• Rerun Synthesis on page 2-40


Chapter 2: Synplify Pro Tutorial Introduction to the Tutorial

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Introduction to the TutorialThis tutorial is designed to walk you through some typical tasks and familiarize you with the user interface, but it does not cover all the possible tasks you could do. For additional information, refer to the following sources:

The tutorial design is an eight-bit micro controller. After completing this tutorial, you will be familiar with the tool and able to apply the knowledge you gained to your own, more complicated designs.

This tutorial assumes that you have

• Installed the software correctly

• Obtained the necessary licenses

If you need help with these issues, refer to the installation instructions.

For information about... See...

Installation information The installation instructions

Information about the interface Synplify Pro Reference Manual

Common tasks not covered in the tutorial

Chapter 3, Tasks and Tips

Advanced techniques Chapter 4, Advanced Techniques

Detailed information about the commands and syntax

Synplify Pro Reference Manual



The Tutorial Design Flow Chapter 2: Synplify Pro Tutorial

The Tutorial Design FlowThis flow diagram graphically illustrates the procedures demonstrated in this tutorial:

Set up Source Files

Set Constraints

Run

Start Software

Analyze

Implement FPGA

Set Options

Source files

Technology parameters

Rerun



Chapter 2: Synplify Pro Tutorial Start the Software

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Start the SoftwareYou can start the software and run the tutorial from either a PC or a UNIX workstation. If your setup is different, talk to your system administrator.

1. Make sure you have installed the software and obtained a license.

2. Copy the contents of the tutorial directory to your working area. Keep the directory structure, because the tutorial is based on this structure. When you work on your own designs, you can set up the structure any way you want.

Your tutorial directory contains the following directories and files. The <technology> directories are apex and virtex, the two technologies used in this tutorial.

3. Start the software.

– If you are working on a PC, select Programs->Synplicity->Synplify Pro from the Start button.

– If you are working on a UNIX workstation, type this at the command line: synplify_pro.

tutorial

<technology>

Source Files

verilogvhdl

Source Files

<technology>

Source Files Source Files



Start the Software Chapter 2: Synplify Pro Tutorial

The command starts the synthesis tool and opens the Project Window. This figure shows the window the first time you start the software. If you have run the software before, the window displays the previous project. For more information about the interface, see the Synplify Pro Reference Manual.

Menu

Project Window

Toolbars

TCL Window Log Watch Window



Chapter 2: Synplify Pro Tutorial Set up Source Files

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Even though you do not use the Tcl window in this tutorial, you can leave it open to view status and other informational messages.

You can access common commands in different ways: through the menu, popup menus, keyboard shortcuts, and icons. Throughout this tutorial, the alternate methods are listed first and the menu command is listed at the end.

Set up Source FilesThe first step is to set up the input files for the project. A project is a design that you work on, and consists of the input files and the imple-mentation files. This section shows you how to do the following:

• Create a Project File

• Check the Source Files

• Resolve Source File Warnings

• Examine the RTL View

Create a Project FileTo run synthesis, you need a project file. So, the first step is to create a project file. A project contains the data needed for a particular design: the list of source files, the synthesis results file, and your device option settings. The following procedure shows you how to set up a project file.

1. In the window, select File -> Build Project to open a form.

2. In the Select Files to Add to Project dialog box, do the following to set the directory and project file name:

– Set the Look In: field at the top of the form to the appropriate directory: tutorial\vhdl\<technology>. If you plan to work through the Altera flow in the tutorial, select apex for the technology; if you want to work through the Xilinx flow, select virtex. The tutorial only illustrates these two technologies, but the software supports many



Set up Source Files Chapter 2: Synplify Pro Tutorial

other technologies. If you use a technology that is not covered by the tutorial, you can still follow the general flow of the tutorial but substitute parameters specific to your technology.

– Set Files of Type to HDL Files (.vhd, .v). This tutorial uses only the VHDL files. If you want to use Verilog, use the Verilog source files provided in the tutorial\verilog directory, but your results might not exactly match all the steps in this tutorial.

The next step is to add the source files to your project file.

3. Add the source files, by doing the following in the dialog box:

– Set the Look In field at the top to the <technology> folder. This tutorial uses VHDL source files. However, when you run the software on your own design, you also have the option of using Verilog source files or mixed input files.

– Set Files of Type to VHDL files (*.vhd). If you are using Verilog files, you must set this to Verilog files (*.v).

– Add the package file first. Select the const_pkg.vhd file and click the Add button on the right side of the form. The file appears in the




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text box at the bottom of the form. You do not need to add the package file first in Verilog.

– Add the other files. Click the Add All button on the right side of the form to add all the files in the directory. The text box now displays all the .vhd files.

– Click OK.

Your project window displays a newly-created project file called const_pkg with a folder called vhdl and a directory under it called rev_1, The rev_1 directory will contain the files from the first implementation of your design. Implementations are revisions of your design within the context of the synthesis software, and do not replace external source code control software and processes. Multiple implementa-tions let you modify device and synthesis options to explore design options. Each implementation has its own synthesis and device options and its own project-related files.

4. Click on the plus sign next to the vhdl folder.

You see a list of the source HDL files for the project.




5. Make sure the package file is the first file and the top-level file is the last in the list of files in the Project window. Click the top-level file (eight_bit_uc.vhd) in the text box and drag it to the end of the list of files. The order of the rest of the files does not matter.

6. Save and rename the project. Select File->Save, type tutorial as the name of the project, and click Save. The Project window reflects your changes.

If your files are not in a folder under the tutorial directory, you can set this preference by selecting the Options->Project View Options command and checking the View project files in folders box. This separates one kind of file from another in the Project view by putting them in separate folders.

Check the Source Files1. Press F7 or select Run -> Compile Only.

The software optimizes the logic using technology-independent operations, and checks for syntax and hardware-related synthesis errors. When it has compiled, you see the following changes:

– The status box at the top contains the message Done (Warnings).

– The RTL icon in the toolbar is now selectable.

– There is an exclamation mark next to the ins_decode.vhd file, which indicates a warning. Errors are more serious than warnings; warnings are more serious than notes, which are often informational.




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2. Review the warning. To see the warning, click the Warnings tab in the Tcl window. Double-click the ins_decode.vhd file in the Project view. This opens the Text Editor window, with the error highlighted in red.

@W: ins_decode.vhd(21): Map for port tris_we of componentins_decode not found

@W: eight_bit_uc.vhd(171): tris_we is not assigned a value(floating)

Resolve Source File Warnings You can edit the source files directly in the Text Editor window, which you opened by double-clicking on the file in the project window.

1. Check the warning in the ins_decode.vhd source file.

– Read the highlighted line in the source file. If you are not at the line with the warning, press F5 to go to the correct line. The TRIS_WE : out std_logic line is highlighted.

– Check the bottom of the Text Editor window for an explanation of the error: Warning: Map for port tris_we of component ins_decode notfound.

There is a discrepancy between port definitions at the component level and the top level.

2. Return to the project view and check the top-level design file.

– Close the window with the ins_decode.vhd source file.

– Double-click eight_bit_uc.vhd in the project window to open the top-level file.

– Press Ctrl-f to open the Edit->Find form.




– Type TRIS in the Find What field of the form and click Find Next. The software finds this line:

TRIS_XWE : out std_logic;

3. Correct the error by changing TRISX_WE to TRIS_WE to match the port defined in the ins_decode component.

Normally you would also check the schematic view of the design, but for the purposes of the tutorial, just correct the typing mistake.

4. Close the editing window, and click Yes in the dialog box that asks you if you want to save your changes.

5. Press F7 to recompile.

This time there are no errors, and the status box displays the message Done!

Examine the RTL ViewNow that you have compiled the design and your source files do not have any errors, you can look at an RTL schematic view of the design.

1. Click the RTL View icon from the toolbar, or select HDL Analyst -> RTL -> Hierarchical View to open the RTL view.

This view is a hierarchical, technology-independent schematic view, that is generated by the software. The RTL view has two panes: the




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left pane lists the nets and ports in the design and the right pane contains the schematic. At the top, it lists the number of sheets in the schematic.

2. To view the design, use these icons from the toolbar, or the corresponding commands from the View menu.

– Click the lens icon with a plus (+) on it, and use the Z-shaped cursor to define a rectangle for zooming in.

– Zoom into the prgrmcntr block and look at the incrementor, state machines, and large mux. Zoom into the regs block to see how the software inferred the RAM. The RTL view shows components at a high level of abstraction, so you can recognize the pieces of logic from the source code.

Zoom into this area marked by the red rectangle




– Click on the Zoom in icon again to exit zoom mode or right-click in an empty area of the RTL view. The Z-shaped cursor changes to the crosshair cursor, which indicates the default selection mode.

3. Select the Push/Pop Hierarchy icon and click on the Prgrm_Cntr block in the schematic. You see a schematic of the program counter.

Synplicity’s proprietary B.E.S.T (Behavioral Extraction Synthesis Technology) automatically detects and extracts some high-level behavioral constructs. This is different from other synthesis tools which decompose the RTL into low-level boolean primitives that have to be reconstructed into higher-level primitives at the place-and-route stage. The software extracts high-level behavior, represents it




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as an abstract (like the incrementor in the program block), and operates on this abstract.

4. Crossprobe from the Prgrm_Cntr schematic to the source code.

– Zoom in and find the incrementor symbol . Click the Zoom icon again to get out of zoom mode, and then double-click the

RTL View

RTL View after you push into the hierarchy

Incrementor symbol




incrementor symbol. The software displays the corresponding RTL code. Close the source file window when you are done.

– Click the Push/Pop Hierarchy icon and then click in a blank area of the view (you see an arrow pointing upwards) to return to the top level.

5. To crossprobe from the source code to the schematic, double-click the alu.vhd file in the Project view. This opens the source file.

– Select the Push/Pop Hierarchy icon and click the ALU block in the RTL view. You see a schematic of the ALU function.

– Select the entire bitdecoder definition in the source file. You can use Ctrl-f to find the definition, which begins with this code: BITDECODER <= “00000001”.




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– If necessary, select the Sheet icon to move to the correct sheet of the ALU schematic. You might not need to do this, depending on the settings in your .ini file.

6. Close the source code window and return to the top-level schematic view. You can iconize the RTL view, but do not close it.

The rest of the tutorial varies slightly, depending on the technology you use. So, if you are working with Altera technology, go to Altera Flow on page 2-17 for the next step. If you are working with Xilinx technology, go to Xilinx Flow on page 2-29 for the next step. If you do not use either of these vendors, you can follow the methodology used in either of these flows and substitute device options specific to your vendor.

Select this definition in the source code to see these components highlighted in the RTL view of the ALU block.



Altera Flow Chapter 2: Synplify Pro Tutorial

Altera FlowThe Altera design flow in this tutorial uses APEX technology. The following sections show you how to

• Set Altera Constraints

• Set Altera Device Options

• Run Synthesis

• Analyze the Synthesis Results

• Rerun Synthesis

To work through the tutorial with the Xilinx design flow, see Xilinx Flow on page 2-29. If you do not use Altera or Xilinx, you can still follow along with the tutorial, using device options specific to your vendor.

Set Altera ConstraintsDesign constraints are optional, but most designers use them to define the frequency goals and describe the environment around the design. For designs without aggressive timing goals, you can just set the clock period.

You can set constraints in a text file that you can create with any text editor, but it is easier to use SCOPE (Synthesis Constraint Optimization Environment). SCOPE provides an easy-to-use spreadsheet interface for entering constraints.

The tutorial design uses basic constraints, which you enter as follows:

1. Start SCOPE in the open project window by doing one of the following:

– Clicking the Constraint file (SCOPE) icon in the toolbar.

– Selecting File - >New… Constraint file (SCOPE).



Chapter 2: Synplify Pro Tutorial Set Altera Constraints

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The Initialize New Constraints dialog box opens.

2. Click Initialize.

The SCOPE window opens, with the most common constraints, clock frequency and input/output delays, initialized.

3. Do the following to set a clock frequency constraint:

– Select the Clocks tab at the bottom, if it is not already selected.

– Click the box in the Enabled column to enable the clock constraint.

– Enter 65 in the Value column to set the global frequency value.

4. To set input/output delay constraints,

– Click the Inputs/Outputs tab.

– Enable the <input default> and <output default> by clicking the respective boxes.



Set Altera Constraints Chapter 2: Synplify Pro Tutorial

– Set a value of 5 ns for each of them.

5. Save the constraint file by clicking the icon, or by selecting File -> Save.

6. Select Yes in the dialog box that asks you if you want to add the file to the project.

You should now have the following files in the project:

– A vhdl folder that contains the source files

– A constraint folder with the constraint file (tutorial.sdc)

– An implementation folder (rev_1)

Now that you have your files set up, you can set the device options and run synthesis.



Chapter 2: Synplify Pro Tutorial Set Altera Device Options

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Set Altera Device OptionsAt this point, you set the device options for the first implementation (rev_1).

1. Select rev_1, and click the Impl Options button on the left side of the project window, click the current device options listed just under the Synplify Pro banner, or select Project -> Implementation Options.

The dialog box that opens lists the implementation (rev_1) at the top. It has five sections, and opens with the Device section options (the technology parameters) displayed.

2. In the Device section,

– Set Technology to Altera APEX20KC. The software supports a large selection of target technologies. The software has specific algorithms for optimizing each technology for best results.

– Leave the other defaults (Part at EP20K100C Speed at -7 and Package at TC144). The dialog box should look like this:

3. Click the Options/Constraints tab at the top, and set the following:

– Leave the default optimization switches (Symbolic FSM Compiler and Resource Sharing).



Set Altera Device Options Chapter 2: Synplify Pro Tutorial

– Make sure the constraint file is checked.

The settings on this tab and the Implementation Results tab look like this:

4. Click the Implementation Results tab, and check the Write Vendor Constraint File option is checked. Leave the other defaults.

5. Do not make any changes on the VHDL tab. Click OK.

You have already specified the top-level module in the project window by putting it last in the list. If you had not done that, you would specify the top-level module in the VHDL tab.

You have now set all the device options and can run synthesis.



Chapter 2: Synplify Pro Tutorial Run Synthesis

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Run Synthesis1. Make sure you have the prerequisites for synthesis:

– Source files

– Target technology (device options)

– An optional constraint file

2. Click the Run button to start synthesis.

The software goes through two synthesis phases, compilation and mapping. It reflects these stages in the Status box in the upper right of the project window. Compilation is the creation of a technology-independent boolean structure, and mapping is the technology-specific optimization of the boolean structure. You can see the results of compilation in the RTL view and the results after mapping in the Technology view.

You can now go on to analyze your results and check timing.

Analyze the Synthesis ResultsAfter you have run synthesis, you can analyze the results. This section shows you how to

• Examine the Technology View

• Check Timing

• Analyze Critical Paths in the Technology View

Examine the Technology View1. To see the graphical results of your run, click the icon to open

the Technology view.



Analyze the Synthesis Results Chapter 2: Synplify Pro Tutorial

The Technology view contains a schematic of the design after technology mapping, with base cells that are directly mapped to the target technology.

2. Zoom into one of the technology-specific components, like the ATOMs. You can pick any component.

– In the Hierarchy Browser on the left side of the Technology view, click the symbol for one of the components. The schematic in the Technology view moves to the correct sheet and you see the component highlighted in red. The actual number of sheets in the schematic vary, depending on the preference set in your .ini file.

– Select the Zoom icon from the toolbar and click the cursor on the highlighted component to zoom in and see details. Your tutorial design may not be implemented with the component shown in this example because of ongoing optimizations to the technology and the synthesis software.

– If the component was on another schematic sheet, return to the original sheet by pressing Ctrl-s or holding down the right mouse button in the Technology view and selecting View Sheets from the popup menu. Select the original sheet number from the list



Chapter 2: Synplify Pro Tutorial Analyze the Synthesis Results

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(probably Sheet 1), and click OK. Click in an empty area of the schematic to deselect the component.

– Alternatively, click F12 or click the right mouse button and select Filter Schematic from the menu. You see another Technology view, with just the component you selected. Close this view.

Check TimingYou can check timing results in the log file and in the log watch window. The latter is a quick way to view just the essentials.

1. Check the essential timing parameters in the log watch window.

– Select View -> Log Watch Window to open a window where you can quickly see the essential information, presented in a spreadsheet format.

– Position the cursor in the first cell in the Log Parameter column, and hold down the left mouse button.

– Select Estimated Frequency from the popup list. The software displays the corresponding value.

– Repeat the previous two steps in to set the Requested Frequency, Slack and I/O ATOMs. You can see that the design does not meet timing because it has a negative slack time. Positive or 0 slack times indicate that you have met or are under the timing constraint. Close the log watch window.

The following figure shows the values in the log watch window. The values you get when you run the tutorial might vary slightly, because of the ongoing optimization of the synthesis tool.




2. To see further details, look at the log file (eight_bit_uc.srr) by selecting the View Log button from the left side of the Project window. You see a window with the log file.

– In the log file window, scroll down to the Performance Summary section. You see details of the clock information. Scroll a little further to see the detailed critical path.

– Close the log file window. You can now check the critical path in the Technology view.

Analyze Critical Paths in the Technology View1. First, flatten the hierarchical schematic. Either hold down the right

mouse button in the Technology view and select Flatten Current Schematic, or select HDL Analyst -> Technology -> Flattened View. You see another Technology view window, with more schematic sheets.

2. To view the critical path, do the following in the flattened view:

– Select the Critical Path icon , or select Show Critical Path from the popup menu. The critical path is highlighted.

– If you do not see anything highlighted, page through the schematic to view the critical path. Use Shift+ right arrow, or select the command from the HDL Analyst menu. You see the critical path logic highlighted in red. Zoom in to see the details.




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– Position your cursor over one of the highlighted objects. A tooltip lists the delay and slack. The Technology view shows that the start and end points of the critical path correlate with the information you saw previously in the log file.

– To see the corresponding RTL code, double-click on a highlighted object in the Technology view.

3. Filter the critical path for further analysis.

– Make sure the critical path is still selected. If it is not, reselect the Critical Path icon.

– Either press F12, select the Filter icon, or select Filter Schematic from the HDL Analyst or popup menus. The software isolates just the gates in the critical path.

– Zoom in and examine the critical path. You can meet timing on this critical path by setting it up as a two-cycle path. You now add a multicycle path constraint and resynthesize the design. If your critical path is different from the one shown because of ongoing optimizations, you can use the method shown in Rerun Synthesis on page 2-40 to add the constraint you need. See the Synplify Pro Reference Manual for details about the constraints you can add.

4. Leave the filtered critical path view open, and close any other open Technology views.



Rerun Synthesis Chapter 2: Synplify Pro Tutorial

Rerun SynthesisThis section walks you through the post-analysis phase, where you set constraints, rerun synthesis, and check your results.

Rerun SynthesisThe critical path fails timing because it was not set up as a two-cycle path. You now add that constraint and resynthesize the design.

1. Make sure you have the filtered view of the critical path open. Click the clock icon, to deselect the objects in the filtered view.

2. Open the constraints file.

– Double-click on the constraint file (tutorial.sdc) in the Project view to open the file. The SCOPE window opens.

– Select the Multi-cycle Paths tab in SCOPE.

3. Add a constraint to the end point of the critical path. In this example, the end point is Dmux.ALUA. You can use one of these ways to add the end point.

– To drag and drop: Select one of the end points of the critical path in the filtered Technology view. You can select it directly or use Ctrl-f to find and select the object you want. If you use Ctrl-f, double-click the object you want on the Instances tab. This moves the object from the Unhighlighted to the Highlighted column, and it is selected in all open views. Drag and drop it into the Object column of the SCOPE window.

– To select in the SCOPE table: Pull down the menu in the Object column in SCOPE, and select the object you need. To do this, you must have a compiled design.

4. Set the constraints.

– For each component, set Type to to.

– Type 2 in the Value column for each of the components.



Chapter 2: Synplify Pro Tutorial Rerun Synthesis

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– Save the constraint file. If you save it as a new constraint file, you must add it to the project file. Iconify or close the SCOPE window.

5. Click the Run button to rerun synthesis.

6. Close the different windows you have open. You can now check your results.

Check the Results1. Check the results in the Log Watch window and the log file as

described previously in Check Timing on page 2-24.

The design now meets the timing requirements. The critical path has changed.

2. Check the output files in the rev_1 directory.

The software generates vendor-specific netlists with the attributes and constraints carried forward. This ensures that the design is optimized for the target technology.

The software generates vendor-specific netlists with the attributes and constraints carried forward. This ensures that the design is optimized for the target technology. You can see the following vendor-specific files.

File Description

eight_bit_uc.edf [EDIF] Netlist for P&R tools

eight_bit_uc.vm [VERILOG] Optional mapped netlist

eight_bit_uc.vhm [VHDL] Optional mapped netlist

eight_bit_uc_cons.tcl [Constraints] Constraints file for place-and-route

eight_bit_uc.vqm [VERILOG/VHDL] Result file



Xilinx Flow Chapter 2: Synplify Pro Tutorial

At this point, you have finished synthesis. The next step is to simulate waveforms or to place and route the design. You can use the tool to crossprobe and debug your designs further, or use the synthesis output files to run place-and-route.

Xilinx FlowThe Xilinx flow uses Virtex technology. The following sections show you how to

• Set Constraints

• Set Xilinx Device Options

• Run Synthesis

• Analyze the Synthesis Results

• Rerun Synthesis

To work through the tutorial with the Altera design flow, see Altera Flow on page 2-17. If you do not use Altera or Xilinx, you can follow along with the tutorial using device options specific to your vendor.



Chapter 2: Synplify Pro Tutorial Set Constraints

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Set ConstraintsDesign constraints are optional, but most designers use them to define the frequency goals and describe the environment around the design. For designs without aggressive timing goals, you can just set the clock period.

You can set constraints in a text file that you can create with any text editor, but it is easier to use SCOPE (Synthesis Constraint Optimization Environment). SCOPE provides an easy-to-use spreadsheet interface for entering constraints.

The tutorial design uses basic constraints, which you enter as follows:

1. Start SCOPE in the open project window by doing one of the following:

– Clicking the Constraint file (SCOPE) icon in the toolbar.

– Selecting File - >New… Constraint file (SCOPE).

The Initialize New Constraints dialog box opens.

2. Click Initialize.

The SCOPE window opens, with the most common constraints, clock frequency and input/output delays, initialized.

3. Do the following to set a clock frequency constraint:

– Select the Clocks tab at the bottom, if it is not already selected.

– Click the box in the Enabled column to enable the clock constraint.

– Enter 82 in the Value column to set the global frequency.



Set Constraints Chapter 2: Synplify Pro Tutorial

4. To set input/output delay constraints,

– Click the Inputs/Outputs tab.

– Enable the <input default> and <output default> by clicking the respective boxes.

– Set a value of 5 ns for each of them.

5. Save the constraint file by clicking the icon, or by selecting File - Save.

6. Select Yes in the dialog box that asks you if you want to add the file to the project.

You should now have the following files in the project:

– A vhdl folder that contains the source files

– A constraint folder with the constraint file (tutorial.sdc)

– An implementation folder (rev_1)



Chapter 2: Synplify Pro Tutorial Set Xilinx Device Options

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You can now set the device options and run synthesis.

Set Xilinx Device OptionsAt this point, you set the device options for the first implementation (rev_1).

1. Select rev_1, and click the Impl Options button in the Project window, click the current device options listed under the Synplify Pro banner, or select Project -> Implementation Options.

The dialog box that opens lists the implementation (rev_1) at the top. It has five sections, and opens with the Device section options (the technology parameters) displayed.

2. In the Device section,

– Set Technology to Xilinx Virtex. The software supports a large selection of target technologies. The software has specific algorithms for optimizing each technology for best results. For example, there are special fanout optimizations for Xilinx Virtex designs.

– Set Part to XCV300, and Speed to -5. Leave the Package field as is.



Set Xilinx Device Options Chapter 2: Synplify Pro Tutorial

– Leave the other defaults. The dialog box should look like this:

3. Click the Options/Constraints tab at the top, and set the following:

– Leave the default optimization switches (Symbolic FSM Compiler and Resource Sharing).

– Make sure the constraint file is checked.

– Leave the defaults on the Implementation Results tab.

– Click OK.



Chapter 2: Synplify Pro Tutorial Set Xilinx Device Options

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4. Click the Implementation Results tab, and make sure the Write Vendor Constraint File option is checked. Leave the other defaults.

5. Do not make any changes on the VHDL tab. Click OK.

You have already specified the top-level module in the project window by putting it last in the list. If you had not done that, you would specify the top-level module in the VHDL tab. You have now set all the device options and can run synthesis.



Run Synthesis Chapter 2: Synplify Pro Tutorial

Run Synthesis1. Make sure you have the prerequisites for synthesis:

– Source files

– Target technology (device options)

– An optional constraint file

2. Click the Run button to start synthesis.

The software goes through two synthesis phases, compilation and mapping, and it reflects these stages in the Status box in the upper right of the project window. Compilation is the creation of a technology-independent boolean structure, and mapping is the technology-specific optimization of the boolean structure. You can see the results of compilation in the RTL view and the results after mapping in the Technology view.

You might get warning messages after mapping. You can ignore these warnings.

Analyze the Synthesis ResultsAfter you have run synthesis, you can analyze the results. This section describes how to

• Examine the Technology View

• Check Timing

• Analyze Critical Paths in the Technology View

Examine the Technology View1. To see the graphical results of your run, click the icon to open

the Technology view.




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The Technology view contains a schematic of the design after technology mapping, with base cells that are directly mapped to the target technology.

2. Zoom into one of the technology-specific instances. This example shows a MUXF5, but your design may not be implemented in the same way because of ongoing optimizations to the technology and the synthesis software.

– In the Hierarchy Browser on the left side of the Technology view, click the symbol for an instance. The schematic in the Technology view moves to the correct sheet and you see the component highlighted in red. The actual sheet numbers you see might differ, depending on the preference set in your .ini file.

– Select the Zoom icon from the toolbar and click the cursor on the highlighted component to zoom in and see details.

– If the component was on another schematic sheet, return to the original sheet by pressing Ctrl-s or holding down the right mouse button in the Technology view and selecting View Sheets from the popup menu. Select the original sheet number from the list (probably Sheet 1), and click OK. Click in an empty area of the schematic to deselect the component.

– Alternatively, click F12 or click the right mouse button and select Filter Schematic from the menu. You see another Technology view, with just the object you selected. Close this view.




Check TimingYou can check timing results in the log file and in the Log Watch window. The latter is a quick way to view just the essentials.

1. Check the essential timing parameters in the log watch window.

– Select View -> Log Watch Window to open a window where you can quickly see the essential information, presented in a spreadsheet format.

– Position the cursor in the first cell in the Log Parameter column, and hold down the left mouse button.

– Select Estimated Frequency from the popup list. The software displays the corresponding value.

– Repeat the previous two steps in subsequent cells to set the Requested Frequency, and Slack. You can see that the design does not meet timing because it has a negative slack time. Positive or 0 slack times indicate that you have met or gone under the timing constraint. Close the Log Watch window.




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The following figure shows the values in the log watch window. The values you get when you run the tutorial might vary slightly, because of the ongoing optimization of the synthesis tool.

2. To see further details, look at the log file (eight_bit_uc.srr) by selecting the View Log button from the left side of the Project window. You see a window with the log file.

– In the log file window, scroll down to the Performance Summary section. You see details of the clock information. Scroll a little further to see the detailed critical path. It is the path from Dmux.ALUA to UC_ALU.ALUZ and Dmux.ALUB.

– Close the log file window. You can now check the critical path in the Technology view.




Analyze Critical Paths in the Technology View1. Open the Technology view if it is not already open.

2. The first step in analyzing the critical path is to flatten the hierarchical schematic. Either hold down the right mouse button in the Technology view and select Flatten Current Schematic, or select HDL Analyst -> Technology -> Flattened View. You see a flattened view, with more schematic sheets.

The software uses the built-in HDL Analyst tool for critical path analysis.

3. To view the critical path, do the following in the flattened view:

– Select the critical path icon , or select Show Critical Path from the popup menu. The critical path is highlighted.

– Page through the schematic to view the critical path. Use Shift+ right arrow, or select the command from the HDL Analyst menu. You see the critical path logic highlighted in red. Zoom in to see the details.

– Position your cursor over one of the highlighted objects. A tooltip lists the delay and slack. The Technology view shows that the start and end points of the critical path correlate with the information you saw previously in the log file.

– To see the corresponding RTL code, double-click on a highlighted object in the Technology view.

4. Filter the critical path for further analysis.

– Make sure the critical path is still selected.

– Either press F12, select the Filter icon, or select Filter Schematic from the HDL Analyst or popup menus. You see only the gates in the critical path.




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– Zoom in and examine the critical path. You can handle the critical path by adding a multicycle path constraint and resynthesizing the design. The start point of the path is Dmux.ALUA and the end points are UC_ALU.ALUZ and Dmux.ALUB. If you have a different critical path, you can follow the method shown here to add a different constraint.

5. Leave the filtered critical path view open, and close any other open Technology views.

Rerun SynthesisTo meet timing, you set multicycle constraints on the start and end points of the critical path. You add the constraints and resynthesize the design.

1. Make sure you have the filtered view of the critical path open. Click the clock icon, to deselect the objects in the view.

2. Open the constraints file.

– Double-click on the constraint file (tutorial.sdc) in the Project view to open the file. The SCOPE window opens.

– Select the Multi-cycle Paths tab in SCOPE.

3. Add the start point of the critical path to SCOPE. You can use one of these ways to add the start point.

– To drag and drop:

Select the start point of the critical path (Dmux.ALUA) in the filtered Technology view. You can select it directly or use Ctrl-f to find and select the object you want. If you use Ctrl-f, double-click the object you want on the Instances tab. This moves the object from the Unhighlighted to the Highlighted column, and it is selected in all open views.

Drag and drop it into the Object column of the SCOPE window.



Rerun Synthesis Chapter 2: Synplify Pro Tutorial

– To select in SCOPE:Pull down the menu in the Object column in SCOPE, and select the object you need. To do this, you must have a compiled design.

– To enter directly, type Dmux.ALUA[7:0] in the Object column in SCOPE.

4. Repeat the previous step to add the end points of the critical path to SCOPE.

5. Set the constraints.

– For the start point (Dmux.ALUA), set Type to from.

– For the end points (UC_ALU.ALUZ and Dmux.ALUB), set Type to to.

– Type 2 in the Value column for each of the components.

– Save the constraint file and add it to the project file. Iconify the SCOPE window.

6. Click the Run button to rerun synthesis. You can now check the results to see if the constraints eliminated the negative slack on the path.

Check the Results 1. Check the results in the Log Watch window and the log file.

For details, see Check Timing on page 2-37. The critical path now meets the timing requirements, and a new path is now the most critical path.

2. Close the different windows you have open.

3. Check the output files in the rev_1 directory.




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The software generates vendor-specific netlists with the attributes and constraints carried forward. This ensures that the design is optimized for the target technology. You see the following vendor-specific files.

At this point, you have finished synthesis. The next step is to simulate waveforms or to place and route the design. You can use the software to crossprobe and debug your designs further, or use the synthesis output files to run place-and-route.

File Description

eight_bit_uc.edf [EDIF] Netlist for P&R tools

eight_bit_uc.vhm [VHDL] Synthesized netlist for simulation

eight_bit_uc.vm [VERILOG] Synthesized netlist for simulation

eight_bit_uc_ncf [Constraints] Constraints for P&R tools



Chapter 3Tasks and Tips

This chapter describes typical synthesis tasks, some of which are also in the tutorial. It covers the following:

• The Design Flow on page 3-2

• Setting Up HDL Source Files on page 3-3

• Setting Up Project Files on page 3-13

• Setting Implementation Options on page 3-22

• Setting Constraints with SCOPE on page 3-28

• Working in the RTL and Technology Views on page 3-39

• Crossprobing on page 3-54

• Working with HDL Analyst on page 3-61

• Checking the Log on page 3-72

• Using the Symbolic FSM Compiler on page 3-82

• Adding Attributes and Directives on page 3-95

• Optimizing Results on page 3-100

• Preventing Optimization on page 3-102

• Design Guidelines on page 3-106

• Generating Vendor-Specific Output on page 3-109


Chapter 3: Tasks and Tips The Design Flow

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The Design FlowThe following figure shows the typical design flow using Synplify Pro. The difference between this flow and the tutorial design flow is that this flow is generic, whereas the tutorial design flow is based on specific design data.

Set up Files

Set Constraints

Run Synplify Pro

Launch the software

Analyze Results

Implement FPGA

Set Options

Source files

Vendor-specific options

Fails requirements



Setting Up HDL Source Files Chapter 3: Tasks and Tips

Setting Up HDL Source FilesWhen you synthesize a design, you need to set up two kinds of files: source HDL files that describe your design, and project files that Synplify Pro uses to manage the design. This section describes how to set up your source files; project file setup is described in Setting Up Project Files on page 3-13. Source files can be in Verilog or VHDL. For information about structuring the files for synthesis, refer to the Synplify Pro Reference Manual. This section discusses the following topics:

• Creating Source Files

• Checking Source Files

• Viewing and Editing Source Files

• Crossprobing from the Text Editor Window

• Setting Editing Window Preferences

• Useful Shortcuts

Creating Source FilesYou can use one of two languages for your source files: Verilog or VHDL. They use .v (Verilog) or .vhd (VHDL) file extensions, respectively. The files can all be the same format, or a mixture of the two. This section describes how to use the software’s built-in editor to create source files, but does not go into details of what the files contain. For details of what you can and cannot include, as well as vendor-specific information, see the Synplify Pro Reference Manual. For information about using a mixture of Verilog and VHDL input files, see Using Mixed Language Source Files on page 3-17.

1. To create a new source file using the icon, click the HDL file icon .

A blank editing window opens with line numbers on the left. You can name it now by pressing Ctrl-s and naming the file, or after you have entered some text. Go to step 3.

2. To create a new file using the menu command, do the following:

– Select File->New or press Ctrl-n.



Chapter 3: Tasks and Tips Setting Up HDL Source Files

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– In the form that opens, select the kind of source file you want to create, Verilog or VHDL.

– Type a name and location for the file.

– Click OK.

A blank editing window opens, with line numbers on the left.

3. Type the source information in the window, or cut and paste it.

In both languages, there are unsupported constructs that you must not use, constructs that Synplify Pro ignores, and vendor-specific attributes and directives that you can specify for more effective synthesis. See the Synplify Pro Reference Manual for details about the languages, and Viewing and Editing Source Files on page 3-6 for more information on working in the Editing window.

4. Save the file by selecting File->Save or the Save icon.

Once you have created a source file, you can check that you have the right syntax, as described in Checking Source Files on page 3-5.




Checking Source FilesThe software automatically checks the source files when it compiles them. This procedure shows you how to check your source code before synthesis, if you want to check the files as a separate step. There are two kinds of checks you do in Synplify Pro: syntax and synthesis.

1. Select the source files you want to check.

– To check a single file, open the file with File->Open or double-click the file in the source file list in the Project window. If you have more than one file open and want to check only one of them, make sure that the file you want to check is the active window.

– To check all the source files in a project, make sure that none of the files are active, do not select any files in the list, and go to the next step. If you have an active source file, the software only checks the active file.

For details of setting up the project file, see Setting Up Project Files on page 3-13.

2. To check the syntax, select Run->Syntax Check or press Shift+F7.

The software detects syntax errors like incorrect keywords and punctuation. It puts an exclamation mark next to files in the project list that have errors, and lists the number of warnings or notes found. If there are no errors, the Tcl Script window at the bottom of the project window displays this message:

Syntax check successful!

3. To run a synthesis check, select Run->Synthesis Check or press Shift+F8.

If there are hardware-related errors like incorrectly-coded flip-flops, the software displays an exclamation mark next to the file name in the project list and lists the number of warnings or errors it found in the file.

4. Review the errors by doing one of the following:

– Check the log file for information about the error by selecting View -> Log File.

– Look at the relevant source code by double-clicking on the file with errors.




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– Click the Error, Warning, or Note tab in the Tcl window and double-click the error.

The Editing window opens the relevant source file, and highlights the code that caused the error message. Messages can be categorized as errors, warnings or notes. Review all of them and resolve all errors. Warnings are less serious, but you must read through and under-stand them even if you do not resolve all of them. Notes are less serious, and generally contain information. For information on fixing errors, see Viewing and Editing Source Files on page 3-6.

Viewing and Editing Source FilesThe Editing window makes it easy to create your source code, view it, or edit it when you need to fix errors.

1. Do one of the following to open a source file for viewing or editing:

– To automatically open the first file in the list with errors, press Ctrl-F5.

– To open a specific file, select File->Open or press Ctrl-o and specify the source file in the dialog box. Alternatively, you can double-click on the file in the project list in the Project window to open it.

The Editing window opens and displays the source file. Lines are numbered. Keywords are in blue, and comments in green. String values are in red. If you want to change these defaults, refer to Crossprobing from the Text Editor Window on page 3-9.




2. To edit a file, type directly in the window.

This table summarizes common editing operations you might use. You can also use the shortcuts listed in Useful Shortcuts on page 3-11.

3. To create and work with bookmarks in your file, see the following table.

Bookmarks are a convenient way to navigate long files or to jump to points in the code that you refer to often. You can use the icons in the Edit toolbar for these operations. If you cannot see the Edit toolbar on the far right of your window, resize some of the other toolbars.

To... Do...

Cut, copy, paste, undo, or redo

Select the command from the popup (hold down the right mouse button to get the popup) or from the Edit menu

Go to a specific line Press Ctrl-g or select Edit->Go To, type the line number, and click OK.

Find text Press Ctrl-f or select Edit ->Find. Type the text you want to find, and click OK.

Replace text Press Ctrl-h or select Edit -> Replace. Type the text you want to find, and the text you want to replace it with. Click OK.

Complete a keyword Type enough characters to uniquely identify the keyword, and press Esc.

Indent text to the right Select the block, and press Tab.

Indent text to the left Select the block, and press Shift-Tab.

Change to upper case Select the text, and then select Edit->Advanced->Uppercase or press Ctrl-Shift-u.

Change to lower case Select the text, and then select Edit->Advanced->Lowercase or press Ctrl-u.

Add block comments Put the cursor at the beginning of the comment text, and select Edit->Advanced->Comment Code or press Alt-c.

Edit columns Press Alt, and use the left mouse button to select the column.




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4. To fix errors or review warnings in the source code, do the following:

– Go directly to the first error or warning in a file by double-clicking the file from the project list. The beginning of the line with the error is highlighted in red.

– Click on the highlighted error. At the bottom of the Editing window, you see an explanation of the error, and a suggestion for fixing it.

For example, this statement might create a warning message:

attribute syn_encoding of ALUOP_TYPE : type is "sequential";

and the associated explanation:

Warning: syn_encoding obsolete for enumerated types. Usesyn_enum_encoding.

You can fix it by editing the source code so that the line now reads:

attribute syn_enum_encoding of ALUOP_TYPE : type is "sequential";

To... Do...

Insert a bookmark Click anywhere in the line you want to bookmark. Select Edit -> Toggle Bookmarks, press Ctrl+F2, or select the first icon in the Edit toolbar.The line number is highlighted to indicate that there is a bookmark at the beginning of that line.

Delete a bookmark

Click anywhere in the line with the bookmark. Select Edit -> Toggle Bookmarks, press Ctrl+F2, or select the first icon in the Edit toolbar.The line number is no longer highlighted after the bookmark is deleted.

Delete all bookmarks

Select Edit -> Delete all Bookmarks, press Ctrl+Shift+F2, or select the last icon in the Edit toolbar.The line numbers are no longer highlighted after the bookmarks are deleted.

Navigate a file using bookmarks

Use the Next Bookmark (F2) and Previous Bookmark (Shift+F2) commands from the Edit menu or the corresponding icons from the Edit toolbar to navigate to the bookmark you want.




5. Use the following commands to navigate from one error to the next.

– To go to the next error in the same file, select Run->Next Error or press F5. To jump to the next error in another file, press Ctrl-F5.

– To navigate back to the previous error, select Run->Previous Error or press Shift+F5.

6. When you have fixed all the errors, select File -> Save or click the Save icon to save the file.

To use the file, it must be part of a project. You can add it to a project automatically when you save it. You can also add it later, as described in Making Changes to a Project on page 3-16. If it is already in a project, you can rerun synthesis.

Crossprobing from the Text Editor WindowYou can crossprobe to the Text Editor window from a number of other windows. If you double-click an object in an RTL or Technology view or a line in the TCL Script window, the software automatically opens the Text Editor window and highlights the object. To crossprobe from the FSM Viewer, you must open the Text Editor window before selecting the object in the FSM Viewer.

You can use the following method to crossprobe from any text file with objects that have the same instance names as in Synplify Pro. For example, you can crossprobe from place-and-route files.

1. To crossprobe from a text editor window to an RTL view:

– Open the RTL view.

– Select the code you want to crossprobe, and the object is highlighted in the RTL view and its Hierarchy Browser. If necessary you can right-click in the Text Editor window, and select the sheet number from the popup menu. If you select invalid text, the popup menu tells you crossprobing is not available.




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2. To crossprobe from a text editor window to a Technology view:

– Open the RTL and Technology views. You must have both views open to see the object highlighted in the Technology view when you crossprobe.

– Select the HDL code you want to crossprobe, and the object is highlighted in the RTL and Technology views. If necessary you can right-click in the Text Editor window, and select a sheet number from the popup menu. If you select invalid text, the popup menu tells you crossprobing is not available.

3. To crossprobe to an FSM Viewer window:

– Open the FSM Viewer.

– Select the state name you want to crossprobe, and the state is highlighted in the FSM Viewer.

Setting Editing Window PreferencesYou can customize the Text Editing window to display the fonts and colors you want.

1. Select Options->Text Editing Options, select the kind of text file you want to edit, and click OK.

The Text Editing window can be used for any text file, not just source files. For example, you can edit Tcl files or constraint files (.sdc). The Editor Options form opens.

2. This table shows you how to set some common syntax options:

To... Do this....

Set syntax colors Click Syntax coloring.On the Syntax Coloring form, check Use Syntax coloring.Set the colors you want for keywords, comments, quotes, and default text by clicking Foreground and Background and selecting colors from the palette. Click OK.




3. Click OK on the Editor Options form.

Useful ShortcutsThe following table summarizes command shortcuts to use when editing text or checking source files:

Define comment characters

Click Syntax coloring. On the Syntax Coloring form, type the comment start character(s) in the lower part of the form. Type the comment end characters if necessary.Click OK.

Make the text editor case-sensitive

Click Syntax coloringOn the Syntax Coloring form, check Case Sensitivity.Click OK.

Set fonts Click Fonts. On the Font form, set the font and the size,.Click OK.

Set tabs Set tab size and the display of a tab character by checking the appropriate buttons or typing a value.

Keyboard Action

Alt-c Inserts the appropriate comment character in the text file. Same as Edit->Advanced->Comment Code.

Ctrl-c Copies the selected object. Same as Edit->Copy.

Ctrl-f Finds the selected object. Same as Edit->Find.

Ctrl-F2 Toggles bookmarks on and off in a text editing window. Same as Edit->Toggle Bookmarks.

Ctrl-F4 Closes the current view. Same as File->Close, or the View symbol in the far left of the menu bar->Close.

Ctrl-F6 Displays the next view. If you are working in Workbook Mode, you see tabs for the open views. Same as the View symbol in the far left of the menu bar->Next.

Ctrl-g Jumps to the specified line in a text editing window. Same as Edit->GoTo.

To... Do this....




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Ctrl-h In a text editing window, it lets you replace text. Same as Edit-> Replace. In an RTL or Technology view, it enables crossprobing to Visual HDL. Same as HDL Analyst->Visual HDL Crossprobing-> Connect.

Ctrl-n Opens a new file. Same as File->New.

Ctrl-o Opens an existing file or project. Same as File->Open.

Ctrl-p Prints the current view. Same as File->Print.

Ctrl-Shift-F2

Deletes all bookmarks in a text editing window. Same as Edit->Delete all Bookmarks.

Ctrl-Shift-u Changes selected text to uppercase. Same as Edit->Advanced-> Uppercase.

Ctrl-u Changes selected text to lowercase. Same as Edit->Advanced-> Lowercase.

Ctrl-v Pastes the object previously copied or cut. Same as Edit->Paste.

Ctrl-x Cuts the selected objects. Same as Edit->Cut.

Ctrl-y Redoes the action you just reversed with Undo. Same as Edit->Redo.

Ctrl-z Reverses the previous action. Same as Edit->Undo.

F3 Finds the next occurrence of the text you previously specified with Find. Same as clicking the Find Again button on the Edit->Find form.

F5 Displays the next error in the source files. Same as Run->Next Error.

Shift-F5 Displays the previous error in the source files. Same as Run->Previous Error.

Shift-F7 Checks source file syntax. Same as Run->Syntax Check.

Shift-F8 Checks synthesis. Same as Run->Synthesis Check.

Keyboard Action



Setting Up Project Files Chapter 3: Tasks and Tips

Setting Up Project FilesFor a specific example on setting up a project file, refer to the tutorial in Chapter 2, Synplify Pro Tutorial. This section describes the following:

• Creating a Project File

• Opening an Existing Project File

• Making Changes to a Project

• Setting Project View Display Preferences


Creating a Project FileYou must set up a project file for each project. The easiest way to create a project file is to use the wizard. However, you can also use individual commands for each step in the process of building a project file. See Create a Project File on page 2-6 for an example.

1. Click the P icon or select File->Open Project.

2. Click Project Wizard in the first dialog box.



Chapter 3: Tasks and Tips Setting Up Project Files

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3. Click Add Files in the next dialog box. The Select Files to Add to Project dialog box opens.

4. Add the source files to the project.

– Make sure the Look in field at the top of the form points to the right directory. The files are listed in the box. If you do not see the files, check that the Files of Type field is set to display the correct file type. For Verilog files, set it to Verilog (*.v), and for VHDL files set it to VHDL (*.vhd). If you have mixed input files, follow the procedure described in Using Mixed Language Source Files on page 3-17.

– To add all the files in the directory at once, click the Add All button on the right side of the form. To add files individually, click on the file in the list and then click the Add button. Delete files from the list to be added with the Remove and Remove All buttons.

– Click OK to return to the wizard.

– Check that the last file in the list of files is the top-level source file. If it is not, select the file and use the arrows to move the file to the right position. If you do not move the top-level file to the last position now, you must explicitly specify the top-level source file when you set the device options.




– If you are using VHDL files, check file order. Package files must be first on the list because they are compiled before they are used. If you have design blocks spread over many files, make sure you have the following file order: the file containing the entity must be first, followed by the architecture file, and finally the file with the configuration. File order is not important for Verilog files.

– Click Next.

5. Type a name for the project. At this point, you can click Finish, because you have finished setting up the project file.

If you want to set the technology-specific options with the wizard, you can continue by clicking Next. For details about setting device options, see Setting Implementation Options on page 3-22.

6. To close a project file, select the Close Project button or File->Close Project.

Opening an Existing Project File1. If the project you want to open is one you worked on recently, do one

of the following:

– Click the P icon, or press the Open Project button on the left side of the Project window. In the form that opens, double-click the project you want from the list of recent projects.




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– Select File->Recent Projects-> projectName.

The project opens in the Project window.

2. To open an existing project file, do one of the following:

– Select File->Open to open the Open dialog box.

– Click the P icon, or press the Open Project button on the left side of the Project window. Press the Existing Project button to open the Open dialog box.

3. Specify the correct directory in the Look In: field.

4. Set File of Type to Project Files (*.prj). The box lists the project files.

5. Double-click on the project you want to open.

You see the project in the Project window.

Making Changes to a ProjectTypically, you might have to add files (like constraint files) to a project, delete files, or change them.

1. To add source or constraint files to a project,

– Select the Add Files button or Project->Add Source File to open the Select Files to Add to Project dialog box.

– Set the Look In: field at the top of the form to point to the right directory.

– If you need all or most of the files in the directory, click the Add All button on the right side of the form and add all the files in the directory. Delete the files you do not want with the Remove buttons.

– If you need one or two files, add files individually by clicking on the file you want to add, and then clicking Add.

– Click OK.

2. To delete a file from a project, click the file in the Project window, and press the Delete key.




3. To replace a file in a project,

– Select the file you want to change in the Project window.

– Click the Change File button, or select Project->Change File to open a form.

– In the Source File dialog box, set Look In to the directory where the new file is located. The new file must be of the same type as the file you want to replace.

– If you do not see your file listed, select the type of file you need from the Files of Type field.

– Double-click the file. The new file replaces the old one in the project list.

4. To determine how project files are saved in the project, right click on a file in the Project view and select File Options. Set the Save File option to either Relative to Project or Absolute Path.

5. To check the time stamp on a file, right click on a file in the Project view and select File Options. Check the time that the file was last modified, and then click OK.

Using Mixed Language Source FilesWith Synplify Pro, you can use a mixture of VHDL and Verilog input files if you follow this procedure. For examples of the VHDL and Verilog files, see the Synplify Pro Reference Manual.

1. If you want to organize the two formats in different folders, select the Options->Project View Options command and select the View Project Files in Folders option.

When you add the files to the project, the Verilog and VHDL files are in separate folders in the Project view.

2. When you open a project or create a new one, add the Verilog and VHDL files as follows:

– Select the Project->Add Source File command.

– On the form, set Files of Type to HDL Files (*.vhd, *.vhdl, *.v).




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– Select the Verilog and VHDL files you want and add them to your project. For details about adding files to a project, see Making Changes to a Project on page 3-16.

The files you added are displayed in the Project view. The following figure shows the files arranged in separate folders.




3. When you set device options (Impl Options button), specify the top-level module. For more information about setting device options, see Setting Implementation Options on page 3-22.

– If the top-level module is Verilog, click the Verilog tab and type the name of the module.

– If the top-level module is VHDL, click the VHDL tab and type the name of the module.

You must explicitly specify the top-level module, because it is the starting point from which the mapper generates a merged netlist.

4. Select the Implementation Results tab on the same form and select one output HDL format for the files generated by Synplify Pro. For more information about setting device options, see Setting Implementation Options on page 3-22.

– For a Verilog output netlist, select Write Verilog Netlist.

– For a VHDL output netlist, select Write VHDL Netlist.

– Set any other device options and click OK.

You can now synthesize your design. The software reads in the mixed formats of the source files and generates a single .srs file that is used for synthesis.




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Setting Project View Display PreferencesYou can customize the organization and display of project files.

1. Select Options->Project View Options.

The Project View Options form opens.

2. To organize different kinds of files in folders, check View Project Files in Folders.

Checking this option creates separate folders in the Project view for constraint files and source files.

View Project Files in Folders checked View Project Files in Folders not checked




3. To automatically display all the files, check Show Project Library. If this is unchecked, the Project view does not display the names of the files until you click on the plus symbol and expand the files below.

4. To open more than one implementation in the same Project view, check Allow Multiple Projects to be Opened.

5. To determine how file names are displayed, check one of the boxes in the Project File Name Display section of the form. You can choose to display the file name only, the relative path, or the absolute path.

Useful ShortcutsThe following table lists handy shortcuts to common project-level opera-tions:

Keyboard Action



Ctrl-n Opens a new project. Same as File->New.

Ctrl-o Opens an existing project. Same as File->Open.

Ctrl-p Prints the current view. Same as File->Print.

Ctrl-s In the Project View or certain dialog boxes, it saves a file. Same as File ->Save.

Ctrl-t Displays the Tcl window. Same as View->Tcl Window. The Tcl window is not available in Synplify.

Project 2

Project 1



Chapter 3: Tasks and Tips Setting Implementation Options

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Setting Implementation OptionsYou can set various global options for your synthesis run, some of them technology-specific. This section covers the global options you set with the Implementation Options command. You can override the global setting by setting individual attributes or directives. For details of vendor-specific options, or attributes and directives, see the Synplify Pro Reference Manual. This section discusses the following topics:

• Setting Device Options

• Setting Constraint and Optimization Options

• Specifying Result Options

• Specifying Source Code Options

Setting Device OptionsDevice options are part of the global options you can set for the synthesis run. They include the part selection (technology, part and speed grade) and implementation options (I/O insertion and fanouts). The options and the implementation of these options can vary from technology to technology, so check the vendor chapters of the Synplify Pro Reference Manual for information about your vendor options.



Delete Removes the selected files from the project. Same as Project->Remove Files From Project.

F1 Opens a Help window. Same as Help->Help.

F4 Adds a file to the project. Same as Project->Add Source File.

Keyboard Action



Setting Implementation Options Chapter 3: Tasks and Tips

1. Open the Options for Implementation form by clicking the Impl Options button or selecting Project->Implementation Options, and click the Device tab at the top if it is not already selected.

2. Select the technology, part, package, and speed. Available options vary, depending on the technology you choose.

3. Set the device mapping options. The options vary, depending on the technology you choose.

– If you are unsure of what an option means, click on the option to see a description in the box below. For more information about the options, refer to the Synplify Pro Reference Manual.

– To set an option, type in the value or check the box to enable it.

4. Set other options as described in Setting Constraint and Optimization Options on page 3-25, Specifying Result Options on page 3-26, and Specifying Source Code Options on page 3-27.

5. Click OK and run synthesis.

The software compiles and maps the design using the options you set.




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To set device options with a script, use the set_option Tcl command. The following table is an alphabetical list of the device options on the form mapped to the equivalent Tcl commands. Because the options are technology-based, all the options will not apply to your design. All commands begin with set_option, followed by the syntax in the column as shown. Check the Synplify Pro Reference Manual for the most comprehen-sive list of options for your vendor.

Form Option Tcl Command (set_option...)

Area delay percent (Altera, Lattice, Xilinx)

-area_delay_percent net_percentage

Cliquing (Altera) -cliquing {true/false}

Disable I/O insertion -disable_io_insertion {true/false}

Fan-in limit (Altera, Lattice) -fanin_limit max_fanin

Fanout guide (Actel, Atmel, Xilinx) -fanout_guide fanout_value

Fanout limit -fanout_limit limit

Fanout limit (hard) (Actel) -maxfan_hard {true/false}

Force GSR usage (Lucent, Xilinx) -force_gsr {true/false}

Map logic (Altera, Lattice, Xilinx) -map_logic {true/false}

Maximum terms/macrocell (Lattice, Xilinx)

-max_terms_per_macrocell max_terms

Package -package pkg_name

Part -part part_name

Soft buffers (Altera) -soft_buffers {true/false}

Speed -speed_grade speed_grade

Technology -technology keyword




Setting Constraint and Optimization OptionsConstraint and optimization options are part of the global options you can set for the run. This section tells you how to set options like frequency and global optimization options like resource sharing. You can also set some of these options with the appropriate buttons on the UI.

1. Open the Options for Implementation form by clicking the Impl Options button or selecting Project->Implementation Options, and click the Options/Constraints tab at the top.

2. Click the optimization options you want, either on the form or on the left panel. Your choices vary, depending on the technology. If an option is not available for your technology, it is grayed out. Setting the option in one place automatically updates it in the other.

The equivalent Tcl set_option command options are -resource_sharing, -use_fsm_explorer, -pipe, -retiming and -symbolic_fsm_compiler.

3. Specify the constraints you want to use.

– Specify the frequency. The equivalent Tcl command is set_option-frequency frequency_value.

– If you do not want to use a constraint file that is in the project, click off the checkbox next to the file name. You can not set this in the left panel of the project view.

Implementation Options Form Button Panel of Project View




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4. Set other options as described in Setting Device Options on page 3-22, Specifying Result Options on page 3-26, and Specifying Source Code Options on page 3-27.



Specifying Result OptionsThis section shows you how to specify criteria for the output of the synthesis run.

1. Open the Options for Implementation form by clicking the Impl Options button or selecting Project->Implementation Options, and click the Implementation Results tab at the top.

2. Specify the output files you want to generate.

Implementation Options Form Button Panel of Project View




– To generate mapped netlist files, click Write Mapped Verilog Netlist or Write Mapped VHDL Netlist.

– To generate a vendor-specific constraint file for forward annotation, click Write Vendor Constraint File. See Creating Constraint Files for Forward Annotation on page 4-12 for more information.

3. Set the directory to which you want to write the results.

4. Set the format for the output file. The equivalent Tcl command for scripting is project -result_format format.

You might also want to set attributes to control name-mapping. For details, refer to the appropriate vendor chapter in the Synplify Pro Reference Manual.

5. Set other options as described in Setting Device Options on page 3-22, Setting Constraint and Optimization Options on page 3-25, and Specifying Source Code Options on page 3-27.



Specifying Source Code OptionsThis section shows you how to specify the top-level design and set the default encoding style for enumerated types from the Implementation Options form.

1. Open the Options for Implementation form by clicking the Impl Options button or selecting Project->Implementation Options, and click the VHDL or Verilog tabs at the top. If you are working with a mixed language design, you see both language tabs.

2. To specify the top-level design file, type in the name of the file. Leave it blank if you have already made the top-level file the last source file in the project list. For mixed language designs, you must specify the top-level design file.

The equivalent Tcl command for scripting is set_option -top_module {Verilog_module | VHDL_entity | VHDL_entity.arch}.



Chapter 3: Tasks and Tips Setting Constraints with SCOPE

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3. In VHDL files, select a style to set a default encoding style for enumerated types.

4. Set other options as described in Setting Device Options on page 3-22, Setting Constraint and Optimization Options on page 3-25, and Specifying Result Options on page 3-26.



Setting Constraints with SCOPEYou can use a text editor to create a constraint file as described in Working with Constraint Files on page 4-9, but it is easier to use the SCOPE (Synthesis Constraint Optimization Environment) feature, which provides a spreadsheet-like interface. SCOPE is good for editing most constraints, but there are some constraints (like black box constraints) which can only be entered as directives in the source files. If you want to use a text editor to edit a constraint file, close SCOPE before editing the file, or you will overwrite results.

This section describes the following:

• Opening SCOPE on page 3-29

• Entering and Editing Constraints Directly in SCOPE on page 3-30

• Entering Default Constraints with the Wizard on page 3-33

• Defining Clocks on page 3-35

• Setting SCOPE Display Preferences on page 3-38

You can also use SCOPE to add attributes. For more information, see Adding Attributes in SCOPE on page 3-97.



Setting Constraints with SCOPE Chapter 3: Tasks and Tips

Opening SCOPETo work with SCOPE, you must have a compiled design so that SCOPE can access the design structure. You can still use SCOPE with an uncom-piled design, but you have to type in entries manually because SCOPE has no knowledge of the design.

1. To create a new constraint file,

– Compile the design. If you do not compile the design, you can still use SCOPE, but you can not automatically initialize the clocks and I/O ports.

– Start SCOPE in the open project window by doing one of the following: clicking the SCOPE icon in the toolbar , pressing Ctrl-n, or selecting File -> New.

– Specify Constraint File as the type of file to open.

– In the Initialize New Constraint File dialog box, set the constraints you want and click Initialize. If you started with a compiled design, setting these options automatically initializes the Clock, Clock to Clock Edges, and Inputs/Outputs tabs with the appropriate signals.




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An empty SCOPE window opens with a spreadsheet format. The tabs along the bottom list the different kinds of constraints you can add. For each kind of constraint, the columns contain specific data.

You can now enter constraints directly or with the wizard. Refer to Entering and Editing Constraints Directly in SCOPE on page 3-30 or Entering Default Constraints with the Wizard on page 3-33.

2. To open an existing file, do one of the following:

– Double-click the file from the project window.

– Press Ctrl-o or select File->Open. In the dialog box, set the kind of file you want to open to Constraint Files (SCOPE) (*.sdc), and double-click to select the file from the list.

The SCOPE window opens with the file you specified. For details about editing the file, see Entering and Editing Constraints Directly in SCOPE on page 3-30. If you want to edit the Tcl file directly, see Working with Constraint Files on page 4-9.

Entering and Editing Constraints Directly in SCOPEThe direct method is best suited for editing and entering individual constraints. If you are setting many constraints or defaults, use the wizard, as described in Entering Default Constraints with the Wizard on page 3-33. You might want to use the wizard to enter default constraints because the wizard provides and easy way to set them, and then use the direct method to modify, add, or delete constraints.

1. Click the appropriate tab at the bottom of the window to enter the kind of constraint you want to create:




The SCOPE window displays columns appropriate to the kind of constraint you picked. You can now enter constraints using the wizard, or work directly in the SCOPE window.

2. Enter or edit constraints as follows:

– For object or attribute cells in the spreadsheet, click in the cell and select from the pull-down list of available choices.

– For cells with values, type in the value.

To define... Click...

Clock frequency for a clock signal output of clock divider logicA specific clock frequency that overrides the global frequency

Clock

Maximum allowable delays between flip-flops in different clock domainsFalse paths between clock domains that can be ignoredClock domains with asymmetric duty cycles

Clock to Clock

Input/output delays that model your FPGA input /output interface with the outside environment

Inputs/Outputs

Constraints for paths feeding into/out of registers Registers

Paths that require multiple clock cycles Multi-cycle paths

Paths to ignore for timing analysis (false paths) False Paths

Design attributes like syn_reference_clock Attributes

Place and route tool constraintsOther constraints not used by Synplify Pro, but passed to other tools. For example, multiple clock cycles from a register or input pin to a register or output pin

Other




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– Click the check box in the Enabled column to enable the constraint.

– Make sure you have entered all the essential information for that constraint. Scroll horizontally to check. For example, to set a clock constraint in the Clocks tab, you must fill out Enabled, Clock, Value, and Units. The other columns are optional.

This table summarizes the essential steps for different SCOPE constraints:

Constraint (Tab) Minimum required to set the constraint

Clock Select the clock (Clock).Type a frequency value (Value).Check the Enabled box.

Clock to Clock Select the first clock (Clock1) and the edge (Rise or Fall).Select the second clock (Clock2) and the edge (Rise/Fall).Type the shortest time between the first edge condition and the next occurrence of the other edge (Value).Check the Enabled box.

Inputs/Outputs Select the port (Port).Select the type of delay, input or output (Type).Type a delay value (Value).Check the Enabled box.

Registers Select the register (Register).Select the type of delay, input or output (Type).Type a delay value (Value).Check the Enabled box.

Multi-cycle paths Select the port or register (Port/Register)Select the multicycle constraint (Type).Type the number of clock cycles (Value).Check the Enabled box.

False Paths Select the port or register (Port/Register)Select the kind of constraint (Type).Check the Enabled box.

Attributes Select the object (Object).Set the attribute (Attribute) and its value (Value).Check the Enabled box.

Other Type the TCL command for the constraint (Command).Enter the arguments for the command (Arguments).Check the Enabled box.




3. For common editing operations in SCOPE, consult this table:

4. Save the file by clicking the Save icon and naming the file.

The software creates a TCL constraint file (*.sdc). See Working with Constraint Files on page 4-9 for information about the commands in this file.

5. To apply the constraints to your design, you must add the file to the project now or later.

– Add it immediately by clicking Yes in the prompt box that opens after you save the constraint file

– Add it later, following the procedure for adding a file described in Making Changes to a Project on page 3-16.

Entering Default Constraints with the WizardThe wizard is best for entering a number of constraints or setting defaults. To edit or set individual constraints, or create constraints in the Other tab, work directly in SCOPE. See Entering and Editing Constraints Directly in SCOPE on page 3-30. The following procedure shows you two methods to enter defaults. The quick method, in step 1, is only appropriate for certain kinds of constraints. The rest of the steps show you how to use the wizard to enter other SCOPE constraints.

1. To quickly generate defaults in the Clocks, Clock to Clock, or Inputs/Outputs tabs, follow these steps. This method does not work for other constraints.

To... Do...

Cut, copy, paste, undo, or redo

Select the command from the popup (hold down the right mouse button to get the popup) or from the Edit menu.

Copy the same value down a column

Select Fill Down (Ctrl-d) from the Edit or popup menus.

Insert or delete rows Select Insert Row or Delete Rows from the Edit or popup menus.

Find text Select Find from the Edit or popup menus. Type the text you want to find, and click OK.




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– Click on one of the tabs, and select Edit->Insert Quick. The software lists all the objects and their types.

– Type values in the Value column. If you need the same value in a number of cells, select the column of cells with the same value, type the value in the topmost cell, and press Ctrl-d. The rest of the selected cells (in the same column) get the same value.

2. Select a tab in SCOPE and then select Edit->Insert Wizard or press Ctrl-w to start the wizard.

The wizard walks you through two dialog boxes, which vary slightly depending on the kind of constraints you want to set.

3. In the first dialog box, select the design objects to which you want to attach the constraints.

– Move objects to the selected list by either using wildcards, or highlighting objects in the unselected list and using the arrow buttons to move them.

– Click Next.

4. In the second dialog box, set defaults for the selected objects.




– Enable or disable the constraints.

– Set the default value.

– Click Finish.

When you are done, the constraints appear in the SCOPE window. To modify or add to them, do so directly in the SCOPE window (refer to Entering and Editing Constraints Directly in SCOPE on page 3-30).

5. To apply the constraints to your design, add the file to the project according to the procedure described in Making Changes to a Project on page 3-16. The constraints file has a .sdc extension. See Working with Constraint Files on page 4-9 for more information about constraint files.

Defining ClocksClock frequency is the most important timing constraint, and must be set accurately.




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1. If you have limited clock resources, define clocks that do not need a clock buffer with the syn_noclockbuf attribute attached to an individual port or to the entire module or architecture.

2. Define frequency by attaching a define_clock constraint to the clock.

– Specify the frequency as either a frequency (-freq option) or a time period (-period option).

– Specify the duty cycle for asymmetrical clocks with either the -duty_ns or duty_pct options.

The software infers all clocks, whether declared or undeclared, by tracing the clock pins of the flip-flops. However, it is recommended that you specify frequencies for all the clocks in your design. The defined frequency overrides the global frequency. Any undefined clocks default to the global frequency. The global frequency also applies to any purely combinatorial paths.

3. Define frequencies for signals other than the clocks with the syn_reference_clock attribute.

You might need to do this if your design uses an enable signal as a clocking signal because of limited clocking resources. If the enable is slower than the clock, defining the enable frequency separately instead slowing down the clock frequency ensures more accuracy. If you slow down the clock frequency, it affects all other registers driven by the clock, and can result in longer run times as the tool tries to optimize a non-critical path. To use this attribute,

– Define a dummy clock with the define_clock constraint.

– Apply the clock to the affected registers with the syn_reference_clock attribute. Use the find command to find all registers enabled by a particular signal. For example,

define_clock dummy -period 40.0define_attribute {find -reg -enable en40}

syn_reference_clock dummy

4. Define the relationship between clocks with a define_clock_delay constraint. For example, you can

– Define the maximum allowable delay between flip-flops on different clock domains.




The software only considers the edges you specified, and ignores any undefined edges. To avoid timing misconceptions, declare all four possibilities (rise to rise, fall to fall, rise to fall, and fall to rise).

– Indicate false paths (paths that can be ignored) between clock domains with the -false option.

define_clock_delay -rise CLK1 -rise CLK2 -false

– Define clock domains with asymmetric duty cycles:

define_clock clkA -period 100.0define_clock_delay -rise clkA -fall clkA 25.0define_clock_delay -fall clkA -rise clkA -75.0

The software does not check design rules, so it is best to define the relationship between clocks as completely as possible.

5. Define internal clock frequencies (clocks generated internally) with the define_clock constraint. Apply the constraint according to the source of the internal clock.

6. Define all gated clocks with the define_clock constraint.

It is recommended that you avoid using gated clocks to eliminate clock skew. If possible, move the logic to the data pin instead of using gated clocks. If you do use gated clocks, you must define them explic-itly, because the software does not propagate the frequency of clock ports to gated clocks.

To define a gated clock, attach the define_clock constraint to the clock source, as described above for internal clocks. To attach the constraint to a keepbuf (a keepbuf is a placeholder instance for clocks generated from combinatorial logic), do the following:

Source Apply define_clock to...

Register Register

Instance, like a PLL or clock DLL

Instance. If the instance has more than one clock output, apply the clock constraints to each of the output nets, making sure to use the n: prefix (to signify a net) in SCOPE.

Combinatorial logic Net. Make sure to use the n: prefix in SCOPE.




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– Attach the syn_keep attribute to the gated clock to ensure that it retains the same name through changes to the RTL code.

– Attach the define_clock constraint to the keepbuf generated for the gated clock.

7. Check the Performance Summary section of the log file for a list of all the defined and inferred clocks in the design.

Setting SCOPE Display PreferencesYou can set format and colors in the SCOPE window. The following table lists some preferences and shows you how to set them.

To... Do this...

Set the appearance of lines and buttons in the table

With a SCOPE window open, select View-> Properties.Set the display options you want on the Display Settings form. Check the Save settings to profile option if you want to settings to be the default.

Set fonts, colors, and borders for a row

Select a SCOPE row.Select Format -> Style.On the Styles form, check Save as Default if you want the new settings to be the default. Select the category you want to change (Row Header or Standard), and click Change.Set the display options you want and click OK on both forms.

Set fonts, colors, and borders for a column

Select a SCOPE row.Select Format -> Style.On the Styles form, check Save as Default if you want the new settings to be the default. Select the category you want to change (Column Header or Standard), and click Change.Set the display options you want and click OK on both forms.

Set fonts, colors, and borders for a single cell

Select a SCOPE cell.Select Format -> Cells.Set the display options you want and click OK.



Working in the RTL and Technology Views Chapter 3: Tasks and Tips

Working in the RTL and Technology ViewsThe RTL and Technology views are views that you use to analyze your design. They are part of the HDL Analyst package. This section describes general operating procedures you use in the RTL and Technology views. For information on specific tasks like analyzing critical paths, see Working with HDL Analyst on page 3-61.

The information is organized into these topics:

• Differentiating Between the Views

• Opening the Views

• Selecting Objects in the RTL/Technology Views

• Finding Objects

• Traversing Hierarchy

• Working with Multisheet Schematics

• Setting Preferences from the UI

• Setting Preferences in the .ini File

• Managing Views

Align text in columns and rows

Select a column or row in SCOPE. Select Format -> Align.Click the alignment you want and click OK.

Size columns/rows to text Select a column or row in SCOPE.Select Format -> Resize Rows or Format -> Resize Columns.

Hide/show cells Select a SCOPE cell.Select Format -> Cover Cells to hide a cell.Select Format -> Remove Covering to show a hidden cell.

To... Do this...



Chapter 3: Tasks and Tips Working in the RTL and Technology Views

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• For related information, see Crossprobing on page 3-54 and Working with HDL Analyst on page 3-61.

Differentiating Between the Views Both the RTL and Technology views are schematic views of your design that are generated by the software. The difference between them is that the RTL view is the view generated after compilation, while the Technology view is the view generated after mapping. The software creates a netlist (.srs) in the Synplicity proprietary format. The Technology view contains technology- and vendor-specific primitives, where the RTL view is technology-independent. The software creates a netlist (.srm) in the Synplicity proprietary format for this view.

The RTL view displays your design as a high-level, technology-indepen-dent schematic. In this high level of abstraction, your design is repre-sented with components like variable-width adders, registers, large muxes, other data path components, and state machines.

The Technology view is an FPGA schematic representation of your design with technology-specific primitives. It is a low-level, vendor-specific schematic view showing vendor-specific components such as look-up tables, cascade and carry chains, F and H Maps, muxes, and flip-flops.




Opening the Views

Both the RTL and the Technology views have the schematic on the right and a pane on the left that contains a hierarchical list of the objects in the design. This pane is called the Hierarchy Browser. The bar at the top of the window contains the name of the view, hierarchical level, and the number of sheets in the schematic.

1. To open the RTL view do one of the following after the design has been compiled:

– Select a hierarchical or flattened view from the HDL Analyst->RTL menu.

– Click the RTL View icon (a plus sign inside a circle).

2. To open the Technology view do one of the following after running synthesis:

Technology View

RTL View




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– Select a hierarchical or flattened view from the HDL Analyst ->Technology menu.

– From the toolbar, click the Technology View icon (the NAND gate icon).

Analyzing Your Design GraphicallyBy using B.E.S.T (Behavior Extraction Synthesis Technology) in the RTL view, the software keeps a high-level of abstraction, and makes the RTL view easy to look at and debug. High-level structures like RAMs, ROMs, operators and FSMs are kept as abstractions in this view instead of being converted to gates. You can examine the high-level structure, or push into a component and view the gate-level structure.

In the Technology view, the software uses module generators to imple-ment the high-level structures from the RTL view using technology-specific resources.

To analyze information, compare the current view with the information in the RTL/Technology view, the log file, the FSM view, and the source code. You can use techniques like crossprobing, flattening, and filtering to isolate and examine the components. The following table points you to where you can find more information about these techniques.

Selecting Objects in the RTL/Technology Views1. To select an object, click on it in the RTL or Technology schematic or

click on its name in the left pane of the view.

HDL Analyst highlights the selected object in red. Refer to Finding Objects on page 3-43 for information on locating the objects you want.

For Information About See...

Crossprobing Crossprobing on page 3-54

Isolating or filtering logic Filtering Schematics on page 3-64

Flattening Flattening Schematic Hierarchy on page 3-62

Expand filtered logic Extending Selected Logic on page 3-65




If the object you select is on another sheet of the schematic, the view tracks to the appropriate sheet. If you have other windows open, the selected object is highlighted in the other windows as well (crossprobing) but the other views do not track to the correct sheet. Selected nets that span different hierarchical levels are highlighted on all the levels. See Crossprobing on page 3-54 for more information about crossprobing.

2. To select more than one object, either

– Draw a rectangle around the objects, if they are close together.

– Select an object or a group, and then add more objects by holding down the Control key while clicking on the object to be added.

3. To select all the objects of a certain type, hold down the right mouse button and choose Select All->object from the popup menu.

4. To deselect objects, click the left mouse button in a blank area of the schematic or click the right mouse button to bring up the pop-up menu and choose Unselect All. Deselected objects are no longer highlighted.

Finding ObjectsYou can always zoom in to find an object in the schematic. This procedure shows you how to use the Hierarchy Browser in the left pane of the view and the Find command to find objects in the RTL and Technology views.

1. To find an object using your knowledge of the design hierarchy, do this in the left pane of the view: click the name of the net, port, or instance you want to select.

If the object is on a lower level of hierarchy, expand the object by clicking the plus symbol next to the higher-level object, and then click on the object you want. The selected object is highlighted in the schematic.

2. To find an object by name, select HDL Analyst->Find or press Control-f, and do the following on the form:

– Select the tab (at the top of the form) for the kind of object. You see a list of all the objects of that type in the box on the left. You can now do either of the following




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– Select the objects you want from the box on the left and click the right arrow to move the objects into the box on the right. Click OK.

– To use wildcards, type your criteria in the Highlight Wildcard field, click the arrow to move the selections to the box on the right, and click OK.

Selected objects are highlighted in red in your schematic window. The Find command works on the same level of hierarchy and does not search the hierarchy.

Traversing HierarchySchematics generally have a certain amount of design hierarchy. The software has two methods for traversing design hierarchy: the Hierarchy Browser in the left pane of the view, and Push/Pop mode. For additional information, see Working with HDL Analyst on page 3-61.

Using the Hierarchy BrowserThe Hierarchy Browser is the list of objects on the left side of the RTL and Technology views. It is best used to get an overview, or when you need to browse and find an object you are unsure of. If you want to move between design levels of a particular object, the Push/Pop mode is more direct. Refer to Using Push/Pop Mode on page 3-45 for details.




The hierarchy browser allows you to traverse and select the following:

• Ports

• Internal nets

• Components and submodules

The browser lists the names of the objects and a symbol. A plus sign in a square icon indicates that there is hierarchy under that object. A minus sign indicates that the design hierarchy has been expanded. To descend the hierarchy, click on the object’s plus sign. To ascend the hierarchy, click on the minus sign.

Using Push/Pop ModePush/Pop mode is best suited for traversing through a specific hierarchy. If you want a general view, use the Hierarchy Browsers described in Using the Hierarchy Browser on page 3-44.

1. To start Push/Pop mode, do one of the following:

– Select the View -> Push/Pop Hierarchy menu item.

– Click the right mouse button and choose Push/Pop Hierarchy from the popup menu.

– From the toolbar, click the Push/Pop Hierarchy icon (two arrows pointing up and down).

– Press F2.

The cursor changes to an arrow. The arrow points in a different direc-tion, depending on the hierarchy. The status bar at the bottom of the window reports information about the objects over which you move




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your cursor, including when an object is a primitive. You cannot push into a primitive.

The status bar at the bottom of the Synplify Pro window reports information about the object currently under the cursor, including whether the object is a primitive.

2. To push (descend) into an object, click on the hierarchical object.

Down arrow (hierarchy below)

Up arrow (hierarchy above)

“x” arrow (primitive) or in blank areas




When you descend into a ROM, you can push into it one more time to see the ROM data table. The information is in a view-only text file called rom.info. Here is an example of the file:

Note: This data is for viewing only

ROM work.INS_ROM(first)-data[11:0]address width: 11data width: 12inputs:0: Addr[0]1: Addr[1]2: Addr[2]...outputs:0: data[0]1: data[1]2: data[2]data:00000000000 -> 10100000000100000000001 -> 00000110001100000000010 -> 000001100101...default -> 000000000000

Similarly, you can push into a state machine. If you push into a state machine from the RTL view, the FSM viewer opens, where you can graphically view the transitions. For more information, see Using the FSM Viewer on page 3-89. If you push into a state machine from the Technology view, you see the underlying logic.




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3. To pop (ascend) a level, move your cursor to a blank area and click.

4. To exit Push/Pop mode, do one of the following:

– Click the right mouse button in a blank area of the view.

– Deselect View->Push/Pop Hierarchy.

– Deselect the Push/Pop Hierarchy icon.

– Press F2.




Working with Multisheet SchematicsThe title bar in the RTL view or Technology view indicates how many sheets there are in that schematic. The schematic is initially opened to the first sheet. The following table summarizes common operations for navigating multisheet schematics and the different ways you can access the navigation commands.

The following figure shows the sheet connector symbols.

To View... Do one of the following...

Next sheet Select View->Next Sheet. Click the right mouse button, and select Next Sheet from the popup.Click the Next Sheet icon (arrow pointing right) Press Shift-right arrow.

Previous sheet Select View->Previous Sheet. Click the right mouse button, and choose Previous Sheet from the popup. Click the Previous Sheet icon (arrow pointing left). Press Shift-left arrow.

A specific sheet number

Select View->View Sheets, and specify the sheet number you want to view. Click the right mouse button, select View Sheets from the popup, and then specify the sheet number. Press Ctrl-s and specify the sheet number.

Selected items only

Filter the schematic as described in Flattening Schematic Hierarchy on page 3-62.

A net across sheets

Click the right mouse button on a sheet connector to open the sheet to which the net is connected. Sheet connectors are special symbols (see following figure) in the schematic for nets that span multiple sheets. If the net is connected to multiple sheets, a popup menu lets you select the sheet.

Sheet Connector Symbol Sheet Connector with Multisheet Popup Menu




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Setting Preferences from the UIYou can set font, label, and view preferences for the RTL and Technology views from the user interface. This is easier than editing the .ini file. However, to set colors, you must modify the .ini file directly, as described in Setting Preferences in the .ini File on page 3-51.

1. Select Options->Schematic Options.

2. To set general options, do the following:

Some of these options do not take effect in the current view, but are visible in the next view you open.

3. To control the display of labels, click any of the Label Options. You must enable the Show Text option to access the other label options. The following figure illustrates the label that each option controls.

To... Set...

Display the Hierarchy Browser Disable Analyst Tree

Control crossprobing from object to place-and-route text file

Allow Text Crossprobing

Determine the number of objects displayed on a sheet.

Set Schematic Partition Size. Increase the number to display more objects per sheet.

Determine the number of objects displayed on a sheet in a filtered view.

Set Filter Partition Size. Increase the number to display more objects per sheet. You cannot set this number to a value less than the Schematic Partition Size value.




4. To change the label font, click Change (on the lower right), select the font type, size, and style on the Font form, and click OK.

5. Click OK on the Schematic Options form.

The software writes the preferences you set to the .ini file, and they remain in effect until you change them.

Setting Preferences in the .ini FileYou can customize the colors used in the RTL view and Technology view schematics and specify the number of objects in a schematic sheet.

1. Edit the synplify _pro.ini file. On Windows platforms, the file is in the Windows (or Winnt) directory. On UNIX workstations, it is in your home directory ($HOME/Windows).

Show Instance Name

Show Symbol Name

Show Port Name

Show Conn Name

Show Pin Name

Show Text




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2. Adjust the RGB (red, green, blue) values in the [Schematics] section.

Here are some examples of RGB values:

0 0 0 = black255 255 255 = white255 0 0 = red200 200 200 = gray

3. To change the amount of logic displayed on a single schematic sheet, use the PartitionSize=value statement. You can also set this with the Options->Schematic Options command.

– To see your entire design on a single page, set the value to a number larger than the total number of components in the design. Remember that setting a larger value takes a longer time to display.

– To see smaller areas of your design, set the value to a lower number.

To Change... Adjust...

The default color for instances, nets, and ports SSC_DEFAULT_LINE

The highlight (selected object) color SSC_HILIT

The color for unselected objects SSC_NOSELECTED

The window background color SSC_BACKGROUND




Managing ViewsAs you work on a project, you move between many views of the design. The following guidelines help you manage the different views you have open.

1. Toggle on View->Workbook Mode.

Below the Project view, you see tabs like the following for each open view. The tab for the current view is on top. The symbols in front of the view name on the tab help identify the kind of view.

2. To bring an open view to the front, do one of the following:

– If the window is not visible, click on its tab.

– If part of the window is visible, click in any part of the window or click on the tab for the view.

If you previously minimized the view, it will be in minimized form. Double-click on it to open a minimized view.

3. To bring the next view to the front, click Ctrl-F6 in that window.

4. To close a view, press Ctrl-F4 in that window or select File->Close.

5. You can order the display of open views with the commands from the Window menu. You can cascade the views (stack them, slightly offset), or tile them horizontally or vertically.



Chapter 3: Tasks and Tips Crossprobing

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Crossprobing This section describes how to crossprobe from different views. It includes the following:

• Overview

• Crossprobing within an RTL/Technology View

• Crossprobing from the RTL/Technology View

• Crossprobing from the Text Editor Window

OverviewCrossprobing is the process of selecting an object in one view and having the object or the corresponding logic automatically highlighted in other views. Highlighting a line of text, for example, highlights the corre-sponding logic in the schematic views. Crossprobing helps you visualize where coding changes or timing constraints might help to reduce area or increase performance.

You can crossprobe between the RTL view, Technology view, the FSM Viewer, the log file, the source files, and some external text files from place-and-route tools. However, not all objects or source code crossprobe to other views, because some source code and RTL view logic is optimized away during the compilation or mapping processes.



Crossprobing Chapter 3: Tasks and Tips

Crossprobing within an RTL/Technology ViewSelecting an object name in the Hierarchy Browser highlights the object in the schematic, and vice versa.

In this example, when you select the DECODE module in the Hierarchy Browser, the DECODE module automatically is selected in the RTL view.

Item Selected Item Highlighted/Displayed

Instance in schematic (single-click) Module icon in hierarchy browser

Net in schematic Net icon in hierarchy browser

Port in schematic Port icon in hierarchy browser

Logic icon in hierarchy browser Instance in schematic

Net icon in hierarchy browser Net in schematic

Port icon in hierarchy browser Port in schematic




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Crossprobing from the RTL/Technology View1. To crossprobe from an RTL or Technology views to other open views,

select the object by clicking on it.

The software automatically highlights the object in all open views. If the open view is an RTL or Technology view, the software highlights the object in the Hierarchy Browser on the left as well as in the schematic. If the highlighted object is on another sheet of a multi-sheet schematic, the view does not automatically track to the page.

If the open view is a source file, the software tracks to the appro-priate code and highlights it. The following figure shows crossprobing between the RTL, Technology, and Text Editor (source code) views.




2. To crossprobe from the RTL or Technology view to the source file when the source file is not open, double-click on the object in the RTL or Technology view.

Double-clicking automatically opens the appropriate source code file, and highlights the appropriate code. For example, if you double-click an object in a Technology view, HDL Analyst automatically opens an editor window with the source code and highlights the code that contains the selected register.

The following table summarizes the crossprobing capability from the RTL or Technology view.

Crossprobing from the Text Editor Window1. To crossprobe from a source code window to an open RTL view, select

a part of the HDL code, right-click, and select from the popup menu. The RTL view must be open.

2. To crossprobe from a source code window to a Technology view, do the following:

– Open the RTL and Technology views. You must have both views open to see the object highlighted in the Technology view when you crossprobe.

From To... Conditions

RTL Source code

If the source code file is not open, double-click on an object to open the Text Editor window to the appropriate piece of code.If the file is already open, the software scrolls to the correct section of the code and highlights it.

RTL Technology The Technology view must be open.

RTL FSM Viewer

The FSM view must be open. You must use a onehot encoding style

Technology Source code

If the source code file is already, open, the software scrolls to the correct section of the code and highlights it. If the source code file is not open, double-click an object in the Technology view to open the source code file.

Technology RTL The RTL view must be open.




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– Select a part of the HDL code in the source code window, right-click, and select from the popup menu.

You can use this method to crossprobe from any text file with objects that have the same instance names as in Synplify Pro. For example, you can crossprobe from place-and-route files. See Example of Crossprobing a Path from a Text File on page 3-58 for a practical example of how to use crossprobing.

3. To turn off text crossprobing from the RTL and Technology views, select Options->Schematic Options and deselect the Allow Text Crossprobing box.

Example of Crossprobing a Path from a Text FileThis example selects a path in a log file and crossprobes it in the Technology view. You can use the same technique to crossprobe from other text files like place-and-route files, as long as the instance names in the text file match the instance names in the synthesis tool.

1. Open the log file, the RTL, and Technology views.

2. Select the objects in the log file.

– Select the column by pressing Alt and dragging the cursor to the end of the column.

– To select all the objects in the path, right-click and choose Select All from the popup menu. Alternatively, you can select certain objects only, as described next.

The software selects the objects in the column, and highlights the path in the open RTL and Technology views.




– To further filter the objects in the path, right-click and choose Select From from the popup menu.On the form, check the objects you want, and click OK. The corresponding objects are highlighted.

3. To isolate and view only the selected objects, do this in the Technology view: press F12, or right-click and select the Filter Schematic command from the popup menu.

You see just the selected objects.

Technology view




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Crossprobing from the Tcl Script WindowTo crossprobe from the Tcl Script window to the source code, double-click a line in the Tcl window. If you are trying to crossprobe a warning, make sure to click the Warning tab first so that you can see the warning and double-click it.

The software opens the relevant source code file and highlights the corre-sponding code. Crossprobing from the Tcl script window is useful for debugging error messages.

Crossprobing from the FSM ViewerYou can crossprobe to the FSM Viewer if you have the view open. You can crossprobe from an RTL, Technology, or source code window.

To crossprobe from the FSM Viewer, do the following:

1. Use a onehot encoding style.

With another style, the number of registers in the RTL or Technology views do not match the number of registers in the FSM Viewer. This means that you can not crossprobe from the transition table, although you can crossprobe from the bubble diagram.

2. Open the view to which you want to crossprobe (RTL, Technology), or the source code file.

3. Click the state bubble or a state in the FSM table that you want to crossprobe.

The software highlights the corresponding code or object in the open views. You can only crossprobe from a state in the FSM table if you used a onehot encoding style.



Working with HDL Analyst Chapter 3: Tasks and Tips

Working with HDL AnalystHDL Analyst is a graphical productivity tool that helps you visualize your synthesis results, and improve your devices performance and area results. HDL Analyst generates hierarchical RTL-level and technology-primitive level schematics from your VHDL and Verilog designs, and lets you crossprobe between the RTL-level and technology-level views and your HDL source code. HDL Analyst also highlights and isolates critical paths within your design so you can analyze problem areas in your design, add timing constraints and resynthesize.

This section discusses the following topics:

• Flattening Schematic Hierarchy

• Filtering Schematics

• Extending Selected Logic

• Viewing Critical Paths in HDL Analyst

• Handling Negative Slack


For additional information, see Working in the RTL and Technology Views on page 3-39 and Crossprobing on page 3-54.



Chapter 3: Tasks and Tips Working with HDL Analyst

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Flattening Schematic HierarchyYou often have to flatten the hierarchical schematics in the RTL and Technology views when you debug your design. This section describes the commands you can use to flatten and filter your design. The commands can be accessed from the HDL Analyst menu and the popup menu that opens when you hold down the right mouse button in an RTL or Technology view.

If you use the filtering and flattening commands together, you can easily isolate parts of your design for detailed debugging. The following figure shows the results of using one sequence of commands.

To Flatten... Use this command Result

An entire RTL or Technology view schematic

Flatten Current Schematic

The schematic is flattened down to generic logic cells in the RTL view. In the technology view, it is flattened down to the technology cells.

An entire Technology view schematic down to Boolean logic

Flatten Current Schematic to Gates

The Technology view displays a level below the technology cells, down to the equivalent Boolean logic.

Selected instances in a flattened Technology view down to the Boolean logic

Dissolve Selected instances

The Technology view displays a flattened view of only the chunk of logic that you selected.




Filter Schematic

Dissolve Selected Instances

Selected Instances




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Filtering SchematicsIn HDL Analyst, you can isolate selected objects in their own schematic sheet. This is very useful for analyzing portions of your design. To do this, you use the Filter Schematic command, which takes all selected objects and groups them together in one schematic, filtering or removing all other objects.

This procedure shows you how to filter your schematic:

1. Select one or more objects that you want to filter. For example, you can select the objects on a critical path.

2. Select the Filter Schematic command, using one of these methods:

– Choose HDL Analyst -> Filter Schematic.

– Click the right mouse button and choose Filter Schematic from the popup.

– Click the Filter Schematic icon (buffer gate) .

– Press F12.

You see just the objects you selected displayed. You can crossprobe from this view.

3. To return to the previous schematic view, select the Filter Schematic command again.




Extending Selected LogicWhen you have flattened your design and isolated selected instances in an HDL Analyst view, you might need to include more logic in your selected set to debug your design. The software provides commands that simplify this task; they are described in the following table. All the commands are on the HDL Analyst menu and in the popup.

Expanding Filtered Logic

To... Do this... Result

See all cells connected to a pin

Select a pin and select the Expand command.

Added logic for the cells connected to the selected pin. See Expanding Filtered Logic on page 3-65.

See all cells that are connected to a pin up to the next register

Select a pin and select the Expand to Register/Port command.

Added logic up to the next register or port for the cells connected to the selected pin. See Expanding Filtered Logic to Register/Port on page 3-66.

Select the driver of a net

Select a pin and select the Select Net Driver command.

Added logic for the net driver in the display. See Selecting the Net Driver on page 3-66.

Trace the driver across schematic sheets

Select a pin and select the Go to Net Driver command.

Changes the current view to the schematic page with the driver.

Select active cone of logic containing selected objects

Select objects and select the Expand Paths command.

Displays the input and output cones of logic for the objects. See Expanding Paths on page 3-66.




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Expanding Filtered Logic to Register/Port

Selecting the Net Driver

Expanding Paths




Viewing Critical Paths in HDL AnalystHDL Analyst makes it simple to find and examine critical paths and the relevant source code.

1. Open a Technology view after synthesis.

2. For hierarchical designs, flatten the design by selecting HDL Analyst -> Flatten Schematic.

3. Turn on critical path highlighting by selecting HDL Analyst -> Show Critical Path, and analyze the highlighted path. You can also select the Show Critical Path icon (stopwatch button) or the command from the right mouse button popup menu.

The command highlights the instances and nets in the critical paths of your design and displays timing numbers above every instance. You can analyze your critical paths from this window, or you can isolate them in their own schematic to make it easier to analyze. This figure shows you how to interpret the numbers above the instance:

4. To isolate instances with the worst-case slack time in the critical path, select HDL Analyst -> Filter Schematic. You also can select the Filter Schematic button (buffer button) or from the right mouse button pop-up menu.

This command takes all selected objects and groups them together in one schematic, removing all other objects. All the selected instances are shown, regardless of the sheet on which they were originally.

5. Use the Filter Schematic command to restore your original schematic.

out[0] (dfm7a), Delay: 12.9 ns, Slack: -10.5 ns

For combinational logic, it is the cumulative delay to the output of the instance, including the net delay of the output. For flip-flops, it is the portion of the path delay attributed to the flip flop. The delay can be associated with either the input path or output path, whichever is worse, because the flip flop is the end of one path and the start of another.

Slack time of the worst path that goes through the instance. A negative value indicates that timing has failed.




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6. View instances in the critical path that have less than the worst-case slack time:

– Determine the slack time for your design.

– Select HDL Analyst -> Set Slack Margin.

– Set a value for the slack margin, and click OK. The software subtracts this number from the slack time to get a range, and the Technology view displays the instances that fall within the range.

For example, if your slack time is -10 ns, and you set a slack margin of 4 ns, the command displays all instances with slack times between -6 ns and -10 ns. If your slack margin is 6 ns, you see all instances with slack times between -4 ns and -10 ns. To return to viewing just the instances with the worst-case slack time, enter a zero. For additional information on handling slack times, see Handling Negative Slack on page 3-68.

7. Use crossprobing to check the RTL view and the source code. Analyze the code and the schematic to determine how to address the problem. You can add more constraints or make code changes.

8. Rerun synthesis, and check your results.

HDL Analyst displays any remaining critical paths Repeat this step until none or few critical paths remain.

When you are within 5-10 percent of your desired result, place and route your design to see if you have met your goal. If so, you are done. If your vendor provides timing-driven place and route, you might improve your results further by adding timing constraints to place and route.

Handling Negative SlackPositive slack time values (greater than or equal to 0 ns) are good, while negative slack time values (less than 0 ns) indicate the design has failed timing requirements. The negative slack value indicates the amount by which the timing is off because of delays in the critical paths of your design.

The following procedure shows you how to add constraints to fix negative slack. Timing constraints can improve your design by 10% to 20%.




1. Isolate the critical path with Filter Schematic, and check the end points of the paths that are displayed. Look at the instances. Use the commands described in Flattening Schematic Hierarchy on page 3-62, Filtering Schematics on page 3-64, and Extending Selected Logic on page 3-65.

The start point can be a primary input or a flip-flop. The end point can be a primary output or a flip-flop.

2. Determine whether there is a timing exception, like a false or multicycle path. If this is the cause of the negative slack, set the appropriate timing constraint.

If there are fewer start points, pick a start point to add the constraint. If there are fewer end points, add the attribute to an end point.

3. If there are no timing exceptions and timing is within about 20% of the goal, you can use the -improve constraints to speed up the design and meet timing:

– To speed up paths from primary inputs, add the define_input_delay timing constraint to the input. Use the input name displayed in HDL Analyst as the input port name argument for the timing constraint because names can vary depending on the source code: in Verilog, the name comes from the reg register_name declaration; in VHDL, the instance name is the signal name to which you assigned values to create the register. Specify the slack value as the -improve value. If the slack time is -2.4 ns, use -improve 2.4. The software tries to optimize timing to meet this constraint.

– To speed up paths from flip-flops, add the define_reg_output_delay timing constraint to the flip-flop. Use the instance name displayed in HDL Analyst as the register name for the timing constraint. Specify the slack value as the -improve value.

– To speed up a path to a primary output, add the define_output_delay timing constraint to that output. Use the instance name displayed in HDL Analyst as the register name for the timing constraint. Specify the slack value as the -improve value.

– To speed up paths to flip-flops, add the define_reg_input_delay timing constraint on that flip-flop. Use the instance name displayed in HDL Analyst as the register name for the timing constraint. Specify the slack value as the -improve value.




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4. If your design does not meet timing by 20% or more, you might need to make structural changes. You could do this by

– Adding options like pipelining (Pipelining on page 4-29), FSM exploration (Using FSM Explorer on page 4-26), or resource sharing.

– Changing the source code.

5. Rerun synthesis and check your results.

Useful ShortcutsThe following table lists handy shortcuts to common commands you use in HDL Analyst:

Keyboard Action

Ctrl-1 Displays a scaled view of the design in the RTL or Technology views. Same as View->Normal View.

Ctrl-a Pans the view and centers it on the selected point. Same as View->Pan Center.

Ctrl-f Finds the selected object. Same as HDL Analyst->Find.



Ctrl-l Toggles the Zoom function off and on. Same as View->Zoom Lock.

Ctrl-k Enables crossprobing to windows in other tools. Same as HDL Analyst ->External Crossprobing Engaged.

Ctrl-r Expands the path to show the net driver. Same as View->Go To Net Driver.

Ctrl-g Lets you select the sheet number in a multipage schematic. Same as View->View Sheets.

Ctrl-Shift-i Selects all instances in the view. Same as View->Select all-> Instances in an RTL or Technology view.

Ctrl-Shift-p Selects all ports in the view. Same as View->Select all->Ports in an RTL or Technology view.




Ctrl-Shift-n Selects all nets in the view. Same as View->Select all->Nets in an RTL or Technology view.



d Selects the driver for the selected net. Same as Select Net Driver from the popup menu in the RTL or Technology views.

e Expands the path to include instances connected to the selected pin. Same as HDL Analyst->Expand in the RTL or Technology views.

E Expands the path from the selected pin in the selected direction to up to the next register or port. Same as HDL Analyst->Expand to Register/Port in the RTL or Technology views.

F2 Changes the RTL or Technology view to show the next hierarchical level below or above. Same as View->Push/Pop Hierarchy.

F4 Fits the entire schematic in the window. Same as View ->Full View.

F10 Pans the view in the direction you drag the cursor. Same as View->Pan.

F11 Zooms into the specified area. Same as View->Zoom In.

F12 Filters the schematic to show only the selected objects and their connectivity. Same as HDL Analyst->Filter Schematic.

i Selects instances connected to the selected net. Same as View->Select Net Instances in the RTL or Technology views.

p Shows all the logic between the selected instances. Same as HDL Analyst->Expand Paths.

Shift-F11 Zooms out of the specified area. Same as View->Zoom Out.

Shift-F5 Displays the previous error in the source files. Same as Run->Previous Error.

Shift-left arrow

Displays the previous schematic page. Same as View->Previous Sheet in an RTL or Technology view.

Shift-right arrow

Displays the next schematic page. Same as View->Next Sheet in an RTL or Technology view.

Keyboard Action



Chapter 3: Tasks and Tips Checking the Log

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Checking the Log• Viewing the Log File

• Analyzing Results Using the Log File Reports

• Handling Warnings

Viewing the Log FileThe log file contains the most comprehensive results and information about a synthesis run. If you want to check a few critical performance criteria, it is easier to use the Log Watch window described in Using the Log Watch Window on page 3-74, but if you want details, read through the log file.

1. To view the log file, select View -> Log File, or click the View Log button from the left side of the Project window. You see an Editing window with the log file.

The log files lists the compiled files, details of the synthesis run, a list of errors, warnings and notes, and a number of reports. For informa-tion about the reports, see Analyzing Results Using the Log File Reports on page 3-74.

For general information about working in an Editing window, including adding bookmarks, see Viewing and Editing Source Files on page 3-6.



Checking the Log Chapter 3: Tasks and Tips

2. To find information in the log file, select Edit -> Find or press Ctrl-f. Fill out the criteria in the form and click OK.

The following table lists places in the log file you can use when searching for information.

3. Resolve any errors and check all warnings.

You must fix errors, because you cannot synthesize a design with errors. Check the warnings and make sure you understand them. See Handling Warnings on page 3-76 for information about some common warnings. Notes are usually informational, and can be ignored. For details about crossprobing and fixing errors, see Viewing and Editing Source Files on page 3-6 and Crossprobing from the Text Editor Window on page 3-9.

4. If you are trying to find and resolve errors, you can bookmark them as shown in this procedure:

– Select Edit -> Find or press Ctrl-f.

– Type @W as the criteria on the Find form, and click Mark All. The software inserts bookmarks at every line with a warning. You can now page through the file from bookmark to bookmark using the commands in the Edit menu or the icons in the Edit toolbar. For more information on using bookmarks, see Viewing and Editing Source Files on page 3-6.

5. To crossprobe from the log file to the source code, double-click on a warning.

To find... Search for...

Notes @N

Warnings and errors @W and @E

Performance summary Performance Summary

The beginning of the timing report START TIMING REPORT

Detailed information about slack times, constraints, arrival times, etc.

Interface Information

Resource usage Resource Usage Report




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Analyzing Results Using the Log File ReportsThe log file contains technology-appropriate reports like timing reports, resource usage reports and net buffering reports.

1. To analyze timing results,

– View the Timing Report by going to the Performance Summary section of the log file.

– Check the slack times.

– Check the detailed information for the critical paths, including the setup requirements at the end of the detailed critical path description. You can crossprobe and view the information graphically and determine how to improve the timing.

2. To check buffers,

– Check the report by going to the Net Buffering Report section of the log file.

– Check the number of buffers or registers added or replicated and determine whether this fits into your design optimization strategy.

3. To check logic resources,

– Go to the Resource Usage Report section at the end of the log file.

– Check the number and types of components used to determine if you have used too much of your resources.

Using the Log Watch WindowThe Log Watch window is a more convenient viewing mechanism than the log file if you want to quickly check key performance criteria, or if you want to compare results from different runs. Its limitation is that it only displays certain criteria. If you need details, use the log file, as described in Viewing the Log File on page 3-72.

1. Open the Log Watch window if needed, by checking View -> Log Watch Window.

If you open an existing project the Log Watch window shows the parameters set the last time you opened the window.




2. Select the log parameter you want to monitor by clicking on a line and selecting a parameter from the menu.

The software automatically fills in the appropriate value from the last synthesis run. You can check the clock requested and estimated frequencies, the clock requested and estimated periods, the slack, and some resource usage criteria.

3. To compare the results of two or more synthesis runs, do the following:

– If needed, resize the Tcl Script window to get a bigger log window.

– Click the right mouse button in the window and select Configure Watch from the popup.

– Click Watch Selected Implementations, and check the implementations you want to compare, or click Watch All Implementations. Click OK. The log watch window now shows a column for each implementation you selected.

– In the log watch window, set the parameters you want to compare.

The software shows the values for the selected implementations side by side. For more information about multiple implementations, see Working with Multiple Implementations on page 3-104.




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Checking Results in the Tcl Script WindowAs you make selections in the UI, the Tcl Script window displays the corresponding Tcl commands.

1. Scroll back through the Tcl window to review the actions you took to synthesize the design.

You can easily interpret the Tcl commands. For example, if you compiled your design, the Tcl window displays project -run compile.

2. Crossprobe errors from the Tcl window:

– Click the Errors or Warnings tab to display the errors and warnings, respectively.

– Scroll through the errors and warnings or use the Next Error and Previous Error commands from the Run menu.

– Double-click the error to open the source code file with the error.

Handling WarningsThe following cases describe some warning messages you might see in your log file and discusses how you can deal with them.

Asynchronous LoadsRegister <name> with async load is being synthesized in compatibility mode. A synthesis/simulation mismatch is possible.

This message is generated when the software creates objects that are not explicitly defined in the RTL code. For example, if you have a register with an asynchronous load, the software generates a set/reset register even if this is not defined in the code. To avoid simulation mismatches, rewrite the code with explicit assignments.




Latch InferenceLatch generated from always block for signal <name>, probably caused by a missing assignment in IF or CASE statement.

You see a message like this when you have not declared all the cases in a CASE or IF statement describing purely combinatorial logic. This may be permissible in your design, but you must check to make sure. If you do not want a latch generated, make sure that you use a default clause or a Verilog full_case directive for CASE statements. Make sure you always use the else clause in IF-THEN-ELSE statements. If you require a latch, use assign statements.

Verilog Example

Original Code Revised Code

always @(posedge clk or posedge load)beginif (load)q=d0;else q=d1;end

wire tmp_set = load & d0;wire tmp_rst = load & -d0;always @(posedge clk or posedge tm_rst or posedge tmp_set)beginif (tmp_rst)q=0;else if (tmp_set)q=1;elseq=d;end

VHDL Example


process (clk, load)beginif (load = ‘1’) then )q <= d0;elsif (rising_edge(clk)) thenq <=d;end if;end

begintmp_set <= load and d0;tmp_rst <= load and not (d0);process (clk, tmp_rst, tmp_set)if (tmp_rst = ‘1’) then )q <= 0;elsif (tmp_set = ‘1’) thenq <= ’1’;elsif (rising_edge(clk)) thenq <=d;end if;end




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The software generates a latch for the following example, because there is no assignment for the case when sel2 = 11. You can fix it by adding a state-ment, as shown.

Latch generated because there is no assignment for case 11:

case sel2 iwhen "00" => mux41_out <= inp1;when "01" => mux41_out <= inp2;when "10" => mux41_out <= inp3;when others => null;end case;

No latch generated when all the cases are specified:

case sel2 iwhen "00" => mux41_out <= inp1;when "01" => mux41_out <= inp2;when "10" => mux41_out <= inp3;when "11" => mux41_out <= inp4;when others => null;end case;




Incomplete Sensitivity ListIncomplete Sensitivity List - assuming completeness. Referenced variable <name> is not in the sensitivity list.

The software generates this message if you have signals missing in the sensitivity list. The software assumes the list is complete and does not account for missing signals, so you could have a mismatch with the simulation results.

The following table shows a piece of code. In the examples on the left, the signal B is missing from the sensitivity list. When A is unchanged at 1, and B changes from 1 to 0, the code on the left is insensitive to the change and Y1 remains at 1 nand 1 or 0. However, when the code is written as shown on the right, it is sensitive to the change and the value is 1 nand 0 or 1.

Verilog Example


module nand2(A,B,Y1);input A, B;output Y1;always @(A)beginY1 = !(A & B);endendmodule

module nand2(A,B,Y1);input A, B;output Y1;always @(A or B)beginY1 = !(A & B);endendmodule

VHDL Example


process (A)beginY1 <= A nand B;end process;

process (A, B)beginY1 <= A nand B;end process;




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Unused Inputs“<design>|Input <input name> is unused.

You see this kind of message when an input is unused. You must check these warnings because the software removes any logic that does not ultimately feed a primary output.

Redundant LogicRemoving sequential element <element_name>.

During optimization, the software reduces duplicate instances, and issues a warning message like the one above. For example, if you have one instance driving four other instances, the software uses just one driver instead of four copies. Check your design and ensure that the optimiza-tion is appropriate. If you want to keep four copies of the driver, you must specify this explicitly in the code with the syn_preserve directive.




Verilog Example

Original Code Code with syn_preserve

module dff (q1, q2, q3, q4, data1, clk);output q1, q2, q3, q4;input data1, clk;reg q1, q2, q3 , q4;always @(posedge clk)begin

q1 <= data1;q2 <= data1;q3 <= data1;q4 <= data1;

endendmodule

module dff (q1, q2, q3, q4, data1, clk);output q1, q2, q3, q4;input data1, clk;reg q1 /*syn_preserve =1*/,

q2 /*syn_preserve =1*/, q3 /*syn_preserve =1*/, q4 /*syn_preserve =1*/;

always @(posedge clk)begin

q1 <= data1;q2 <= data1;q3 <= data1;q4 <= data1;

endendmodule

VHDL Example

Original Code Code with syn_preserve

entity dff isport (data1, clk : in bit;

q1, q2, q3, q4 : out bit);end dff;architecture rtl of dff is beginprocess (clk) beginif (clk ‘event and clk = ‘1’) then

q1 <= data1; q2 <=data1; q3 <= data1; q4 <= data1;

end if;end process;end rtl;

entity dff isport (data1, clk : in bit;

q1, q2, q3, q4 : out bit);attribute syn_preserve : boolean;attribute syn_preserve of q1, q2, q3,

q4 : signal is true;end dff;architecture rtl of dff is beginprocess (clk) beginif (clk ‘event and clk = ‘1’) then

q1 <= data1; q2 <=data1; q3 <= data1; q4 <= data1;




Chapter 3: Tasks and Tips Using the Symbolic FSM Compiler

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Using the Symbolic FSM CompilerThe Symbolic FSM Compiler is an advanced state machine optimizer, which automatically recognizes state machines in your design and optimizes them. Unlike other synthesis tools that treat state machines as regular logic, the FSM Compiler extracts the state machines as symbolic graphs, and then optimizes them by re-encoding the state representations and generating a better logic optimization starting point for the state machines. The FSM Explorer uses the state machines extracted by the FSM Compiler when it explores different encoding styles.

For more information, see the following topics:

• Choosing When to Use the FSM Compiler

• Running the FSM Compiler on the Whole Design

• Running the FSM Compiler on Individual State Machines

• Specifying FSMs with Attributes and Directives

Choosing When to Use the FSM CompilerThe FSM Compiler and the FSM Explorer are automatic tools for state machines, but you can also specify FSMs manually with attributes. For more information about the FSM Explorer and FSM attributes, see Using FSM Explorer on page 4-26, Adding Attributes and Directives on page 3-95 and Specifying FSMs with Attributes and Directives on page 3-87.

There are three main reasons to use the FSM Compiler:

• To generate better results for your state machines

The software uses optimization techniques that are specifically tuned for FSMs, like reachability analysis for example. The FSM Compiler also lets you convert an encoded state machine to another encoding style (to improve speed and area utilization) without changing the source. For example, you can use a onehot style to improve results.



Using the Symbolic FSM Compiler Chapter 3: Tasks and Tips

• To debug the state machines

State machine description errors result in unreachable states, so if you have errors, you will have fewer states. You can check whether your source code describes your state machines correctly. You can also use the FSM Viewer to see a high-level bubble diagram and crossprobe from there. For information about the FSM Viewer, see Using the FSM Viewer on page 3-89.

• To run the FSM Explorer

The FSM Explorer is a tool that examines all the encoding styles before selecting the best option, based on the state machine extrac-tion done by the FSM Compiler. If the FSM Compiler has not been run previously, the Explorer automatically runs it. For more informa-tion about using the FSM Explorer, see Using FSM Explorer on page 4-26.

Running the FSM Compiler on the Whole Design1. Enable the compiler by checking the Symbolic FSM Compiler box in one

of these places:

– The main panel on the left side of the project window

– The Options/Constraints tab of the dialog box that comes up when you click the New Impl or Impl Options buttons

2. To set a specific encoding style for a state machine, define the style with the syn_encoding attribute, as described in Specifying FSMs with Attributes and Directives on page 3-87.

If you do not specify a style, the FSM Compiler picks an encoding style based on the number of states.

3. Click Run to run synthesis.

The software automatically recognizes and extracts the state machines in your design, and instantiates a state machine primitive in the netlist for each FSM it extracts. It then optimizes all the state machines in the design, using techniques like reachability analysis, next state logic optimization, state machine re-encoding and propri-etary optimization algorithms. Unless you have specified encoding




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styles, it automatically selects the encoding style based on the number of states.

The FSM Compiler also writes a log file that contains a description of each state machine extracted and the set of reachable states for each state machine.

4. Select View->View Log File and check the log file for descriptions of the state machines and the set of reachable states for each one. You see text like the following:

Extracted state machine for register cur_stateState machine has 7 reachable states with original encodings of:

0000001000001000001000001000001000001000001000000

....original code -> new code

0000001 -> 00000010000010 -> 00000100000100 -> 00001000001000 -> 00010000010000 -> 00100000100000 -> 01000001000000 -> 1000000

Number of States Encoding Style

Up to 4 Sequential

5-24 Onehot

> 24 Gray




5. Check the state machine implementation in the RTL and Technology views and in the FSM viewer.

– In the RTL view you see the FSM primitive with one output for each state.

– In the Technology view, you see a level of hierarchy that contains the FSM, with the registers and logic that implement the final encoding.

– In the FSM view you see a bubble diagram and mapping information. For information about the FSM viewer, see Using the FSM Viewer on page 3-89.

– In the fsm.info text file, you see the state transition information.

Running the FSM Compiler on Individual State MachinesIf you have state machines that you do not want automatically optimized by the FSM Compiler, you can use one of these techniques, depending on the number of FSMs to be optimized. You might want to exclude state machines from automatic optimization because you want them imple-mented with a specific encoding or because you do not want them extracted as state machines. The following procedure shows you how to work with both cases.

1. If you have just a few state machines you do not want to optimize, do the following:

– Enable the FSM Compiler by checking the box in the button panel of the Project window.

– If you do not want to optimize the state machine, add the syn_state_machine directive to the registers in the Verilog or VHDL code. Set the value to 0. When synthesized, these registers are not extracted as state machines.

Verilog reg [3:0] curstate /* synthesis syn_state_machine=0 */ ;

VHDL signal curstate : state_type;attribute syn_state_machine : boolean;attribute syn_state_machine of curstate : signal is false;




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– If you want to specify a particular encoding style for a state machine, use the syn_encoding attribute, as described in Specifying FSMs with Attributes and Directives on page 3-87. When synthesized, these registers have the specified encoding style.

– Run synthesis.

The software automatically recognizes and extracts all the state machines, except the ones you marked. It optimizes the FSMs it extracted from the design, honoring the syn_encoding attribute. It writes out a log file that contains a description of each state machine extracted, and the set of reachable states for each FSM.

2. If you have many state machines you do not want optimized, do this:

– Disable the compiler by unchecking the Symbolic FSM Compiler box in one of these places: the main panel on the left side of the project window or the Options/Constraints tab of the dialog box that comes up when you click the New Impl or Impl Options buttons. This disables the compiler from optimizing any state machine in the design. You can now selectively turn on the FSM compiler for individual FSMs.

– For state machines you want the FSM Compiler to optimize automatically, add the syn_state_machine directive to the individual state registers in the VHDL or Verilog code. Set the value to 1. When synthesized, the FSM Compiler extracts these registers with the default encoding styles according to the number of states.

– For state machines with specific encoding styles, set the encoding style with the syn_encoding attribute, as described in Specifying FSMs with Attributes and Directives on page 3-87. When synthesized, these registers have the specified encoding style.

– Run synthesis.

Verilog reg [3:0] curstate /* synthesis syn_state_machine=1 */ ;

VHDL signal curstate : state_type;attribute syn_state_machine : boolean;attribute syn_state_machine of curstate : signal is true;




The software automatically recognizes and extracts only the state machines you marked. It automatically assigns encoding styles to the state machines with the syn_state_machine attribute, and honors the encoding styles set with the syn_encoding attribute. It writes out a log file that contains a description of each state machine extracted, and the set of reachable states for each state machine.

3. Check the state machine in the log file, the RTL and technology views, and the FSM viewer. For information about the FSM viewer, see Using the FSM Viewer on page 3-89.

Specifying FSMs with Attributes and DirectivesIf your design has state machines, he software can extract them automat-ically with the FSM Compiler (see Using the Symbolic FSM Compiler on page 3-82), or you can manually specify attributes to define the state machines. You attach the attributes to the state registers. The following table lists the attributes, and where you can set them. For detailed infor-mation about the attributes and their syntax, see the Synplify Pro Refer-ence Manual. For information about adding attributes, see Adding Attributes and Directives on page 3-95.

To... Attribute HDL SCOPE

Set encoding style syn_encoding Yes Yes

Specify a state machine for extraction and optimization

syn_state_machine=1 Yes No

Prevent state machines from being extracted and optimized

syn_state_machine=0 Yes No

Prevent the state machine from being optimized away

syn_preserve=1 Yes No




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The syn_encoding attribute defines an encoding style for the state machine. Both the FSM Compiler and the FSM Explorer honor this setting. The different values for this attribute are briefly described here:

• sequentialUse this value if area is important, because it is one of the smallest encoding styles. The software uses this style by default if there are less than five states. In this style, more than one bit of the state register can change at a time, so the value must be decoded to deter-mine the state. This style could be faster than a onehot style if you have a large output decoder following an FSM.

• onehotThis style is usually the fastest, and is well-suited to most FPGA architectures because it requires the least state decode logic. Speed could be an issue as FPGAs usually have a large number of flip-flops. In this style, each state variable has one bit set, and only one bit of the state register changes at a time.

• grayWith this style, only one bit of the state register changes at a time, but because more than one bit can be hot, the value must be decoded to determine the state. This style could be faster than a onehot style if you have a large output decoder following an FSM.

• safeIf recovery from an invalid state is important, use this value in conjunction with onehot, sequential, or gray, to force the state machine to reset. For example, an alpha particle hit in a hostile operating environment could cause a register to change spontaneously. When you specify safe, the state machine can be reset from an unknown state to its reset state. You specify safe before the other value.

Verilog reg [2:0] state /* synthesis syn_encoding = “safe, onehot” */;

VHDL attribute syn_encoding of state : signal is “safe, onehot”;

Tcl Constraint define_attribute {state[*]} syn_encoding {safe, onehot}



Using the FSM Viewer Chapter 3: Tasks and Tips

Using the FSM Viewer

Viewing FSM InformationThe FSM viewer displays state transition bubble diagrams for FSMs in the design, along with additional information about the FSM. You can use this viewer to view state machines implemented by either the FSM Compiler or the FSM Explorer. For more information, see Using the Symbolic FSM Compiler on page 3-82 and Using FSM Explorer on page 4-26, respectively.

1. To start the FSM viewer, open the RTL view and either

– Select the FSM instance, click the right mouse button and select View FSM from the popup menu.

– Push down into the FSM instance using the Push/Pop icon or the command from the popup menu.

The FSM viewer opens. The viewer consists of a transition bubble diagram and a table for the encodings and transitions. If you used Verilog to define the FSMs, the viewer displays binary values for the state machines if you defined them with the ‘define keyword, and actual names if you used the parameter keyword.



Chapter 3: Tasks and Tips Using the FSM Viewer

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2. The following table summarizes basic viewing operations.

This figure shows you the mapping information for a state machine. The Transitions tab shows you simple equations for conditions for each state. The RTL Encodings tab has a State column that shows the state names in the source code, and a Registers column for the corre-sponding RTL encoding. The Mapped Encoding tab shows the state names in the code mapped to actual values.

To view... Do...

From and to states, and conditions for each transition

Click the Transitions tab at the bottom of the table.

The correspondence between the states and the FSM registers in the RTL view

Click the RTL Encoding tab.

The correspondence between the states and the registers in the Technology View

Click the Mapped Encodings tab (available after synthesis).

Just the transition diagram without the table

Select View->FSM table or click the FSM Table icon. You might have to scroll to the right to see it.




3. To view just one selected state,

– Select the state by clicking on its bubble. The state is highlighted.

– Click the right mouse button and select the filtering criteria from the popup menu: output, input, or any transition.

The transition diagram now shows only the filtered states you set. The following figure shows filtered views for output and input transi-tions for one state.

States and Conditions

Mapped Encoding RTL Encoding




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Similarly, you can check the relationship between two or more states by selecting the states, filtering them, and checking their properties.

4. To view the properties for a state,

– Select the state.

– Click the right mouse button and select Properties from the popup menu. A form shows you the properties for that state.

To view the properties for the entire state machine like encoding style, number of states, and total number of transitions between states, deselect any selected states, click the right mouse button outside the diagram area, and select Properties from the popup menu.

CountCont state filtered by output transitions

CountCont state filtered by input transitions




5. To view the FSM description in text format, select the state machine in the RTL view and View FSM Info File from the right mouse popup. This is an example of the FSM Info File, statemachine.info.

State Machine: work.Control(verilog)-cur_state[6:0]No selected encoding - Synplify Pro will chooseNumber of states: 7Number of inputs: 4Inputs:

0: Laplevel1: Lap2: Start3: ResetClock: Clk

Transitions: (input, start state, destination state)-100 S0 S6--10 S0 S2---1 S0 S0-00- S0 S0--10 S1 S3-100 S1 S2-000 S1 S1---1 S1 S0--10 S2 S5-000 S2 S2-100 S2 S1---1 S2 S0-100 S3 S5-000 S3 S3--10 S3 S1---1 S3 S0-000 S4 S4--1- S4 S0-1-- S4 S0---1 S4 S0-000 S5 S5-100 S5 S4--10 S5 S2---1 S5 S01--0 S6 S6---1 S6 S00--- S6 S0




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Useful ShortcutsThe following table lists handy shortcuts to use in the FSM Viewer:

Keyboard Action

Ctrl-++ Shows only the output transitions for the selected states in an FSM bubble diagram. Same as View->Filter->Selected in the FSM viewer.

Ctrl-+- Shows only the input transitions for the selected states in an FSM bubble diagram. Same as View->Filter->Selected in the FSM viewer.

Ctrl-+* Shows all transitions for the selected states in an FSM bubble diagram. Same as View->Filter->Selected in the FSM viewer.

Ctrl-1 Displays a scaled view of the design. Same as View->Normal View.

Ctrl-Enter Shows only the selected states in an FSM bubble diagram. Same as View->Filter->Selected in the FSM viewer.



Ctrl-l Toggles the Zoom function off and on. Same as View->Zoom Lock.

Ctrl-u Shows all the states (unfilters) in an FSM bubble diagram. Same as View->Unfilter in the FSM viewer.



F4 Fits the entire diagram in the window. Same as View ->Full View.

F10 Pans the view in the direction you drag the cursor. Same as View->Pan.

F11 Zooms into the specified area. Same as View->Zoom In.

Shift-F11 Zooms out of the specified area. Same as View->Zoom Out.



Adding Attributes and Directives Chapter 3: Tasks and Tips

Adding Attributes and DirectivesAttributes and directives are pieces of information that you attach to design objects to control the way in which your design is analyzed, optimized, and mapped. The difference between attributes and directives is that you must specify directives in the source code. Directives can only be added in the source code, but attributes can be added in SCOPE and HDL Analyst windows as well as in the source code. For further details, refer to these subtopics:

• Adding Attributes and Directives in VHDL

• Adding Attributes and Directives in Verilog

• Adding Attributes in SCOPE

• Adding Attributes From the RTL and Technology Views

Adding Attributes and Directives in VHDLYou can also use SCOPE to add attributes to objects, as described in Adding Attributes in SCOPE on page 3-97. However, you can specify direc-tives only in the source code.

1. If you are going to use the predefined attributes package included in the software library, add these lines to the syntax:

library synplify;use synplify.attributes.all;

The advantage to using the predefined package is that you avoid redefining the attributes and directives each time you include them in source code. The disadvantage is that your source code is less portable.

2. Add the attribute or directive you want after the design unit declaration.

<declarations>;attribute <att_name> of <object_name>:<object_kind> is <value>;



Chapter 3: Tasks and Tips Adding Attributes and Directives

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For example:

entity simpledff isport(q: out bit_vector(7 downto 0);

d : in bit_vector(7 downto 0);clk : in bit);

attribute syn_noclockbuf of clk :signal is true;

For information about the syntax of attributes and directives, see the Synplify Pro Reference Manual.

3. If you do not use the predefined attributes package, define attributes after design unit declarations as follows:

<design_unit_declaration>;attribute <att_name> : <data_type>;attribute <att_name> of <object_name>:<object_kind> is <value>;

If you do not use the attributes package, you must redefine the attributes each time you include them in source code. For example:

entity simpledff isport(q: out bit_vector(7 downto 0);

d : in bit_vector(7 downto 0);clk : in bit);

attribute syn_noclockbuf : boolean;attribute syn_noclockbuf of clk :signal is true;

4. Add the source file to the project.

Adding Attributes and Directives in VerilogYou can also use SCOPE to add attributes to objects, as described in Adding Attributes in SCOPE. However, you can only specify directives only in the source code.

1. To add an attribute or directive in Verilog, use Verilog line or block comment syntax directly following the design object, and before the semicolon, if there is one.

Verilog Block Comment Syntax Verilog Line Comment Syntax

/* synthesis <att_name> = <value> *//* synthesis <dir_name> = <value>

// synthesis <att_name> = <value>// synthesis <dir_name> = <value>




Verilog does not have predefined synthesis attributes and directives, so you must add them as comments. Note that the attribute or direc-tive name is preceded by the keyword synthesis. For information about attributes and their values, refer to the Synplify Pro Reference Manual. The following are examples of attributes and directives:

module fifo(out, in) /* synthesis syn_hier = “firm“ */;

module b_box(out, in) /* synthesis syn_black_box */;

2. To attach multiple attributes or directives to the same object, separate the attributes with white spaces, but do not repeat the synthesis keyword. For example:

case state /* synthesis full_case parallel_case */;

Adding Attributes in SCOPESCOPE provides an easy-to-use interface to add any attribute. You cannot use it for adding directives, because they must be added to the source files. (See Adding Attributes and Directives in VHDL on page 3-95 or Adding Attributes and Directives in Verilog on page 3-96).

1. Start with a compiled design and open SCOPE. To add the attributes to an existing constraint file, open SCOPE by clicking on the existing file in the Project view. To add the attributes to a new file, click the SCOPE icon and click Initialize to open the SCOPE window.

2. Click the Attributes tab at the bottom of the SCOPE window.

You can either select the object first (step 2) or the attribute first (step 3).

3. To specify the object, do one of the following in the Object column. If you already specified the attribute, the Object column lists only valid object choices for that attribute.

– Drag the object to which you want to attach the attribute from the RTL or Technology views to the Object column in SCOPE.

– Select the type of object in the Object Filter column, and then select an object from the list of choices in the Object column.

– Type the name of the object in the Object column. If you do not know the name, use the Find command or the Object Filter column.



Chapter 3: Tasks and Tips Adding Attributes and Directives

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If you specified the object first, you can now specify the attribute. The list shows only the valid attributes for the type of object you selected.

4. Specify the attribute by holding down the mouse button in the Attribute column and selecting an attribute from the list.

If you selected the object first, the choices available are determined by the selected object and the technology you are using. If you selected the attribute first, the available choices are determined by the technology.

When you select an attribute, the SCOPE window tells you the kind of value you must enter for that attribute and provides a brief description of the attribute. If you selected the attribute first, make sure to go back and specify the object.

5. Fill out the value. Hold down the mouse button in the Value column, and select from the list. You can also type in a value.

If you manually type an attribute SCOPE does not recognize, or select an incompatible attribute/object combination, the attribute cell is shaded in red.

6. Save the file and add it to the project, if it is not already in the project.

The software saves the SCOPE information in a Tcl constraint file. The file includes the attribute, using this syntax:

define_attribute object_name attribute_name value

When you synthesize the design, the software applies the attribute. For more information on editing the Tcl constraint file directly instead of working in SCOPE, see Working with Constraint Files on page 4-9.




Adding Attributes From the RTL and Technology ViewsYou can add attributes to instances, nets, or ports in the RTL or Technology windows.

1. If you already have a constraint file but you want to use a new one for the attributes, create a file first, and add it to the project. If you are using an existing constraint file, go to the next step.

2. Select an instance, net, or port in an RTL or Technology view.

You can only select a single object. The instance must be a primitive or a module.

3. Right-click and select SCOPE->Edit Attributes from the popup menu.

If the command is grayed out, you have selected an invalid object.

If you do not have a constraint file, the software asks you if you want to create one. If you select OK, the software automatically creates a constraint file and adds it to the project file. If you have a constraint file, the software opens and minimizes it. If there are multiple constraint files, you are prompted to choose one from a list.

Then, an attribute editing dialog box opens.

4. Specify the attribute and the value in the box. The bottom left of the form shows a short description of the selected attribute and lists the type of value required.



Chapter 3: Tasks and Tips Optimizing Results

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Optimizing ResultsYou can optimize your results with attributes and directives, some of which are specific to the technology you are using. For a complete list of all the directives and attributes, see the Reference Manual. This section describes the following:

• Controlling Flattening on page 3-100

• Setting Fanout Limits on page 3-101

Controlling FlatteningOptimization flattens hierarchy. To control the flattening, use the syn_hier attribute as described here. You can also use the attribute to prevent flattening, as described in Preserving Hierarchy on page 3-103.

1. Attach the syn_hier attribute to the module or architecture you want to preserve. You can also add the attribute in SCOPE. If you use SCOPE to enter the attribute, make sure to use the v: syntax.

2. Set the attribute value:

The software flattens the design as directed. If there is a lower-level syn_hier attribute, it takes precedence over a higher-level one.

To... Value...

Flatten all levels below, but not the current level flatten

Remove the current level of hierarchy without affecting the lower levels

remove

Remove the current level of hierarchy and the lower levels flatten, remove

Flatten the current level (if needed for optimization) soft



Optimizing Results Chapter 3: Tasks and Tips

Setting Fanout LimitsOptimization affects net fanout. If your design has critical nets with high fanout, you can set fanout limits.

1. Select Project->Implementation Options and set a global fanout limit on the Device tab.

The value you set is for all the nets in the design. The software uses it as a guide and tries to ensure that all nets have fanouts that are under the limit. The tradeoff for high fanouts is buffering or repli-cated net drivers.

2. For individual nets with high fanouts, set the syn_maxfan attribute on the register output or the input port in certain technologies.

You cannot use this attribute with Cypress and Lattice designs. In Actel 54SX and 42MX designs, the limit you set is a hard limit that the software cannot exceed. In other technologies, the limit is a guide that the software tries to meet.

The software reduces fanout by replicating drivers or adding buffers. When the attribute is set on the register output, it replicates the registers. If the attribute is set on the input ports in Altera Apex, Actel 54SX, Actel 42MX, and QuickLogic pAsic3 designs, the software adds buffers to reduce the fanout.



Chapter 3: Tasks and Tips Preventing Optimization

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Preventing OptimizationYou can use attributes and directives to specify objects or hierarchy that you want to preserve during synthesis.

Preserving Objects from OptimizationSynthesis can collapse or remove nets during optimization. If you want to retain a net for simulation, probing, or for a different synthesis implemen-tation, you must specify this with an attribute. Similarly, the software removes duplicate registers or instances with unused output. If you want to preserve this logic for simulation or analysis, you must use an attribute. The following table lists the attributes to use in each situation. For details about the attributes and their syntax, see the Reference Manual.

To Preserve... Attach... Result

Nets syn_keep on wire or reg (Verilog), or signal (VHDL)

Keeps net for simulation or a different synthesis implementation

Nets for probing syn_probe on wire or reg (Verilog), or signal (VHDL)

Preserves internal net for probing

Shared registers syn_keep on input wire or signal of shared registers

Preserves duplicate driver cells, prevents sharing

Sequential components

syn_preserve on reg or module (Verilog), signal or architecture (VHDL)

Preserves logic of constant-driven registers, keeps registers for simulation, prevents sharing

FSMs syn_preserve on reg or module (Verilog), signal (VHDL)

Prevents the output port or internal signal that holds the value of the state register from being optimized

Instantiated components

syn_noprune on module or component (Verilog), architecture or instance (VHDL)

Keep instance for analysis, preserves instances with unused outputs



Preventing Optimization Chapter 3: Tasks and Tips

Preserving HierarchyThe synthesis process includes cross-boundary optimizations that can flatten hierarchy. To override these optimizations, use the syn_hier attribute as described here. You can also use this attribute to direct the flattening process as described in Controlling Flattening on page 3-100.

1. Attach the syn_hier attribute to the module or architecture you want to preserve. You can also add the attribute in SCOPE. If you use SCOPE to enter the attribute, make sure to use the v: syntax.

2. Set the attribute value:

The software flattens the design as directed. If there is a lower-level syn_hier attribute, it takes precedence over a higher-level one.

To... Value...

Preserve the interface but allow cell packing across the boundary firm

Preserve the interface with no exceptions (Actel except ProASIC, Altera, and Xilinx only)

hard

Preserve the interface and contents with no exceptions (Actel except ProASIC, Altera, Lucent, and QuickLogic only)

macro

Flatten lower levels but preserve the interface of the specified design unit

flatten, firm



Chapter 3: Tasks and Tips Working with Multiple Implementations

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Working with Multiple ImplementationsSynplify Pro lets you create multiple implementations of the same design and then compare results. This lets you experiment with different settings for the same design. Implementations are revisions of your design within the context of the Synplify Pro software, and do not replace external source code control software and processes.

1. Run synthesis on your design.

2. Click the New Impl button or select Project->New Implementation.

The software creates another implementation in the project view. The new implementation has the same name as the previous one, but with a different number suffix.

The new implementation uses the same source code and constraint files. It copies some files from the previous implementation: the .tlg log file, the .srs RTL netlist file, and the <design>_fsm.sdc file gener-ated by FSM Explorer. It also keeps a repeatable history of the synthesis runs.

3. To open more than one implementation in the same Project view, check Allow Multiple Projects to be Opened.

4. Run synthesis again with different settings. For example, you might want to try a different part or experiment with a different frequency. A green arrow marks the current implementation in the project view. The Log Watch Window monitors the current implementation. If you

Project 2

Project 1



Working with Multiple Implementations Chapter 3: Tasks and Tips

configured it to watch all implementations, it automatically adds the current implementation to the window.

5. Compare the results.

– Use the Log watch window to compare selected criteria. Make sure to set the implementations you want to compare with the Configure Watch command. See Using the Log Watch Window on page 3-74 for details.

– To compare details, compare the log file results.

6. To rename an implementation, click the right mouse button on the implementation name in the project view, select Change Implementation Name from the popup menu, and type a new name.

7. To copy an implementation, click the right mouse button on the implementation name in the project view, select Copy Implementation from the popup menu, and type a new name for the copy.

8. To delete an implementation, click the right mouse button on the implementation name in the project view, and select Remove Implementation from the popup menu.



Chapter 3: Tasks and Tips Design Guidelines

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Design GuidelinesThe software automatically makes efficient tradeoffs to achieve the best results. However, you can optimize your results by using the appropriate control parameters. This section describes general design guidelines for optimization. The topics have been categorized as follows:

• General Optimization Tips

• Area Optimization Settings

• Timing Optimization Settings

General Optimization TipsThis section contains general optimization tips that are not directly area or timing-related. For area optimization tips, see Area Optimization Settings on page 3-107. For timing optimization, see Timing Optimization Settings on page 3-107.

• In your source code, remove any unnecessary priority structures in timing-critical designs. For example, use CASE statements instead of nested IF-THEN-ELSE statements for priority-independent logic.

• If your design includes safe state machines, use the syn_encoding attribute with a value of safe. This ensures that the synthesized state machines never lock in an illegal state.

• For FSMs coded in VHDL using enumerated types, use the same encoding style (syn_enum_encoding attribute value) on both the state machine enumerated type and the state signal. This is because discrepancies in the type of encoding can negatively affect the final circuit.

• Make sure that the source code supports inferencing or instantiation by using architecture-specific resources like memory blocks.

• Some designs benefit from hierarchical optimization techniques. To enable hierarchical optimization on your design, set the syn_hier attribute to firm.



Design Guidelines Chapter 3: Tasks and Tips

• For timing-driven synthesis, explicitly define the clock frequency with a constraint. The software does not use the global clock frequency for timing-driven synthesis.

Area Optimization SettingsThis section contains information on optimizing to reduce area. Optimizing for area often means larger delays, and you will have to weigh your performance needs against your area needs to determine what works best for your design. For tips on optimizing for performance, see Timing Optimization Settings on page 3-107. General optimization tips are in General Optimization Tips on page 3-106.

• Increase the fanout limit when you set the implementation options. A higher limit means less replicated logic and fewer buffers inserted during synthesis, and a consequently smaller area. In addition, as P&R tools typically buffer high fanout nets, there is no need for excessive buffering during synthesis.

• Check the resource sharing option when you set implementation options. With this option checked, the software shares hardware resources like adders, multipliers, and counters wherever possible, and minimizes area.

• For designs with large FSMs, use the gray or sequential encoding styles, because they typically use the least area.

• If you are mapping into a CPLD and not meeting area requirements, set the default encoding style for FSMs to sequential instead of onehot.

• For small CPLD designs (less than 20K gates), you might improve area by using the syn_flatten attribute. With this attribute, the software optimizes across hierarchical boundaries and creates smaller designs.

Timing Optimization SettingsThis section contains information on optimizing to meet timing require-ments. Optimizing for timing is often at the expense of area, and you will have to balance the two to determine what works best for your design. For tips on optimizing for area, see Area Optimization Settings on page 3-107. General optimization tips are in General Optimization Tips on page 3-106.



Chapter 3: Tasks and Tips Design Guidelines

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• Use realistic design constraints, about 10 - 15% of the real goal. Over constraining your design can be counter-productive because you can get poor implementations. Use clock boundary, false path, and multicycle path constraints to make the constraints realistic.

• Select a balanced fanout constraint. A large constraint creates nets with large fanouts, and a low fanout constraint results in replicated logic. Both extremes affect routing and design performance. The right value depends on your design. In one design, using a fanout constraint of 32 might result in a fanout of 11 or 12 and large delays on the critical path. In another design a fanout constraint of 32 might result in excessive replication.

• If the critical path goes through arithmetic components, try disabling resource sharing. You can get faster times at the expense of increased area, but use this technique carefully. Adding too many resources can cause longer delays and defeat your purpose.

• Run a second iteration using the -improve or -route options with the appropriate timing constraint. Use the -improve option if Synplify Pro and the P&R tool both report the same critical path.

This forces the software to restructure the design to meet clock frequency goals. Use the -route option if the P&R tool reports a different critical path. With this option, the software adds route delay to its calculations when trying to meet the clock frequency goal. In both cases, use realistic values for the constraints.

• For FSMs, use the onehot encoding style, because it is often the fastest implementation. If a large output decoder follows an FSM, gray or sequential encoding could be faster.

• For designs with black boxes, characterize the timing models accurately, using the syn_tpd, syn_tco, and syn_tso directives.

• If you saw warnings about feedback muxes being created for signals when you compiled your source code, make sure to assign set/resets for the signals. This improves performance by eliminating the extra mux delay on the input of the register.

• Make sure that you pass your timing constraints to the place-and-route tools, so that they can use the constraints to optimize timing.



Generating Vendor-Specific Output Chapter 3: Tasks and Tips

Generating Vendor-Specific OutputYou can generate output targeted to your vendor.

1. To specify the output, click the Impl Options button.

2. Click the Implementation Results tab, and check the output files you need.

The following table summarizes the outputs to set for the different vendors, and shows the P&R tools for which the output is intended.

Vendor Output Netlist P&R Tool

Actel EDIF (*.edn) Designer Series

Actel ProAsic EDIF (*.edn) ASICmaster

Altera Flex EDIF (*.edf) MAX+PLUSII

Altera Apex Verilog (*.vqm) Quartus, Quartus II

Altera Max EDIF (*.edf) MAX+PLUSII

Atmel EDIF (*.edf) Figaro

Cypress VHDL (*.vhn) Warp

Lattice EDIF (*edf) ispExpert

Lattice Mach EDIF (*edf) or *.src ispExpert

Lucent EDIF (*edn) ORCA Foundry

QuickLogic *.qdf SpDE

Triscend EDIF (*.edf) FastChip

Xilinx CoolRunner EDIF (*edf) or *.src Web Fitter for EDIF files, Minc for *.src files

Xilinx Spartan and XC4000, XC4500, etc.

EDIF (*edf )or *xnf Xilinx M2-1i

Xilinx Virtex EDIF (*edf) Xilinx M2-1i



Chapter 3: Tasks and Tips Generating Vendor-Specific Output

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3. To generate mapped Verilog/VHDL netlists and constraint files, check the appropriate boxes and click OK.

See Specifying Result Options on page 3-26 for details about setting the option. For more information about constraint file output formats and how constraints get forward-annotated, see Creating Constraint Files for Forward Annotation on page 4-12.



Chapter 4Advanced Techniques

This chapter covers topics for the advanced user:

• Batch Mode on page 4-2

• Working with Tcl Scripts and Commands on page 4-4

• Working with Constraint Files on page 4-9

• Defining Black Boxes for Synthesis on page 4-15

• Defining State Machines for Synthesis on page 4-24

• Inferring RAMs on page 4-41

• Classic Interface on page 4-52

• Working with Altera Designs on page 4-54

• Working with Xilinx Designs on page 4-59


Chapter 4: Advanced Techniques Batch Mode

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Batch ModeBatch mode is a command-line mode where you run scripts from the command line. You might want to set up multiple synthesis runs with a batch script. You can run in batch mode if you have a floating license, but not with a node-locked license.

Batch scripts are in Tcl format. For more information about Tcl scripts, see Working with Tcl Scripts and Commands on page 4-4 or the Synplify Pro Reference Manual.

This section describes the following operations:

• Running Batch Mode on a Project File

• Running Batch Mode with a Tcl Script

Running Batch Mode on a Project FileUse this procedure to run batch mode if you already have a project file set up.

1. Make sure you have a project file (.prj) set up with the implementation options.

2. In the directory where the project files are located, type the following at the UNIX or DOS command prompt:

synplify_pro -batch project_file_name.prj

The software runs synthesis in batch mode. Use absolute path names or a variable instead of a relative path name.

The software returns 0 if synthesis was successful and a non-zero value if synthesis fails. If you run batch mode with a Tcl file, the software always returns 0.

3. If there are errors in the source files, check the standard output for messages. On UNIX systems, this is generally the monitor; on Windows systems, it is the sdout.log file.

4. After synthesis, check the result_file.srr log file for error messages about the run.



Batch Mode Chapter 4: Advanced Techniques

Running Batch Mode with a Tcl ScriptThe following procedure shows you how to create a Tcl batch script for running synthesis.

1. Create a Tcl batch script. See Creating a Tcl Synthesis Script on page 4-5 for details.

2. Save the file with a *.tcl extension to the directory that contains your source files and other project files.

3. In the directory with the files, type the following at the UNIX or DOS prompt:

synplify_pro -batch Tcl_script.tcl

The software runs synthesis in batch mode.

4. Check for errors.

– For source file errors, check the standard output for messages. On UNIX systems, this is generally the monitor; on Windows systems, it is the stdout.log file.

– For synthesis run errors, check the project_file_name.srr log file.



Chapter 4: Advanced Techniques Working with Tcl Scripts and Commands

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Working with Tcl Scripts and CommandsThe software uses extensions to the popular Tcl (Tool Command Language) scripting language to control synthesis and for constraint files. See the following for more information:

• Using Tcl Commands and Scripts

• Generating a Job Script

• Creating a Tcl Synthesis Script

• Using Tcl Variables for Multiple Runs

• Running Bottom-up Synthesis with a Script

Crossprobing from the Tcl Script WindowTo crossprobe from the Tcl Script window to the source code, click on the appropriate tab (Errors or Warnings) and then double-click a line in the Tcl window. The software opens the relevant source code file and highlights the corresponding code. Crossprobing from the Tcl script window is useful for debugging error messages.

Using Tcl Commands and Scripts1. To get help on Tcl syntax, do any of the following:

– Refer to the Synplify Pro Reference Manual for information about the synthesis commands.

– Refer to the online help (Help -> Tcl Help) for general information about Tcl syntax.

– Type help * in the Tcl window for a list of all the Tcl synthesis commands.

– Type help <command_keyword> in the Tcl window to see the syntax for the command.



Working with Tcl Scripts and Commands Chapter 4: Advanced Techniques

2. To run a Tcl script, either type source Tcl_scriptfile in the Tcl script window, or do the following:

– Select File -> Run Tcl Script.

– Select the Tcl file you want and click Open.

The software runs the selected script and executes the commands in it. For more information about Tcl scripts, refer to the following sections.

Generating a Job ScriptYou can record Tcl commands from the interface and use it to generate job scripts.

1. In the Tcl script window, type recording -file logfile to write out a Tcl log file.

2. Work through a synthesis session.

The software saves the commands from this session into a Tcl file that you can use as a job script, or as a starting point for creating other Tcl files.

Creating a Tcl Synthesis ScriptTcl scripts are text files with a *.tcl extension. The following covers general guidelines for creating a script from scratch.

1. Use a text file editor or select File->New, click the Tcl Script option and type a name for your Tcl script.

2. Specify the project with the project -new command. For an existing project, use load project.prj.

3. Add files.

– Add source files with add_file -vhdl or add_file -verilog.

– Add constraint files with add_file -constraint.




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4. Set the design synthesis controls and the output:

– Use the set_option command for implementation options.

– Set vendor-specific controls as needed. See the appropriate vendor chapter in the Synplify Pro Reference Manual for details.

– Set the output file information with project -result_file and project -log_file.

5. Set the file and run options:

– Save the project with project -save.

– Run the project with project -run.

6. Check the syntax.

– Check case, because Tcl is case-sensitive.

– Start all comments with a hash mark (#).

– Enclose all pathnames and filenames in double quotes.

– Always use a forward slash (/) in directory and pathnames, even on the PC.

Using Tcl Variables for Multiple Runs To create a single script for multiple synthesis runs with different criteria, you need to create a Tcl variable for the different settings you want to try. For example, you might want to try different target technologies.

1. To create a variable, use this syntax:

set variable_name {first_option_to_trysecond_option_to_try...}

2. Create a foreach loop that runs through each option in the list, using the appropriate Tcl commands. The following example shows a variable set up to synthesize a design with different frequencies:



Working with Tcl Scripts and Commands Chapter 4: Advanced Techniques

This example sets up synthesis with different target technologies:

Running Bottom-up Synthesis with a ScriptTo run bottom-up synthesis, you create Tcl scripts for individual logic blocks, and a script for the top level that reads the other Tcl scripts.

1. Create a Tcl script for each logic block. The Tcl script must synthesize the block.

2. Create a top-level script that reads the block scripts using this syntax:

source “block_script.tcl”

set try_freq {20.024.028.032.036.040.0

)foreach frequency $try_freq {

set_option -frequency $frequencyproject -log_file $frequency.srrproject -run}

Synplify Pro Tcl commands that set the frequency option, create log files for each run, and run synthesis

Foreach loop

Set of frequenciesto try

set try_tech {FLEX8000FLEX10KACT3XC4000XC4000EXC400EX

)foreach technology $try_tech {

set_option -technology $technologyproject -run}

Synplify Pro Tcl commands that set the technology option and run synthesis.

Foreach loop

Set of technologies to try




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3. Create a new project for the top level with project -new.

4. Add the top-level data:

– Add source files with add_file -vhdl or add_file -verilog.

– Add constraint files with add_file -constraint.

– Set the top-level options with set_option.

– Set the output file information with project -result_file and project -log_file.

– Save the project with project -save.

– Run the project with project -run.

When the script has finished running, the entire design is synthe-sized, beginning with the lower-level logic blocks specified in the sourced files, and then the top level.



Working with Constraint Files Chapter 4: Advanced Techniques

Working with Constraint FilesConstraint files are text files that are generated by SCOPE (see Setting Constraints with SCOPE on page 3-28), or which you create manually with a text editor. They contain Tcl commands or attributes that constrain the synthesis run. Alternatively, you can set constraints in the source code, but it is not the preferred method.

This section contains information about

• When to Use Constraint Files over Source Code

• General Tcl Guidelines

• Creating Constraint Files

• Creating Constraint Files for Forward Annotation

When to Use Constraint Files over Source CodeYou can add constraints in constraint files (generated by SCOPE or entered in a text editor) or in the source code. In general, it is better to use constraint files, because you do not have to recompile for the constraints to take effect. It also makes your source code more portable.

However, if you have black box timing constraints (syn_tco, syn_tpd, syn_tsu) or directives, you must enter them in the source code. Unlike attributes, directives can only be added to the source code, not to constraint files. See Adding Attributes and Directives on page 3-95 for more information on adding directives to source code.

General Tcl GuidelinesThis section covers general guidelines for using Tcl for constraint files:

• Pay attention to case, because Tcl is case-sensitive.

• Remember these rules when naming objects:

– Make sure that object names match the names in the HDL code.

– Enclose all instance and port names with curly braces {}.



Chapter 4: Advanced Techniques Working with Constraint Files

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– Do not use spaces in names.

– Use periods as separators in hierarchical names

– Use the following syntax for instance, port, and net names in Verilog modules, where cell is the name of the design entity, prefix is a prefix to identify objects with the same name, and object_name is an instance path with periods as separators:

v:cell[prefix:]object_name

– Use the following syntax for instance, port, and net names in VHDL modules, where v: identifies it as a view object, lib is the name of the library, cell is the name of the design entity, view is a name for the architecture, prefix is a prefix to identify objects with the same name, and object_name is an instance path with periods as separators. You only need view if there is more than one architecture for the design. See the preceding table for the prefixes for different objects.

v:cell[.view] [prefix:]object_name

• You can use the * and ? wildcards to match names. The asterisk matches any number of characters, and the question mark matches a single character. These characters do not match periods that are used as hierarchy separators. For example, you can use the following to identify all bits of the statereg instance in the statemod module:

statemod | i: statereg[*]

Prefix (Lower-case) Object

i: Instance names

p: Port names (entire port)

b: Bit slice of a port

n: Net names




Creating Constraint FilesThis section shows you how to create a Tcl file for general timing constraints. Black box constraints must be entered in the source code. For details of the Tcl commands, refer to the Synplify Pro Reference Manual. You can also enter equivalent commands in the source code, but this is not recommended. For additional information, see When to Use Constraint Files over Source Code on page 4-9.

1. Open a file for editing.

– Make sure you have closed SCOPE, or you could overwrite previous constraints.

– To create a new file, select File->New, and select the Constraint File (SCOPE) option. Type a name for the file and click OK.

– To edit an existing file, select File->Open, set the Files of Type filter to Constraint Files (.sdc) and open the file you want.

2. Follow the syntax guidelines in General Tcl Guidelines on page 4-9.

3. Enter the timing constraints you need. If you have black box timing constraints, you must enter them in the source code.

To define... Use...

Clock frequencies define_clock

Clock frequency other than the one implied by the signal on the clock pin

syn_reference_clock(attribute)

Maximum allowable delay between flip-flops on different clock domains

define_clock_delay

False paths between clock domains that are to be ignored

define_clock_delay

Clock domains with asymmetric duty cycles define_clock_delay

Speed up paths feeding into a register define_reg_input_delay




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4. If you want to add vendor-specific attributes in this file, use define_attribute. Set global attributes with define_global_attribute. See Adding Attributes and Directives on page 3-95 for more information about using attributes.

5. Save the file.

6. Add the file to the project as described in Making Changes to a Project on page 3-16, and run synthesis.

Creating Constraint Files for Forward AnnotationYou can create certain vendor-specific constraint files, where the Synplify Pro constraints are mapped to the appropriate vendor constraints.

1. Set attributes to control forward annotation.

– To forward-annotate I/O constraints (define_input_delay and define_output_delay) to the .tcl file for APEX designs or the .ncf file for Xilinx designs, set syn_forward_io_constraints with a value of 1 on the top level of the design or as a global attribute.

– For Xilinx designs, relax period constraints that are too tight with the xc_ncf_auto_relax attribute set to 1. This attribute controls constraints on paths from input to register and from register to output.

– For Lucent designs, set the -from and -to false path and multicycle constraints on the Others tab of the SCOPE interface.

For details about the attributes, see the Synplify Pro Reference Manual.

Speed up paths coming from a register define_reg_output_delay

Input delays from outside the FPGA define_input_delay

Output delays from your FPGA define_output_delay

Paths with multiple clock cycles define_multicycle_path

False paths (certain technologies) define_false_paths

To define... Use...




2. Select Project->Implementation Options, and check Write Vendor Constraints in the Implementation Results tab.

Currently you can forward-annotate constraints for some vendors only.


The software converts the Synplify Pro define_input_delay, define_output_delay, define_clock, and global frequency constraints into corresponding commands in the *.acf file for Altera, the *.lp file for Lucent, and the *.ncf file for Xilinx. See the following table for details about the forward annotation.

Synplify Pro Constraint Vendor Constraint

Altera *.tcl File

define_input_delay External pin delays

define_output_delay External pin delays

define_clock Frequency

global frequency Frequency

duty_cycle DUTY_CYCLE = %_of_clk_period

altera_chip_pin_lc pin : LOCATION = pin_value

Altera *.acf File

define_input_delay input : TSU = period - input_delay

define_output_delay output : TCO = period - output_delay

define_clock clock : FREQUENCY = freq

global frequency FREQUENCY = freq

altera_chip_pin_lc pin : LOCATION = pin_value

Lucent *.lp File

define_input_delay INPUT_SETUP input NS clknet = net

define_output_delay CLOCK_TO_OUT output NS clknet = net

define_clock FREQUENCY PORT clkname number MHz




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4. For Lucent designs, you must copy the constraints into the Lucent .prf file.

– Open the ORCA Foundry place-and-route tool, and run the Map stage. This creates a .prf file.

– Copy the .lp file created by the Synplicity software and paste it at the end of the .prf file. Do not overwrite the .prf file.

define_multicycle_path MULTICYCLE [ FROM | TO ] PORT "name" clock_cycles-or-MULTICYCLE [ FROM | TO ] CELL "name" clock_cycles

define_false_paths BLOCK PATH [ FROM | TO ] PORT "name"-or-BLOCK PATH [ FROM | TO ] CELL "name"

Xilinx *.ncf File

define_input_delay NET input OFFSET = IN : period -input_delay : BEFORE clk

define_output_delay NET output OFFSET = OUT: period -output_delay : BEFORE clk

define_clock NET clk PERIOD = period

define_multicycle_path INST from_instance_name TNM = from_value;INST to_instance_name TNM = to_value;TIMESPEC from_value = TO to_value (number of cycles * period)

define_false_path INST from_instance_name TNM = from_value;INST to_instance_name TNM = to_value;TIMESPEC from_value = TO to_value TIG;

Synplify Pro Constraint Vendor Constraint



Defining Black Boxes for Synthesis Chapter 4: Advanced Techniques

Defining Black Boxes for SynthesisBlack boxes are predefined components for which the interface is speci-fied, but whose internal architectural statements are ignored. They are used as place holders for IP blocks, legacy designs, or a design under development.

This section discusses the following topics:

• Instantiating Black Boxes and I/Os in Verilog on page 4-15

• Instantiating Black Boxes and I/Os in VHDL on page 4-17

• Adding Black Box Timing Constraints on page 4-19

• Adding Other Black Box Attributes on page 4-21

Instantiating Black Boxes and I/Os in Verilog Verilog black boxes for macros and I/Os come from two sources: commonly-used or vendor-specific components that are predefined in Verilog macro libraries, or black boxes that are defined in another input source like a schematic. The following process shows you how to instan-tiate both types as black boxes.

1. To instantiate a predefined Verilog module as a black box:

– Select the library file with the macro you need from the Synplify_install_dir/lib/vendor directory. Files are named family.v. Most vendor architectures provide macro libraries that predefine the black boxes for primitives and macros.

– Add the file to the top of the source file list for your project.

2. To instantiate a module that has been defined in another input source as a black box:

– Create an empty macro that only contains ports and port directions.



Chapter 4: Advanced Techniques Defining Black Boxes for Synthesis

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– Put the syn_black_box synthesis directive just before the semicolon in the module declaration.

module myram (out, in, addr, we) /* synthesis syn_black_box */;output [15:0] out;input [15:0] in;input [4:0] addr;input we;

endmodule

– Make an instance of the stub in your design.

– Compile the stub along with the module containing the instantiation of the stub.

3. To instantiate a vendor-specific (black box) I/O that has been defined in another input source:

– Create an empty macro that only contains ports and port directions.

– Put the syn_black_box synthesis directive just before the semicolon in the module declaration.

– Specify the external pad pin with the .ispad directive. These examples show the directives attached to different pads:

module vendors_input pad(out, in) /* synthesis syn_black_box*/;output out;input in /* synthesis .ispad=1 */;...

module vendors_output pad(out, in) /* synthesis syn_black_box*;output out /* synthesis .ispad=1 */;input in ;

...

– Make an instance of the stub in your design.

– Compile the stub along with the module containing the instantiation of the stub.

4. Add timing constraints and attributes as needed. See Adding Black Box Timing Constraints on page 4-19 and Adding Other Black Box Attributes on page 4-21.




5. After synthesis, merge the black box netlist and the synthesis results file using the method specified by your vendor.

Instantiating Black Boxes and I/Os in VHDL VHDL black boxes for macros and I/Os come from two sources: commonly-used or vendor-specific components that are predefined in VHDL macro libraries, or black boxes that are defined in another input source like a schematic. The following process shows you how to instan-tiate both types as black boxes.

1. To instantiate a predefined VHDL macro (for a component or an I/O),

– Select the library file with the macro you need from the Synplify_install_dir/lib/vendor directory. Files are named family.vhd. Most vendor architectures provide macro libraries that predefine the black boxes for primitives and macros.

– Add the appropriate library and use clauses to the beginning of your design units that instantiate the macros.

library family ;use family.components.all;

2. To create a black box for a component from another input source:

– Create a component declaration for the black box.

– Declare the syn_black_box attribute as a boolean attribute.

– Set the attribute to be true.

library synplify;use synplify.attributes.all;entity top is

port (clk, rst, en, data: in bit; q; out bit);end top;

architecture structural of top iscomponent bbox

port(Q: out bit; D, C, CLR: in bit);end component;

attribute syn_black_box of bbox: component is true;...




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– Instantiate the black box and connect the ports.

beginmy_bbox: my_bbox port map (

Q => q,D => data_core,C => clk,CLR => rst);

If you plan to simulate with a VHDL simulator, you must define the internals of black boxes, even though the synthesis software ignores it.

3. To create a vendor-specific (black box) I/O for an I/O defined in another input source:

– Create a component declaration for the I/O.

– Declare the black_box_pad_pin attribute as a string attribute.

– Set the attribute value on the component to be the external pin name for the pad.

library synplify;use synplify.attributes.all;...

component mybufport(O: out bit; I: in bit);

end component;

attribute black_box_pad_pin of mybuf: component is “I”;

– Instantiate the pad and connect the signals.

begindata_pad: mybuf port map (

O => data_core,I => data);

4. Add timing constraints and attributes as needed. See Adding Black Box Timing Constraints on page 4-19 and Adding Other Black Box Attributes on page 4-21.




Adding Black Box Timing ConstraintsWhen a design includes a black box, Synplify Pro has no information about timing characteristics inside the box. You must ensure that you characterize black box timing correctly, because it can critically affect the overall timing of the design. To do this, you use constraints, added as directives in the source code. You cannot add black box constraints in SCOPE, because the constraints apply to individual instances. As an alternative to timing constraints, you can use a STAMP model, described in Defining Black Boxes Using STAMP Models on page 4-22.

You attach black box timing constraints to instances that have been defined as black boxes. There are three black box timing constraints, syn_tpd, syn_tsu, and syn_tco.

1. Define the instance as a black box, as described in Instantiating Black Boxes and I/Os in Verilog on page 4-15 or Instantiating Black Boxes and I/Os in VHDL on page 4-17.

2. Determine the kind of constraint for the information you want to specify:

For each directive, there are ten predeclared constraints in the attributes package, from directive_name1 to directive_name10. In VHDL, you must use the predefined attributes package to use the prede-clared constraints.

If you need more constraints, declare them by using the next number, like syn_tco11, for example.

3. In VHDL, use the following syntax for the constraints:

– Use the predefined attributes package by adding this syntax

library synplify;use synplify.attributes.all;

To define... Use...

Propagation delay through the black box syn_tpd

Setup delay (relative to the clock) for input pins syn_tsu

Clock-to-output delay through the black box syn_tco




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– Define the constraints with this syntax:

attribute directive_name<n> : “ bundle -> bundle = value”

For general information about adding directives to the source code, see Adding Attributes and Directives in VHDL on page 3-95. The following is an example of the directives:

architecture top of top iscomponent rcf16x4z port(

ad0, ad1, ad2, ad3 : in std_logic;di0, di1, di2, di3 : in std_logic;wren, wpe : in std_logic;tri : in std_logic;do0, do1, do2 do3 : out std_logic;

end component

attribute syn_tpd1 of rcf16x4z : component is“ad0,ad1,ad2,ad3 -> do0,do1,do2,do3 = 2.1”

attribute syn_tpd2 of rcf16x4z : component is“tri -> do0,do1,do2,do3 = 2.0”

attribute syn_tsu1 of rcf16x4z : component is“ad0,ad1,ad2,ad3 -> ck = 1.2”

attribute syn_tsu2 of rcf16x4z : component is“wren,wpe,do0,do1,do2,do3 -> ck = 0.0”

4. In Verilog, add the directives as comments, as shown in this example:

module ram32x4 (z, d, addr, we, clk)/* synthesis syn_black_boxsyn_tpd1=”addr[3:0]->z[3:0]=8.0”syn_tsu1=”addr[3:0]->clk=2.0”syn_tsu2=”we->clk=3.0” */;

output [3:0[ z;input [3:0] d;input [3:0] addr;input we;input clk;endmodule

For general information about adding directives to the source code, see Adding Attributes and Directives in Verilog on page 3-96.

5. After synthesis, check black box timing.




Adding Other Black Box AttributesBesides black box timing constraints, you can also add other attributes to define pin types on the black box. You cannot use the attributes for all technologies. Check the Reference Manual for support details.

1. To specify that a clock pin on the black box has access to global clock routing resources, use syn_isclock.

Depending on the technology, different clock resources are inserted. In Xilinx, the software inserts BUFG, for Actel it inserts CLKBUF, and for QuickLogic, it inserts Q_CKPAD.

2. To specify that the software need not insert a pad for a black box pin, use black_box_pad_pin.

Use this for technologies that automatically insert pad buffers for the I/Os like Xilinx, some Altera families, Actel, Lattice, QuickLogic, Lucent, and Triscend.

3. To define a tristate pin so that you do not get a mixed driver error when there is another tristate buffer driving the same net, use black_box_tri_pins.

4. To ensure consistency between synthesized black box netlist names and the names generated by third party tools or IP cores, use the following attributes (Xilinx only):

– syn_edif_bit_format

– syn_edif_scalar_format

Pad

Clk

Clk buffer

syn_isclock

black_box_tri_pins

Black Box

black_box_pad_pin




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5. To specify that a port on a black box is connected to an internal STARTUP block in Xilinx XC4000architectures, use the xc_isgr directive.

Defining Black Boxes Using STAMP ModelsSTAMP is a Synopsys modeling language that you can use to describe the timing models of black boxes. For details about STAMP, see your FPGA vendor or the Synopsys documentation. Synplify Pro uses the STAMP timing models to generate synthesis results that more accurately reflect the final physical results.

Use the method described here for only those black boxes that come from the FPGA vendor with a STAMP model. For other black boxes, use the timing constraints described in Defining Black Boxes for Synthesis on page 4-15. To use STAMP files for synthesis, you must do the following:

1. Check the limitations to using this model, described in Limitations on page 4-23.

2. To instantiate the black box, create a black box wrapper for the module in the HDL source code. The wrapper must define the output and input ports.

3. Make sure you have the following vendor-supplied STAMP files for the black box. See your FPGA vendor for information about generating the STAMP models for black boxes.

– <name>.mod describes the port modes and the interface timing arcs of the block.

– <name>.data describes the actual delay and constraint values for the arcs in the model file.

Black Box

StartupR

Rxc_isgr




The file name must be the same as the module name. Both STAMP files have the same name, with different extensions. Although the STAMP format allows multiple .data files, you can only use one file with the synthesis software. For information about STAMP files, see the Synopsys documentation.

4. Add the .mod and .data files to the project, using the Project-> Add Source File command.

In the Project view, the software creates a separate folder and adds the files to it.

5. Run synthesis.

Synplify Pro translates the STAMP information into a proprietary internal format. It automatically links the converted model to the rest of the design and uses it during synthesis.

LimitationsBecause Synplify Pro is a synthesis tool, not a timing tool, it only supports a subset of the STAMP capabilities. The following are some of the currently unsupported timing features:

• Multiple .data files for different operating conditions

• Conditional arcs

• Max/min timing arcs

• Internal timing points

• Modes

• Models other than worst-case timing

• Models using multiple clocks or edges

• Constraints other than setup/hold and posedge/negedge

• Generated clocks

• Internal pins

• Buses

• Scaling information



Chapter 4: Advanced Techniques Defining State Machines for Synthesis

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Defining State Machines for SynthesisA finite state machine (FSM) is a piece of hardware that advances from state to state at a clock edge. The synthesis software recognizes and extracts the state machines from the HDL source code. For guidelines on setting up the source code, see the following:

• Defining Verilog State Machines

• Defining VHDL State Machines

For information about the attributes used to define state machines, see Running the FSM Compiler on Individual State Machines on page 3-85.

Defining Verilog State MachinesThe synthesis software recognizes and automatically extracts state machines from the Verilog source code if you follow these coding guide-lines:

• In Verilog, model the state machine with case, casex, or casez state-ments in always blocks. Check the current state to advance to the next state and then set output values. Do not use if statements.

• Always use a default assignment as the last assignment in the case statement, and set the state variable to ‘bx. This is a “don’t care” statement and ensures that the software can remove unnecessary decoding and gates.

• Make sure the state machines have a synchronous or asynchronous reset to set the hardware to a valid state after power-up, or to reset the hardware when you are operating.

• Use explicit state values for states using parameter or ‘define state-ments. This is an example of a parameter statement that sets the current state to 2’h2:

parameter state1 = 2’h1, state2 = 2’h2;...current_state = state2;



Defining State Machines for Synthesis Chapter 4: Advanced Techniques

This example shows how to set the current state value with ‘define statements:

‘define state1 2’h1‘define state2 2’h2...current_state = ‘state2;

Defining VHDL State MachinesThe synthesis software recognizes and automatically extracts state machines from the VHDL source code if you follow these coding guide-lines:

• Use CASE statements to check the current state at the clock edge, advance to the next state, and set output values. You can also use IF-THEN-ELSE statements, but CASE statements are preferable.

• If you do not cover all possible cases explicitly, include a WHEN OTHERS assignment as the last assignment of the CASE statement, and set the state vector to some valid state.

• If you create implicit state machines with multiple WAIT statements, the software does not recognize them as state machines.

• Make sure the state machines have a synchronous or asynchronous reset to set the hardware to a valid state after power-up, or to reset the hardware when you are operating.

• To choose an encoding style, attach the syn_encoding attribute to the enumerated type. The software automatically encodes your state machine with the style you specified.



Chapter 4: Advanced Techniques Using FSM Explorer

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Using FSM Explorer

Deciding When to Use the FSM ExplorerThe FSM Explorer and the FSM Compiler are automatic tools for encoding state machines. Like the FSM Compiler, you use the FSM Explorer to generate better results for your state machines. Unlike the FSM Compiler, which picks an encoding style based on the number of states, the FSM Explorer tries out different encoding styles and picks the best style for the state machine based on overall design constraints. The tradeoff is that the FSM Explorer takes longer to run than the FSM Compiler.

In addition to the two automatic tools, you can always specify state machine encoding manually with attributes. For more information about the attributes, see Specifying FSMs with Attributes and Directives on page 3-87.

Running the FSM Explorer1. If you need to customize the extraction process, set attributes.

– Use syn_state_machine=0 to specify state machines you do not want to extract and optimize.

– Use syn_encoding if you want to set a specific encoding style.

Verilog reg [3:0] curstate /* synthesis state_machine */ ;

VHDL signal curstate : state_type;attribute syn_state_machine : boolean;attribute syn_state_machine of curstate : signal is true;

Verilog reg [3:0] curstate /* synthesis syn_encoding “gray”*/ ;

VHDL signal curstate : state_type;attribute syn_encoding : string;attribute syn_encoding of curstate : signal is true;



Using FSM Explorer Chapter 4: Advanced Techniques

The FSM Compiler honors the syn_state_machine attribute when it extracts state machines, and the FSM Explorer honors the syn_encoding attribute when it sets encoding styles. See Specifying FSMs with Attributes and Directives on page 3-87 for details.

2. Enable the FSM Explorer by checking the FSM Explorer box in one of these places:

– The main panel on the left side of the project window

– The Options/Constraints tab of the dialog box that comes up when you click the New Impl or Impl Options buttons.

If you have not checked the FSM Compiler option, checking the FSM Explorer option automatically selects the FSM Compiler option.

3. Click Run to run synthesis.

The FSM Explorer uses the state machines extracted by the FSM Compiler. If you have not run the FSM Compiler, the FSM Explorer invokes the compiler automatically to extract the state machines, instantiate state machine primitives, and optimize them. Then, the FSM Explorer runs through each encoding style for each state machine that does not have a syn_encoding attribute and picks the best style. If you have defined an encoding style with syn_encoding, it uses that style.

The FSM Compiler writes a description of each state machine extracted and the set of reachable states for each state machine in the log file. The FSM Explorer adds the selected encoding styles. The FSM Explorer also generates a <design>_fsm.sdc file that contains the encodings and which is used for mapping.



Chapter 4: Advanced Techniques Using FSM Explorer

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4. Select View->View Log File and check the log file for the descriptions. The following extract shows the state machine and the reachable states as well as the encoding style, gray, set by FSM Explorer.

Extracted state machine for register cur_stateState machine has 7 reachable states with original encodings of:

0000001000001000001000001000001000001000001000000

....Adding property syn_encoding, value "gray", to instancecur_state[6:0]List of partitions to map:

view:work.Control(verilog)

Encoding state machine work.Control(verilog)-cur_state_h.cur_state[6:0]original code -> new code

0000001 -> 0000000010 -> 0010000100 -> 0110001000 -> 0100010000 -> 1100100000 -> 1111000000 -> 101

5. Check the state machine implementation in the RTL and Technology views and in the FSM viewer.

For information about the FSM viewer, see Using the FSM Viewer on page 3-89.



Pipelining Chapter 4: Advanced Techniques

PipeliningPipelining is the process of splitting logic into stages so that the first stage can begin processing new inputs while the last stage is finishing the previous inputs. This ensures better throughput and faster circuit perfor-mance. If you have a Xilinx Virtex design, you can use another, related technique to improve performance: retiming. See Retiming on page 4-34 for details.

For pipelining, The software splits the logic by moving registers into the module:

Reg RegRegLUT LUTLUT LUTData

Clk

Without Pipelining

After Pipelining

Reg RegRegLUTLUT LUTData

Clk

LUT



Chapter 4: Advanced Techniques Pipelining

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Prerequisites for Pipelining• Currently, pipelining is only supported for Altera Apex or Flex

designs, and Xilinx Virtex designs.

• In Xilinx Virtex designs, you can pipeline ROMs and multipliers. In Altera Apex and Flex designs, you can pipeline multipliers, but not ROMs.

• ROMs to be pipelined must be at least 512 words. Anything below this limit is too small.

• For Xilinx Virtex designs, you can push any kind of flip-flop into the module, as long as all the flip-flops in the pipeline have the same clock, the same set/reset signal or lack of it, and the same enable control or lack of it. For Altera Apex and Flex designs, you must have asynchronous set/resets if you want to do pipelining.

Pipelining the Entire DesignUse this approach as a first pass to get a feel for which modules you can pipeline. If you know exactly which registers you want to pipeline, use one of the other two methods: Adding Pipelining Attributes in the Source Code on page 4-31 or Adding Pipelining Attributes Interactively on page 4-32.

1. Make sure the design meets the criteria described in Prerequisites for Pipelining on page 4-30.




2. Specify pipelining by either clicking the Pipelining option in the Project window, or by selecting Project -> Implementation Options and checking the Pipelining option in the Device tab.

3. Click Run.

The software looks for all the registers in the design where all the flip-flops of the same row have the same clock, no control signal, or the same unique control signal, and pushes them inside the module. It attaches the syn_pipeline attribute to all these registers.

4. Check the log file (*.srr). You can use the Find command for occurrences of the word pipelining to find out which modules got pipelined.

The log file entries look like this:

@N:|Pipelining module res_out1@N:|res_i is level 1 of the pipelined module res_out1@N:|r is level 2 of the pipelined module res_out1

If you do not want to pipeline some of the modules, you can do another run where you attach the attribute to the registers you want.

Adding Pipelining Attributes in the Source CodeOnce you know which modules you want to pipeline, you can attach the syn_pipeline attribute to the registers directly in the source code. An alter-native method is to do it interactively, as described in Adding Pipelining Attributes Interactively on page 4-32.


2. For Verilog source code, attach the syn_pipeline attribute as a comment in the reg statement:

reg [‘lefta:0] a_aux;reg [‘leftb:0] b_aux;reg [‘lefta+‘leftb+1:0] res /* synthesis syn_pipeline=1 */;reg [‘lefta+‘leftb+1:0] res1;



Chapter 4: Advanced Techniques Pipelining

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The value 1 indicates that pipelining is turned on. For detailed infor-mation about Verilog attributes and examples of the files, see the Synplify Pro Reference Manual.

3. For VHDL source code, add the syn_pipeline attribute to a register as an attribute:

architecture beh of onereg is

signal temp1, temp2, temp3,std_logic_vector(31 downto 0);

attribute syn_pipeline : boolean;attribute syn_pipeline of temp1 : signal is true;attribute syn_pipeline of temp2 : signal is true;attribute syn_pipeline of temp3 : signal is true;

For detailed information about VHDL attributes and sample files, see the Reference Manual.

4. Run synthesis.

The software looks for registers with the syn_pipeline attribute and pushes them into the previous multiplier or ROM.

5. Check that the registers you marked were pipelined. Check the log file (*.srr) and the RTL view.

Adding Pipelining Attributes InteractivelyOnce you know which registers you want to pipeline, you can select the registers interactively. An alternative method is to specify pipelining in the source code, as described in Adding Pipelining Attributes in the Source Code on page 4-31.


2. Open the RTL view of the design and check that the register is suitable for pipelining.




– Select the register and press F12 to filter the schematic view.

– In the new schematic view, select the output and type e (or select Expand from the popup menu. Check that the register is suitable for pipelining.

3. Add the attribute to the register.

– Open SCOPE and click the Attributes tab at the bottom. If you already have a constraints file, you can open the existing file and add the attribute in that file.

– Select the register in the RTL view and drag it to the Object column in SCOPE.



Chapter 4: Advanced Techniques Retiming

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– Set Attribute to syn_pipeline, and Value to 1. A value of 1 enables pipelining.

– If you created a new constraints file, add the constraints file to the project.

4. Run synthesis.

The software looks for registers with the syn_pipeline attribute and pushes them into the previous module.

5. Check that the registers you marked were pipelined. Check the log file (*.srr) and the RTL view.

RetimingRetiming is a powerful technique for improving the timing performance of sequential circuits. Retiming automatically moves registers (register balancing) across combinatorial gates or LUTs to improve timing while ensuring identical behavior as seen from the primary inputs and outputs of the design. Retiming moves registers across gates or LUTs, but does not change the number of registers in a cycle or path from a primary input to a primary output. However, it can change the total number of registers in a design.

The Synplify Pro retiming algorithm retimes only edge-triggered registers. It does not retime level-sensitive latches. Currently you can use retiming for the Xilinx Virtex families only (Virtex, VirtexE, Spartan 2, and Virtex 2).



Retiming Chapter 4: Advanced Techniques

Retiming During SynthesisThe following procedure shows you how to use retiming when you are synthesizing a Virtex family design.

1. To enable retiming for the whole design, check the Retiming check box.

You can set the Retiming option from the button panel in the Project window, or with the Project->Implementation Options command (Device tab).

Retiming is a superset of pipelining, so when you select Retiming, you automatically select Pipelining. See Pipelining on page 4-29 for more information.

Retiming works globally on the design, and moves edge-triggered registers as needed to balance timing.

Set the retiming option in either place.



Chapter 4: Advanced Techniques Retiming

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2. To enable retiming on selected registers, use either of the following techniques:

– Check the Retiming checkbox and attach the syn_allow_retiming attribute with a value of 0 or false to any registers you do not want the software to move. This attribute specifies that the register cannot be moved for retiming.

– Do not check the Retiming checkbox. Attach the syn_allow_retiming attribute with a value of 1 or true to any registers you want the software to consider for retiming. This attribute marks the register as one that can be moved during retiming, but does not necessarily force it to be moved during retiming.

– Retiming is a superset of Pipelining, therefore adding syn_allow_retiming=1 on any registers implies syn_pipeline =1.

3. Set other options for the run.

4. Click Run to start synthesis.

After the LUTs are mapped, the software moves registers to optimize timing. See Retiming Example on page 4-37 for an example. You might not be able to crossprobe between the RTL view and the Technology view, because there is no longer a one-to-one correspon-dence between the objects in these views. For example, a single register in the RTL view might now correspond to multiple registers in the Technology view.

The log file includes a retiming report that you can analyze to under-stand the retiming changes. It contains a list of all the registers added or removed because of retiming. Retimed registers have a _ret suffix added to their names. See Retiming Report on page 4-38 for more information about the report.

Retiming does not change simulation behavior (as observed from primary inputs and outputs) of your design, However if you were monitoring (probing) values on individual registers inside the design, you might need to modify your test bench.



Retiming Chapter 4: Advanced Techniques

Retiming ExampleThe following example shows two levels of logic between the registers and the output, and no levels of logic between the inputs and the registers.

The next figure shows the results of retiming the three registers at the input of the OR gate. The levels of logic from the register to the output are reduced from two to one. The retimed circuit has better performance than the original circuit. Timing is improved by transferring one level of logic from the critical part of the path (register to output) to the non-critical part (input to register).



Chapter 4: Advanced Techniques Inserting Probes

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Retiming ReportThe retiming report is part of the log file, and includes the following infor-mation:

• The number of registers added, removed, or untouched by retiming. Registers added by retiming have a _ret suffix added to their names.

• Names of the registers that were moved by retiming and which no longer exist in the Technology view.

• Names of the registers created as a result of the retiming moves and which did not exist in the RTL view.

Inserting Probes

Specifying Probes in the Source CodeTo specify probes in the source code, you must add the syn_probe attribute to the net. You can also add probes interactively, using the procedure described in Adding Probe Attributes Interactively on page 4-40.

1. Open the source code file.

2. For Verilog source code, attach the syn_probe attribute as a comment on any internal signal declaration:

module alu(out, opcode, a, b, sel);output [7:0] out;input [2:0] opcode;input [7:0 a, b;input sel;reg [7:0] alu_tmp /* synthesis syn_probe=1 */;reg [7:0] out;

//Other code

The value 1 indicates that probe insertion is turned on. For detailed information about Verilog attributes and examples of the files, see the Synplify Pro Reference Manual.



Inserting Probes Chapter 4: Advanced Techniques

To define probes for part of a bus, specify where you want to attach the probes; for example, if you specify reg [1:0] in the previous code, the software only inserts two probes.

3. For VHDL source code, add the syn_probe attribute as follows:

architecture rtl of alu issignal alu_tmp : std_logic_vector(7 downto 0) ;attribute syn_probe : boolean;attribute syn_probe of alu_tmp : signal is true;--other code;

For detailed information about VHDL attributes and sample files, see the Synplify Pro Reference Manual.

4. Run synthesis.

The software looks for nets with the syn_probe attribute and creates probes and I/O pads for them.

5. Check the probes in the log file (*.srr) and the Technology view.

This figure shows some probes and some probe entries in the log file.

Adding property syn_probe, value 1, to net pc[0]Adding property syn_probe, value 1, to net pc[1]Adding property syn_probe, value 1, to net pc[2]Adding property syn_probe, value 1, to net pc[3]....@N|Added probe pc_keep_probe_1[0] on pc_keep[0] in eight_bit_uc @N|Also padding probe pc_keep_probe_1[0] @N|Added probe pc_keep_probe_2[1] on pc_keep[1] in eight_bit_uc@N|Also padding probe pc_keep_probe_2[1] @N|Added probe pc_keep_probe_3[2] on pc_keep[2] in eight_bit_uc



Chapter 4: Advanced Techniques Inserting Probes

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Adding Probe Attributes InteractivelyThe following procedure shows you how to insert probes by adding the syn_probe attribute with SCOPE. Alternatively, you can add the attribute in the source code, as described in Specifying Probes in the Source Code on page 4-38.

1. Open SCOPE and click Attributes.

2. Push down as necessary in an RTL view, and select the net for which you want to insert a probe point.

Do not insert probes for output or bidirectional signals. If you do, you see warning messages in the log file.

3. Do the following to add the attribute:

– Drag the net to SCOPE.

– Add the prefix n: to the net name in SCOPE. If you are adding a probe to a lower-level module, the name is created by concatenating the names of the hierarchical instances.

– If you want to attach probes to part but not all of a bus, make the change in the Object column. For example, if you enter n:UC_ALU.longq[4:0] instead of n:UC_ALU.longq[8:0], the software only inserts probes where specified.

– Select syn_probe in the Attribute column, and type 1 in the Value column.

– Add the constraint file to the project list.

4. Rerun synthesis.

5. Open a Technology view and check the probe wires that have been inserted. You can use the Ports tab of the Find form to locate the probes.

The software adds I/O pads for the probes. The following figure shows some of the pads in the Technology view and the log file entries.



Inferring RAMs Chapter 4: Advanced Techniques

Inferring RAMsThere are two methods of handling RAMs: instantiation and inference. The software can automatically infer RAMs if they are structured correctly in your source code. For details, see the following sections:

• Inference vs. Instantiation

• Structuring RAMs for Inference

• Coding Altera RAMs for Inference

• Coding Xilinx Block RAMs for Inference

Adding property syn_probe, value 1, to net pc[0]Adding property syn_probe, value 1, to net pc[1]Adding property syn_probe, value 1, to net pc[2]Adding property syn_probe, value 1, to net pc[3]....@N|Added probe pc_keep_probe_1[0] on pc_keep[0] in eight_bit_uc @N|Also padding probe pc_keep_probe_1[0] @N|Added probe pc_keep_probe_2[1] on pc_keep[1] in eight_bit_uc@N|Also padding probe pc_keep_probe_2[1] @N|Added probe pc_keep_probe_3[2] on pc_keep[2] in eight_bit_uc



Chapter 4: Advanced Techniques Inferring RAMs

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Inference vs. InstantiationThere are two methods to handle RAMs: instantiation and inference. Many FPGA families provide technology-specific RAMs that you can instantiate in your HDL source code. The software supports instantiation, but you can also set up your source code so that it infers the RAMs. The following table sums up the pros and cons of the two approaches

Structuring RAMs for InferenceRead through the limitations before you start. See Inference vs. Instantia-tion on page 4-42 for information.

1. Structure the assignment to a VHDL signal/Verilog register as follows:

– Define it as an indexed array or a case structure

– Control the structure with a clock edge and a write enable.

Inference in Synplify Pro Instantiation

AdvantagesPortable coding styleAutomatic timing-driven synthesisNo additional tool dependencies

AdvantagesMost efficient use of the RAM primitives of a specific technologySupports all kinds of RAMs

LimitationsGlue logic to implement the RAM might result in a sub-optimal implementation.Can only infer synchronous RAMsNo support for address wrappingNo support for RAM enables, except for write enablePin name limitations means some pins are always active or inactive

LimitationsSource code is not portable because it is technology-dependent.Limited or no access to timing and area data if the RAM is a black box.Inter-tool access issues, if the RAM is a black box created with another tool.




2. For a single-port RAM, make the address for indexing the write-to the same as the address for the read-from. The following figure and code example illustrate how Synplify Pro infers a single-port RAM.

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;

entity ramtest isport (q : out std_logic_vector(3 downto 0);

d : in std_logic_vector(3 downto 0);addr : in std_logic_vector(2 downto 0);we : in std_logic;clk : in std_logic);

end ramtest;

architecture rtl of ramtest istype mem_type is array (7 downto 0) of std_logic_vector

(3 downto 0);signal mem : mem_type;

beginq <= mem(conv_integer(addr));process (clk, we, addr) begin

if rising_edge(clk) thenif (we = '1') then

mem(conv_integer(addr)) <= d;end if;





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3. For a dual-port RAM, make the write-to and read-from addresses different. The following figure and code example illustrate how Synplify Pro infers a single-port RAM.

module ram16x8(z, raddr, d, waddr, we, clk);output [7:0] z;input [7:0] d;input [3:0] raddr, waddr;input we;input clk;reg [7:0] z;reg [7:0] mem0, mem1, mem2, mem3, mem4, mem5, mem6, mem7;reg [7:0] mem8, mem9, mem10, mem11, mem12, mem13, mem14, mem15;always @(mem0 or mem1 or mem2 or mem3 or mem4 or mem5 or mem6 or

mem7 or mem8 or mem9 or mem10 or mem11 or mem12 or mem13 ormem14 or mem15 or raddr)

begincase (raddr[3:0])4'b0000: z = mem0;4'b0001: z = mem1;4'b0010: z = mem2;4'b0011: z = mem3;4'b0100: z = mem4;4'b0101: z = mem5;4'b0110: z = mem6;4'b0111: z = mem7;4'b1000: z = mem8;4'b1001: z = mem9;4'b1010: z = mem10;4'b1011: z = mem11;4'b1100: z = mem12;4'b1101: z = mem13;4'b1110: z = mem14;4'b1111: z = mem15;

endcaseend




always @(posedge clk) beginif(we) begin

case (waddr[3:0])4'b0000: mem0 = d;4'b0001: mem1 = d;4'b0010: mem2 = d;4'b0011: mem3 = d;4'b0100: mem4 = d;4'b0101: mem5 = d;4'b0110: mem6 = d;4'b0111: mem7 = d;4'b1000: mem8 = d;4'b1001: mem9 = d;4'b1010: mem10 = d;4'b1011: mem11 = d;4'b1100: mem12 = d;4'b1101: mem13 = d;4'b1110: mem14 = d;4'b1111: mem15 = d;

endcaseendendendmodule

4. Optimize your RAMs according to the vendor and technology family.

– For Altera-specific details, see Coding Altera RAMs for Inference on page 4-46.

– For Xilinx-specific details, see Coding Xilinx Block RAMs for Inference on page 4-49.

5. For RAMs where inference might not be the best solution, either

– Implement them as regular logic using the syn_ramstyle attribute with a value of registers. You might want to do this is you have to conserve RAM resources.




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– Instantiate RAMs (using the black box methodology) where inference might not be the best solution. For example, in cases where RAM is implemented in two cells instead of one because Synplify Pro does not currently support address wrapping and the RAM address range spans the word limit of the primitive. If the address range is 8 to 23 and the RAM primitive is 16 words deep, the software implements the RAM as two cells, even though the address range is only 16 words deep. Refer to the list of limitations in Inference vs. Instantiation on page 4-42 and the vendor-specific information referred to in the previous step to determine whether you should instantiate RAMs.

6. Synthesize your design.

The software infers RAMs from the source code. If the number of words in the RAM primitive is less than the required address range, the software implements the RAM in two RAM cells, leaving the extra addresses unused.

Coding Altera RAMs for InferenceSynplify Pro supports single-port RAMs for the FLEX10K family and single-port or dual-port RAMs for the FLEX10KE, APEX20K, and 20KE families. It inserts bypass logic to resolve a read/write behavior difference between the RTL and post-synthesis gate-level simulations. There is a half cycle difference between the two: the post-RTL simulation shows memory updates occurring on the positive edge of the system clock, and the post-synthesis simulation shows memory updates on the negative edge. The following procedure shows you how to set up your code.

1. Structure your source code as described in Structuring RAMs for Inference on page 4-42.

2. Include an explicit read address register.

The address must be registered to implement a synchronous RAM in an LPM. You do not need an explicit address for the 10KE family.




3. To eliminate the insertion of bypass logic, register the output of the RAM. The following example defines a register, Q, for this purpose:

module ram_test(q, a, d, we, clk);output[7:0] q;input [7:0] d;input [6:0] a;input we, clk;//Register the RAM output to eliminate glue logicreg [7:0] q;reg [6:0] read_add;reg [7:0] mem [127:0];always @(posedge clk) beginq = mem[read_add];end

always @(posedge clk) beginif(we)//Register RAM data and read addressmem[read_add] <= d;read_add <= a;

endendmodule

If you run synthesis on this example, the software creates a single-port, synchronous RAM, implemented with as few registers as possible.

4. If you are not concerned about the insertion of glue logic, do not register the RAM output. For example:

module ram_test(q, a, d, we, clk);output[7:0] q;input [7:0] d;input [6:0] a;input we, clk;reg [6:0] read_add;reg [7:0] mem [127:0];assign q = mem[read_add];




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always @(posedge clk) beginif(we)//Register RAM data and read addressmem[read_add] <= d;read_add <= a;

endendmodule

If you synthesize this example, the software creates a bypass mux to resolve the read/write simulation behavior on the positive and negative edges of the clock.

5. If your RAM resources are limited, disable RAM inferencing by doing the following:

– Attach the syn_ramstyle attribute to the output signal of the RAM, or the declaration of the memory array. In this example, mem is the declaration of the memory array:

reg [7:0] mem [127:0];

– Set the value of the attribute to registers. This implements the components as flip-flops and logic instead of RAM.

6. Run synthesis.

The software generates Altera-specific RAMs. For FLEX10K designs, it generates single port synchronous RAMs. For FLEX10KE, APEX20K, and 20KE designs, it generates either single or dual-port RAMs with asynchronous READs. When source code is written as a single port RAM, the software implements it as a dual-port RAM with single port RAM functionality, using the LPM_RAM_DQ:ALTDPRAM primitive.




Coding Xilinx Block RAMs for InferenceThe software does not currently infer block RAMs for Virtex designs automatically; you have to use an attribute. The software inserts bypass logic to resolve a read/write behavior difference between the RTL and post-synthesis gate-level simulations. It inserts the glue logic because it does not know the output at the read port when the read address and the write address access the same memory location. The following procedure shows you how to set up your code with an explicit read address register.

1. Include an explicit read address register for Block Select RAMs in the code.

– Add code like the following for a single-port RAM:

always @(posedge clk)if(we)

mem[addr] = din;

always @(posedge clk)addr_reg = addr;

assign dout = mem[addr_reg]




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– Add code like the following for a dual-port RAM:

always @(posedge clk)if(we)

mem[waddr] = din;

always @(posedge clk)raddr_reg = raddr;

assign dout = mem[raddr_reg]

2. To prevent the insertion of glue logic, add the syn_ramstyle=”no_rw_check” attribute.

By default, the software inserts glue logic when the read and write addresses access the same memory location, because it does not know the output of the read port. The glue logic prevents a mismatch between the RTL and post-synthesis simulation results.

3. To infer Virtex block RAM, add the syn_ramstyle=”block_ram”attribute to the register signal in your source code, or to the output signal of the RAM in SCOPE.

4. For the following cases which Synplify Pro does not currently support, consider using instantiation:

– RAMs with enable signals, RAM resets, or initialization settings.

– Pins might be inaccessible: read enable pins are always active, and reset pins are always inactive.

– Dual port RAMs with read/write on a port.

5. Run synthesis.

+ Glue logic to resolve read/write discrepancies




The software implements the circuit using RAM16X1S, RAM32X1S, and RAM16X1D Xilinx primitives. If a RAM block is more complex than a single 16x1 primitive, the software creates the necessary write enable and data multiplexing logic to implement the circuit with multiple RAM blocks.

Specifying RAM Implementation StylesYou can influence how RAMs are inferred with the syn_ramstyle attribute. The valid values vary slightly, depending on the technology you use. Check the Synplify Pro Reference Manual for details.

1. If you do not want to use RAM resources, attach the syn_ramstyle attribute with a value of registers to the RAM instance name or to the signal driven by the RAM.

Use this value for small RAMs. The software implements the RAMs according to the technology. They can be implemented as registers (Altera, Xilinx), LPMs (Atmel, Cypress), dedicated RAM resources (QuickLogic) or synchronous dual port memory cells (Lucent).

2. To use the dedicated memory resources on the FPGA (Altera technologies), do the following:

– Set syn_ramstyle to block_ram.

– For Flex10K architectures, register the read address, because the technology does not support dual port RAMs.

– If you do not want glue logic created, register the RAM output.

The software implements the RAMS as EABs or ESBs, depending on the technology.

3. To implement RAMs using dedicated Block SelectRAM+ in Xilinx Virtex technologies, do the following. To use distributed memory, see the next step.

– Set syn_ramstyle to block_ram.

– Register the read address, because the technology is fully synchronous.



Chapter 4: Advanced Techniques Classic Interface

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– If you do not want to generate glue logic for dual port RAMs, either register the RAM output or set syn_ramstyle to no_rw_check. Use this attribute value only if you do not care about a read/write check.

4. To implement RAMs using distributed memory in Xilinx technologies, you can set syn_ramstyle to select_ram. If you do not set this value explicitly, the software automatically uses this value, because it is the default.

Classic InterfaceFor the look and feel of the Synplify classic interface, you can run Synplify Pro in this mode.

1. To switch to the classic interface, select Options->Project View Options.

2. Check the box for Synplify Classic View, and click OK.



Classic Interface Chapter 4: Advanced Techniques

You see the standard Synplify interface (illustrated in the following figure) instead of the Synplify Pro user interface. Some new features might not be available as buttons on the interface. You will have to use menu or Tcl commands to access them. In addition, you will not be able to run multiple implementations in this mode.



Chapter 4: Advanced Techniques Working with Altera Designs

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Working with Altera DesignsThis section includes some Altera technology-specific tips for optimizing your design. These tips are in addition to the general guidelines described in Design Guidelines on page 3-106. This section discusses the following topics that are specific to Altera technologies:

• APEX Design Tips

• FLEX Design Tips

• Instantiating LPMs

• Inferencing ROMs

• Working with Altera EABs and ESBs

• Packing I/O Cell Registers

In addition, you can use the techniques described in these other topics, which apply to other vendors as well as Altera:

• Defining Black Boxes for Synthesis

• Inferring RAMs

APEX Design TipsUse these techniques when working with APEX designs:

• Set the option to map to ATOM primitives. When the software maps elements to ATOM primitives, the Quartus tool can skip synthesis, thus reducing run time. The pin assignments, part information, and cliquing information are forward-annotated to Quartus.

• If you have a large design and need to conserve flip-flops, pack the registers into Apex I/O cells. See Packing I/O Cell Registers on page 4-58 for more information.



Working with Altera Designs Chapter 4: Advanced Techniques

FLEX Design TipsThe software automatically maps logic to Altera cells like LCELL, carry and cascade primitives. However, the default setting for the Max+ Plus II place-and-route tool is to do technology mapping. You must reconfigure Max+ Plus II to take full advantage of the Synplify Pro results.

If you are not going to use the synthesis technology mapping, turn off the Map logic to Lcells option before you run synthesis.

Instantiating LPMsAltera LPMs (Library of Parameterized Modules) are technology-indepen-dent logic functions that are parameterized for scalability and adapt-ability. There are two ways to instantiate LPMs in your source code: as black boxes, or by using prepared components. The first method can be used to instantiate any Altera LPM, but requires more coding. The second method, the prepared components method, uses generics instead of attributes to specify design parameters. It is simpler to use, but you can not use it on all LPMs. In addition, you can only use this method with VHDL source code.

1. To instantiate an LPM as a black box in Verilog or VHDL, do the following:

– Define a black box for the LPM.

– Assign LPM-specific attributes like LPM_TYPE, LPM_WIDTH, and LPM_WIDTHAD.

– Instantiate the LPM in the higher-level module.

For details about handling black boxes, see Defining Black Boxes for Synthesis on page 4-15.

2. To instantiate an LPM using the prepared components method, do this in VHDL:

– Specify the appropriate library and use clauses.

– Instantiate the components.

– Assign the ports and values for the generics.




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Inferencing ROMs The software automatically infers ROMs from CASE statements in the RTL code. This procedure shows you how to control the implementation of ROM in APEX and FLEX designs with the syn_romstyle attribute.

1. To implement the ROM structure as a block, do the following:

– Apply the syn_romstyle attribute to the signal output value.

– Set the value of the attribute to block_ROM. You can set the attribute in the source code, SCOPE, or directly in the constraint file. See Adding Attributes and Directives on page 3-95 for information.

– Run synthesis.

The software implements all small ROMs (less than seven address bits) as logic. It implements the larger ROM structures as extended system blocks (ESBs) in APEX designs and extended array blocks (EABs) in FLEX designs.

If you have to conserve ROM resources, you can turn off ROM imple-mentation globally with the altera_auto_use_esb and altera_auto_use_eab attributes, and then specify the ROMs you want implemented as block ROMs with the syn_romstyle attribute.

2. To implement the ROM structure as discrete logic, do the following:

– Apply the syn_romstyle attribute to the signal output value.

– Set the value of the attribute to logic.

Format Example

Verilog reg [3:0] z /* synthesis syn_romstyle=”block_rom” */;

VHDL signal z : std_logic_vector(3 downto 0);attribute syn_romstyle : string;attribute syn_romstyle of z : signal is “block_rom”;

Constraint file syntax define_attribute {z_20[3:0]} syn_romstyle {block_rom}



Working with Altera Designs Chapter 4: Advanced Techniques

– Run synthesis.

The software implements all small ROMs (less than seven address bits) and all other ROMs with this attribute as discrete logic primi-tives instead of blocks.

Working with Altera EABs and ESBsAn Altera EAB is an extended array block, in FLEX10K designs. An ESB is an extended system block in Apex 20K and 20KE designs.

1. Attach the altera_implement_in_eab attribute to the component you want to implement as an EAB, and set the value to 1.

2. To implement an ESB, do the following:

– Make your design hierarchical, and instantiate the module/entity in the ESB at the top level.

– Attach the altera_implement_in_esb attribute to the component.

– Set the value to true.

When this attribute is set, the software implements the logic as a PTERM in an extended system block.

3. Run synthesis.

For FLEX10KE, APEX20K, and 20KE designs, Synplify Pro generates Altera-specific single or dual-port RAMs with asynchronous READs. When source code is written as a single port RAM, the software implements it as a dual-port RAM with single port RAM functionality, using the LPM_RAM_DQ:ALTDPRAM primitive.

Format Example

Verilog reg [3:0] z /* synthesis syn_romstyle=”logic” */;

VHDL signal z : std_logic_vector(3 downto 0);attribute syn_romstyle : string;attribute syn_romstyle of z : signal is “logic”;

Constraint file syntax define_attribute {z_20[3:0]} syn_romstyle {logic}




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Packing I/O Cell RegistersYou can improve input or output path timing in APEX designs by packing registers into APEX I/O cells with the syn_useioff attribute.

1. To pack the registers globally, set syn_useioff=1 on the top level module or architecture. Specify the attribute in the source code, SCOPE, or directly in the constraint file.

2. To set the attribute locally, set syn_useioff=1 on a port.

The software packs registers with asynchronous clear pins and asynchronous preset pins for APEX20KE I/O cells. The software can infer the I/O cell if you have a preset or clear, and an embedded flip-flop in the I/O cell.

Format Example

Verilog module test(d, clk, q) /* synthesis syn_useioff=1 */;

VHDL architecture rtl of test is attribute syn_useioff : boolean;attribute syn_useioff of rtl : architecture is true;

Constraint file syntax define_global_attribute syn_useioff 1

Format Example

Verilog module test(d, clk, q);input [3:0] d;input clk;output [3:0] q /* synthesis syn_useioff=1 */;reg q;

VHDL entity test is port (d : in std_logic_vector (3 downto 0);clk : in std_logic;q : out std_logc_vector (3 downto 0);attribute syn_useioff : boolean;attribute syn_useioff of q : signal is true;end test;

Constraint file syntax define_attribute {p:q[3:0]} syn_useioff 1



Working with Xilinx Designs Chapter 4: Advanced Techniques

Working with Xilinx DesignsThis section contains tips for working with Xilinx designs, including the following:

• Designing for Xilinx Architectures

• Instantiating CoreGen/PCI Cores

• Using Clock DLLs in Virtex Designs

• Packing Registers for I/Os

• Controlling Placement with RLOCs

• Instantiating Special I/O Standard Buffers for Virtex

• Inferring Dynamic Shift Register Lookup (SRL) Tables

There is additional Xilinx-specific information in Inferring RAMs on page 4-41 and Using the Xilinx Modular Flow on page 4-71.

Designing for Xilinx ArchitecturesThe tips listed here are in addition to the technology-independent design tips described in Design Guidelines.

• For critical paths in XC4000 family designs, attach the xc_fast attribute to the I/Os.

• To make sure that frequency constraints from register to output pads are forward annotated to the Xilinx P&R tools, add default input_delay and output_delay constraints of 0.0 in the synthesis software. When the constraints are passed to the P&R tools, the frequency constraints are forward-annotated as PERIOD constraint (register-to-register) and OFFSET constraints (input-to-register and register-to-output). The P&R tools use these constraints.

• Run successive P&R iterations with progressively tighter timing constraints to get the best results possible.



Chapter 4: Advanced Techniques Working with Xilinx Designs

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Instantiating CoreGen/PCI CoresPredesigned IP cores save on design effort and improve performance. The process for handling IP cores is slightly different for CoreGen and Virtex PCI cores. Refer to the Synplify Flow for Xilinx Virtex Real PCI 64/66 Core application note on the Synplicity Support web site for details about working with PCI cores. The following procedure describes how to instan-tiate a CoreGen module.

1. Define the core as a black box by adding the syn_black_box attribute to the module definition line.

module ram64x8(din, addr, we, clk, dout)/* synthesis syn_black_box*/;

input[7:0] din;input [5:0] addr;input we, clk;output [7:0] dout;

endmodule;

2. Make sure the bus format matches the bus format in the core generator, using the syn_edif_bit_format and syn_edif_scalar_format directives if needed.

module ram64x8(din, addr, we, clk, dout)/* synthesis syn_black_box syn_edif_bit_format = “%u<%i>”syn_edif_scalar format =”%u” */;

3. Instantiate the black box in the module or architecture.

ram64x8 r1(din, addr, we, clk, dout);

4. Synthesize the design.

Using Clock DLLs in Virtex DesignsThe software can automatically use the CLKDLL (Clock Delay Locked Loop) primitive if you use the xc_clockbuftype attribute.

1. To specify the attribute in SCOPE, use the procedure described in Adding Attributes in SCOPE on page 3-97 to add xc_clockbuftype attribute to the ports.




The software infers a buffer called BUFGDLL that includes the CLKDLL primitive. BUFGDLL consists of an IBUFG followed by a CLKDLL followed by a BUFG.

The output EDIF netlist contains text like the following:

(instance clk_ibuf (viewRef PRIM (cellRef BUFGDLL (libraryRef VIRTEX) ) )

2. To specify the attribute in Verilog, add the attribute as shown in this example.

module test(d, clk, rst, q);input [1:0] d;input clk /* synthesis xc_clockbuftype = “BUFGDLL” */, rst;output [1:0] q;//other coding

3. To specify the attribute in VHDL, add the attribute as shown in this example.

entity test_clkbuftype isport (d: in std_logic_vector(3 downto 0);

clk, rst : in std_logic;q : out std_logic_vector(3 downto 0)

);attribute xc_clockbuftype of clk : signal is “BUFGDLL”;end test_clkbuftype




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Packing Registers for I/OsWhen a register drives an input or output, you might want to pack it in an IOB instead of a CLB. For example, when

• The chip interfaces with another, and you have to minimize the register-to-output or input-to-register delay.

• You have limited CLB resources, and packing the registers in an IOB can free up some resources.

To pack registers in an IOB, you set the syn_useioff attribute.

1. To globally embed all the flip-flops into IOBs, attach the syn_useioff attribute to the module in one of these ways:

– Add the attribute in SCOPE, attaching it to the module, architecture, or the top level. Check the Enable box, set the Attribute column to syn_useioff, the Object column to <global>, and the attribute value to 1. The constraint file syntax looks like this:

define_global_attribute syn_useioff 1

– To add the attribute in the Verilog source code, add this syntax to the top level:

module global_test(d, clk, q) /* synthesis syn_useioff = 1 */;

– To add the attribute in the VHDL source code, add this syntax to the top level architecture declaration:

architecture rtl of global_test isattribute syn_useioff : boolean;attribute syn_useioff of rtl : architecture is true;

For details about attaching attributes in SCOPE and in the source code, see Adding Attributes and Directives on page 3-95.

When set globally, all boundary registers and (OE) registers associ-ated with the data registers are marked with the Xilinx IOB property. This property is forward annotated in the EDIF netlist, and used by the Xilinx place-and-route tools to determine how the registers are packed. All marked registers are packed in the corresponding IOBs.




2. To apply syn_useioff to individual ports, use one of these methods:

– Add the attribute in SCOPE, attaching it to the ports you want to pack, and set the attribute value to 1.The resulting constraint file syntax looks like this:

define_attribute {p:q[3:0]} syn_useioff 1

– To add the attribute in the Verilog source code, add this syntax:

module test is (d, clk, q);input [3:0] d;input clk;output [3:0] q /* synthesis syn_useioff = 1 */;reg q;

– To add the attribute in the VHDL source code, add syntax as shown inside the entity for the local port:

entity test isport (d : in std_logic_vector(3 downto 0);

clk : in std_logicq : out std_logic_vector(3 downto 0);

attribute syn_useioff : boolean;attribute syn_useioff of q : signal is true;end test;

The software attaches the IOB property as described in the previous step, but only to the specified flip-flops. Packing for ports without the attribute is determined by timing preferences. If a register is to be packed into an IOB, the IOB property is attached and forward annotated. If it is to be packed into a CLB, the IOB property is not forward annotated.

In Virtex designs where Synplify Pro duplicates OE registers, setting the syn_useioff attribute on a boundary register only enables the associated OE register for packing. The duplicate is not packed, but placed in CLBs. The packed registers are used for data path, and the CLB registers are used for counter implementation.

In Virtex designs where a shift register is at a boundary edge and the syn_useioff attribute is enabled, the software extracts only the initial or final SRL16 shift register from the LUT for packing. The shift register that is implemented in the technology view is smaller because of the extraction.




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Controlling Placement with RLOCsRLOCs are relative location constraints. They let you control placement in critical sections, thus improving performance. You specify RLOCs using three attributes, xc_map, xc_rloc, and xc_uset. As with other attributes, you can define them in the source code, or in SCOPE.

1. Create the modules you want to constrain, and specify the kind of Xilinx primitive you want to map them to, using the xc_map attribute. The modules can have only one output.

This Verilog example shows a 4-input Spartan XOR module:

module fmap_xor4(z, a, b, c, d) /* synthesis xc_map=fmap*/ ;output z;input a, b, c, d;assign z = a ^ b ^c ^d;endmodule

This is the equivalent VHDL example:

library IEEE;use IEEE.std_logic_1164.all;entity fmap_xor4 is

port (a: in std_logic;b: in std_logic;c: in std_logic;d: in std_logic);

end fmap_xor4;

architecture rtl offmap_xor4 isattribute xc_map : STRING;attribute xc_map of rtl: architecture is “fmap”;begin

z <= a xor b xor c xor d;end rtl;

2. Instantiate the modules you created at a higher hierarchy level.

Family xc_map Value Max. Module Inputs

XC4000, Spartan fmaphmap

4 3

Virtex lut 4




3. Group the instances together (xc_uset attribute) and specify the relative locations of instances in the group with the xc_rloc attribute.

This example shows the Verilog code for the top-level CLB that includes the 4-input module in the previous example:

module clb_xor9(z, a) ;output z;input [8:0] a;wire x03, x47;//Code for XC4000 or Spartanfmap_xor4 x03 /*synthesis xc_uset=”SET1” xc_rloc=”R0C0.f” */

(z03, a[0], a[1], a[2], a[3]);fmap_xor4 x47 /*synthesis xc_uset=”SET1” xc_rloc=”R0C0.g” */

(z47, a[4], a[5], a[6], a[7]);hmap_xor3 zz /*synthesis xc_uset=”SET1” xc_rloc=”R0C0.h” */

(z, z03, z47, a[8]);//Code for Virtex differs because it includes the slicefmap_xor4 x03 /*synthesis xc_uset=”SET1” xc_rloc=”R0C0.S0” */

(z03, a[0], a[1], a[2], a[3]);fmap_xor4 x47 /*synthesis xc_uset=”SET1” xc_rloc=”R0C0.S0” */

(z47, a[4], a[5], a[6], a[7]);hmap_xor3 zz /*synthesis xc_uset=”SET1” xc_rloc=”R0C0.S1” */

(z, z03, z47, a[8]);endmodule

4. Create a top-level design and instantiate your design.




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Instantiating Special I/O Standard Buffers for VirtexThe software supports all the I/O Virtex standards, like HSTL_*, CTT, AGP, PC133_*, PC166_*, etc. You can either instantiate these primitives directly, or specify them with the xc_padtype attribute.

1. To instantiate I/O buffers, use code like the following to specify them.

module inst_padtype(a, b, clk, rst, en, bidir, q) ;input [0:0] a, b;input clk, rst, en;inout bidir;output [0:0] q;

reg [0:0] q_int;wire a_in, bidir_in, q_in;IBUF_AGP i1 (.O(a_in), .I(a) ) ;IOBUF_CTT i2 (.O(q_in), .IO(bidir) , .I(Q_int), .T(en) ) ;OBUF_F_12 o1 (.O(q), .I(q_in) ) ;

always @(posedge clk or posedge rst)if (rst)

q_int = 1’b0;else

q_int = a_in & b;

endmodule




2. To specify the I/O buffers with an attribute, add the attribute in SCOPE (refer to Setting Constraints with SCOPE on page 3-28 for details) or in the source code, as the following example illustrates.

module inst_padtype(a, b, clk, rst, en, bidir, q) ;input [0:0] a /* synthesis xc_padtype = “IBUF_AGP” */, b;input clk, rst, en;inout bidir /* synthesis xc_padtype = “IOBUF_CTT” */;output [0:0] q /* synthesis xc_padtype = “OBUF_F_12” */;

reg [0:0] q_int;

assign q = bidir;assign bidir = en ? q_int : 1’bz;always @(posedge clk or posedge rst)

if (rst)q_int = 1’b0;

elseq_int = a_in & b;

endmodule

Inferring Dynamic Shift Register Lookup (SRL) TablesThe software infers dynamic and static sequential shift components in Xilinx Virtex architectures.

1. Set up the HDL code for the sequential shift components. See VHDL Example on page 4-69 and Verilog Example on page 4-70 for examples.

Note the following:

– The new component represents a set of two or more registers that can be shifted left (from a low address to a higher address).

– The contents of only one register can be seen at a time, based on the read address.

– For static components, the software only taps the output of the last register. The read address of the inferred component is set to a constant.

2. If you do not want the components automatically mapped to Xilinx SRL16 primitives, set the syn_srlstyle attribute value to registers.




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If you do not specify the attribute, the software assumes that the attribute is set with a value of select_srl, which maps the components to SRL16 primitives. When you specifically set the attribute to regis-ters, the components are implemented as registers.

3. Run synthesis.

After compilation, the software displays the components as seqShift components in the RTL view. The RTL component has the following pins: raddr (read address), data (data in), we (write enable), clk (clock), a_rst (asynchronous reset), s_rst (synchronous reset), and dout (data out). Currently, the a_rst and s_rst pins are not used. The following figure shows the seqshift component in the RTL view.

In the technology view, the components are implemented as SRL16 primitives or registers, depending on the attribute values you set.




VHDL ExampleThis is a VHDL example of a shift register with no resets. It has four 8-bit wide registers and a 2-bit wide read address. Registers shift when the write enable is 1.

library IEEE;use IEEE.std_logic_1164.all;

entity srltest isport ( inData: std_logic_vector(7 downto 0);

clk, en : in std_logic;outStage : in integer range 3 downto 0;outData: out std_logic_vector(7 downto 0)

);end srltest;

architecture rtl of srltest istype dataAryType is array(3 downto 0) of std_logic_vector(7

downto 0);signal regBank : dataAryType;

beginoutData <= regBank(outStage);process(clk, inData)

beginif (clk'event and clk = '1') then

if (en='1') thenregBank <= (regBank(2 downto 0) & inData);end if;

end if;end process;

end rtl;




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Verilog Examplemodule test_srl(clk, enable, dataIn, result, addr);input clk, enable;input [3:0] dataIn;input [3:0] addr;output [3:0] result;reg [3:0] regBank[15:0];integer i;

always @(posedge clk) beginif (enable == 1) begin

for (i=15; i>0; i=i-1) beginregBank[i] = regBank[i-1];

endregBank[0] = dataIn;

endend

assign result = regBank[addr];

endmodule



Using the Xilinx Modular Flow Chapter 4: Advanced Techniques

Using the Xilinx Modular Flow

Introduction to the Modular FlowAs designs become more complex, designers need to partition large designs into smaller modules to manage the complexity, leverage team design resources, and handle design changes more efficiently. Synplify Pro supports a modular flow for Xilinx Virtex devices that allows designers to address these issues.

With the Xilinx Virtex modular flow, a team leader partitions the design and workload to work in parallel on modules that are subordinate to the top-level design. The modular flow consists of three design phases: Initial Design Budgeting, Active Implementation, and Final Assembly. The following figure illustrates how to use Synplify Pro for synthesis within this flow to accomplish tasks in the first two phases.

The steps in each phase are briefly described in the following sections, with emphasis on the tasks done with Synplify Pro.

Initial Design BudgetingIn this phase, the team leader uses the team design model to partition the design into modules and define the top-level design and global design constraints. Based on initial floorplanning, the lead team designer assigns physical locations to the modules.

Planning

Design Entry Module P&R

Module Synthesis

Top-level Synthesis Simulation

Top-level P&R

Initial Design Budgeting Final Assembly

Active Implementation

Xilinx Modular Flow Phases and TasksSynplify Pro Tasks in the Flow



Chapter 4: Advanced Techniques Using the Xilinx Modular Flow

LO

Planning Using the team design model, the team leader defines the HDL top-level design, the global design constraints, and determines the positions of each of the modules by doing some preliminary floorplanning. The team leader partitions the design into smaller self-contained modules or struc-tures, and assigns the modules to different teams or designers. This planning stage can be merged with the next stage of Design Entry.

1. Partition the design into smaller self-contained modules or structures.

2. Use initial floorplanning to assign them to specific physical locations on the target device.

3. Allocate global resources like clock buffers.

4. Assign each module to a designer or a design team.

This modular flow uses a simple example to illustrate the flow. The design consists of a top-level design with two lower-level modules, mux and flop. See Design Files and Area Floorplanning on page 4-81 for the files.

Design Entry (Team Leader)The team leader must

1. Create the following files and add them to a project:

– A top-level design file. The HDL source code for the top-level design contains the top-level module with all the global logic such as clock resources, inter-module logic connections, and

Top-Level Design

Flop

Mux




connections between I/O ports and modules. For the top-level file used as an example here, see Top-Level Design File on page 4-82.

– A file for each module. This file is a black box wrapper for the module and lists the inputs and outputs. It also contains attributes to declare the module a black box (syn_black_box) and set the physical location of the module, based on initial floorplanning (xc_modular_region). For information about generating the area numbers for xc_modular_region, see Determining the Area Range for xc_modular_region on page 4-85. For the module files used in this example, see Module Mux File on page 4-83 and Module Flop File on page 4-84.

– A top-level constraint file. You can use SCOPE to set global clock constraints. If there is a conflict between the global clock constraint and a clock constraint set on a module, the global clock constraint is used.

– Synthesize the design. Make sure you set Technology to Xilinx Virtex or Virtex2 and check the Modular Flow checkbox on the Device tab of the Implementation Options form.




LO

When you check Modular Flow, the software generates the directory structure needed for the flow in the Xilinx place-and-route tool.

The software creates top-level .edif and .ncf files, which it places in the top-level directory. It issues warnings if it finds a module that is instantiated more than once at the top level.

2. Generate a top-level .ngo file that contains the top-level area constraints.

– Start the Xilinx place-and-route tool.

– Go to the top_level directory and run ngdbuild in initial mode. Use this syntax and type the command at the command line:

ngdbuild -modular initial <toplevel>.edf

To run our example, the command is ngdbuild -modular initial example_top.edf. This command generates a .ngd file and a .ngo file that contains the top-level area constraints for place and route.

3. Archive the directories, and give each designer or design team working on a module a copy of these files.

Currently empty, used for final assembly

Contains top-level EDIF netlist and top-level constraint file (.ncf)

Currently empty, used for completed modules

Currently empty, used for module design




Design Entry (Module Level)At this stage, the module designer must do the following:

1. Open the source code file(s) for the module you are responsible for, and delete the syn_black_box attribute. Do not remove the xc_modular_region attribute.

For example, if you are the designer responsible for the mux design, you open the source code file for this module and delete the syn_black_box attribute. From your perspective, it is no longer a black box, because you are going to create the internal logic for it.

2. Complete the internal logic design for the module.

Active ImplementationThe active implementation phase starts after the designer finishes the module-level design. This phase consists of module synthesis, top-level synthesis, and module-level placement and routing.

Module SynthesisThe advantage to using the modular design flow is the elimination of dependencies and the need for all teams to be done before an individual team can synthesize a module design with the overall design. Individual teams can synthesize their assigned modules with the top-level design without depending on the progress of other design teams. It allows the module designer to iterate the module design with the top level more frequently, and evolve the overall design and separate modules more efficiently.

Although this is module-level synthesis, you actually synthesize your module design with the top-level design, the top-level constraint file, wrapper files for other modules, and optional module-level constraint files. To use our example, if you are assigned to mux, you create HDL source code for it. You synthesize mux using the project created by the team leader, replacing the original mux wrapper file with the design you created. The project file includes the top-level design source code and constraint file, as well as the wrapper file for the flop module, which remains a black box from your perspective.




LO

1. Start with the project set up by the team leader and set device options in Synplify Pro with Project->Implementation Options. The module file is now updated to contain the design.

– On the Device tab, set the device to Xilinx Virtex or Xilinx Virtex2.

– Check the Modular Flow checkbox.

– On the Implementation Results tab, check that the name of the output netlist matches the name of the module you are actively synthesizing as it occurs in the top-level EDIF file, so that the name of the netlist for this module and the name in the top-level EDIF file are the same. For example, the name for the output file for mux must be mux.edf to match the name of the component in the top-level EDIF file.

– Set any other device options you want, and click OK.

The software issues warnings if it finds either of the following:

– A module that is instantiated more than once at the top level.

– Internal tristates. Unlike the regular design flow, in the modular flow the software cannot move internal tristates up to the top level because of the strict hierarchy limits required by this flow.

2. Compile the design with Run->Compile Only. You need to do this to initialize constraints for SCOPE.




3. Set module-level constraints if needed. Use the following procedure:

– Select the object in the RTL view. Right-click and select SCOPE->Edit Module Constraints to open a SCOPE window. Do not use the SCOPE icon, because that opens the top-level constraints file.

– Set the module-level constraints and save the file. The file name is prefixed by module_. For example, the constraint file generated for the mux module is called module_mux.sdc.

– Add it to the project. If there is a conflict between the global clock constraint (set at the top level) and a clock constraint set on a module, the global clock constraint is used.

4. Click the Run button to synthesize.

As the design continues to evolve, the top-level source files sometimes change to accommodate overall design objectives. Make sure to use the most current top-level files. If there are design changes at the top level, all design teams must be updated with the changes by the team leader.

The software generates the directory structure needed to continue the modular flow in the Xilinx place-and-route tool. For our example, you see the following directories after synthesizing mux with a black box for flop:

– constraint, which contains the constraint files for the design

– top_level_final, which is still empty, but will be used for final assembly

– top_Level, which contains example_top.edf, the EDIF netlist for the top level and example_top.ncf, the top-level place-and-route constraint file

– PIM (Physically Implemented Module), which is currently empty, but will be used to hold modules as they are completed

– mux, which contains mux.edf, the EDIF netlist for the top level, and mux.ncf, the place-and-route constraint file for the module

– flop, which is still empty, because flop is still a black box

Unless you synthesize the top level, you have now finished synthesis. The rest of the flow uses the Xilinx place-and-route tool.




LO

Top-level SynthesisOptionally, you can synthesize the top-level design as an intermediate check, although it is not necessary with the modular flow. This is because the top-level module contains the physical locations of the devices and all modules use the same top-level area constraint file. At this point, you have finished the synthesis phase. The rest of the flow uses the Xilinx place-and-route tool.

Module Placement and RoutingAfter synthesis, you use the Xilinx placement and routing tool (Xilinx Software Solutions Version 3.1I) to place and route the module. The completed module can be then be instantiated in the top-level design. Each module is placed and routed independently with the Xilinx P&R tool. The modules are developed in parallel, so the post-routing timing results of one module can be used with placement and routing constraints when you synthesize another module with Synplify Pro.

The place-and-route commands are included here for completeness. If you need more information about the commands, see the Xilinx software documentation.

You must run placement and routing from the command line, but you could create a script to automate this process.

1. Open the Xilinx place-and-route software.

2. Go to the module directory (in this case, the mux directory) and type the following at the command line to run the ngdbuild command in module mode:

ngdbuild -p <part_num> -modular module -active <module>.edf<path_to_top_level_ngo_file>

For our example, the command is

ngdbuild -p xcv50-6bg256 -modular module -active mux ..\top_level\example_top.ngo

This command runs the ngdbuild command in module mode. It uses the area constraints from the top-level .ngo file to build an .ngo file in the module directory.




3. Map the module with this command:

map <top_level_file>.ngd

For our example:

map example_top.ngd

This command uses the .ngo file in the module directory to generate .ngd and .ncd files in the module directory.

4. Place and route the module with the following command:

par -w <top_level_file>.ncd <top_level_file_par>.ncd

The second .ncd file is the placed and routed file that is generated by this command, so name it something distinct and meaningful to you. By not overwriting the original .ncd file, you can try different design options. The _par suffix is a convention that lets you keep track of when you generated the .ncd file. For our example, use this command:

par -w example_top.ncd example_par.ncd

5. Open the place-and-route tool and check your placement results with this command:

fpga_editor <top_level_file_par>.ncd

For our example, the name of the .ncd file is example_par.

6. Copy the lower-level module files into the PIM directory. From the module directory, type the following

pimcreate -ncd -w <top_level_file_par>.ncd<path_to_pim_directory> <module_file>

For the module file, just specify the name of the module file without any extensions. For example:

pimcreate -ncd -w example_par.ncd ..\PIM mux

This command creates a directory under PIM called mux, into which it copies the mux.ncd and mux.ngo files. The PIM directory is an interme-diate holding area where module designers deposit module files as they are completed. The PIM files are used for final assembly of the design.




LO

Final AssemblyAfter all subordinate modules have been synthesized separately, use their combined netlists to place and route the entire design.

1. Complete all the modules, and copy them to the PIM directory. See Module Synthesis on page 4-75 for details. At this point, you can do functional and timing simulation before placing and routing the top level with the Xilinx P&R tool.

2. Open a command prompt, and go to the top_level_final directory, and type the following:

ngdbuild -p <part_num> -modular assemble -pimpath<path_to_pim_dir> -use_pim <module_name><path_to_top_level_ngo_file>

This command runs ngdbuild in assembly mode, specifying each of the modules in the pim directory. You must repeat -use_pim<module_name> as many times as needed to specify all the modules in the design. For example:

ngdbuild -p xcv50-6bg256 -modular assemble -pimpath ..\PIM -use_pim mux -use_pim flop example_top.ngo

The command generates a top-level .ngd file that is a fully expanded design file.

3. Map the design with the following command. The command maps each module using the files in the pim directory.

map <top_level_file>.ngd

For our example:

map top.ngd

4. Place and route the design with the following command. The command uses the files in the PIM directory.

par -w <top_level_file>.ncd <top_level_file_par>.ncd

For example:

par -w example_top>.ncd example_par.ncd




5. Open the place-and-route tool and verify the locations of the modules with this command:


To use our example, you type the following:


Design Files and Area FloorplanningThis section contains the top-level design files for the example used in the modular flow and discusses how to estimate module area.




LO

Top-Level Design FileThis is the top-level file (example_top.vhd or example_top.v) used as an example in the modular design flow. It contains the ports for the whole design and instantiations of the two lower-level modules.

VHDLlibrary ieee;use ieee.std_logic_1164.all;

entity example_top is port (inmux : in std_logic_vector(3 downto 0);sel : in std_logic_vector(1 downto 0);reset : in std_logic;clk : in std_logic;output : out std_logic);

end example_top;

architecture beh of example_top is

component mux is port (inmux : in std_logic_vector(3 downto 0);sel : in std_logic_vector(1 downto 0);outmux : out std_logic);

end component;

component flop is port (inflop : in std_logic;clk : in std_logic;reset : in std_logic;outflop : out std_logic);

end component;

signal bridge : std_logic;

beginU0 : mux port map (inmux,sel,bridge);U1 : flop port map (bridge,clk, reset, output);end beh;




Verilogmodule modular_design_top (inmux, sel, reset, clk, out);

input [3:0] inmux;input [1:0] sel;input reset;input clk;output out;

wire bridge;

mux U0 (.inmux(inmux), .sel(sel), .outmux(bridge));flop U1 (.inflop(bridge), .outflop(out), .reset(reset),.clk(clk));

endmodule

Module Mux FileFor the module, the team leader creates a port map, declares the module as a black box, and specifies the physical location of the module on the FPGA (mux.vhd or mux.v). The syn_black_box attribute declares this module to be a black box, until the module designer deletes the attribute and creates the internals for the module. The xc_modular_region attribute speci-fies the range of CLBs (or slices in Virtex2 designs) on the FPGA into which this module can be placed. In this case, mux goes in the region between R1C1 and R5C5.




LO


entity mux is port (inmux : in std_logic_vector(3 downto 0);sel : in std_logic_vector(1 downto 0);outmux : out std_logic);

end mux;

architecture beh of mux is

attribute syn_black_box : boolean;attribute syn_black_box of beh : architecture is true;attribute xc_modular_region : string;attribute xc_modular_region of beh : architecture is

"CLB_R1C1:CLB_R5C5";

beginend beh;

Verilogmodule mux (inmux, sel, outmux) /* synthesis syn_black_boxxc_modular_region="CLB_R1C1:CLB_R5C5" */;

input [3:0] inmux;input [1:0] sel;output outmux;

endmodule

Module Flop FileFor the module, the team leader creates a port map, declares the module as a black box, and specifies the physical location of the module on the FPGA (flop.vhd or flop.v). The syn_black_box attribute declares this module to be a black box, until the module designer deletes the attribute and creates the internals for the module. The xc_modular_region attribute speci-fies the range of CLBs (or slices in Virtex2 designs) on the FPGA into which this module can be placed. In this case, flop goes in the region between R7C7 and R8C8.





entity flop is port (inflop : in std_logic;clk : in std_logic;reset : in std_logic;outflop : out std_logic);

end flop;

architecture beh of flop isattribute syn_black_box : boolean;attribute syn_black_box of beh : architecture is true;attribute xc_modular_region : string;attribute xc_modular_region of beh : architecture is

"CLB_R7C7:CLB_R8C8";

beginend beh;

Verilogmodule flop (inflop, outflop, reset, clk) /* synthesissyn_black_box xc_modular_region="CLB_R7C7:CLB_R8C8" */;

input inflop;input reset;input clk;output outflop;

endmodule

Determining the Area Range for xc_modular_regionYou determine the area range by first estimating the area of the module and then fitting it on to the FPGA along with the other modules.

1. Estimate the area of the module. You can use one of these methods:

– Often, the team leader has a rough idea of the area of the module. Use this rough area estimate to determine the area range on the FPGA.




LO

– Synthesize the lower-level modules with the modular design option turned off. The log file gives you the resource usage, which you can use to calculate the area of the module.

2. Determine where it should be placed on the FPGA, based on its size.

3. Indicate placement area range with row and column numbers, and use these numbers as the value of the xc_modular_region attribute.

– For Virtex designs, use this format: CLB_R<n>C<n>:CLB_R<n>C<n>. For example, CLB_R3C3:CLB_R8C8.

– For Virtex2 designs, use this format: SLICE_R<n>C<n>:SLICE_R<n>C<n>. For example, SLICE_R3C3:SLICE_R8C8.

Synplify Pro and Amplify Modular FlowsYou can also use the modular flow with the Amplify Physical Optimizer. You can run it in either Synplify Pro mode or Amplify mode. This section briefly describes the differences between the two modular flows. Consult the Amplify User Guide for details about the Amplify flow.

• If you have saved an SFP file with modular regions, the Amplify modular flow does not require you to check the Modular Flow checkbox when you set the device options. If you select the checkbox in a design that has no modular regions, you get a warning message.

• The Amplify modular flow does not require you to set the xc_modular_region attribute, because module placement is determined by the positions where the modules are drawn. If you do set the attribute, you get warning messages that the mapper is ignoring this attribute.

If you run the modular flow in Synplify Pro mode (with the xc_modular_region attribute) and subsequently use the Amplify mode to specify modular regions, the software ignores the xc_modular_region attributes you specified previously and uses the module regions from the .srp file instead.

• In the current version of the Amplify Physical Optimizer, you cannot set module constraints interactively from SCOPE.



A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Index

Symbols

*.acf file 4-13*.lp file 4-13*.ncf file 4-13.ini file

setting preferences 3-51setting preferences from the UI 3-50

.prf file 4-14

.sdc file 3-30

.v files. See Verilog

.vhd files. See VHDL

AActel netlist 3-109Altera

EABs 4-57ESBs 4-57forward-annotation 4-13I/O packing 4-58LPMs 4-55netlist 3-109RAMs 4-46ROMs 4-56

Altera design tips 4-54Apex 4-54FLEX 4-55

altera_implement_in_eab attribute 4-57altera_implement_in_esb attribute 4-57

APEXnetlist 3-109packing I/Os 4-58

area, optimizing 3-107async load warning message 3-76Atmel netlist 3-109attributes

adding 3-95from RTL and Technology views 3-99in constraint files 4-12in SCOPE 3-97Verilog 3-96VHDL 3-95

altera_implement_in_eab 4-57altera_implement_in_esb 4-57for FSMs 3-87, 4-26pipelining 4-31syn_edif_bit_format 4-60syn_edif_scalar_format 4-60syn_encoding 3-88syn_forward_io_constraints 4-12syn_pipeline 4-31syn_probe 4-38syn_romstyle 4-56syn_useioff in Altera 4-58syn_useioff in Xilinx 4-62VHDL package 3-95xc_clockbuftype 4-60xc_fast 4-59xc_map 4-64xc_ncf_auto_relax 4-12xc_padtype 4-66xc_rloc 4-64, 4-65xc_uset 4-64, 4-65

audience for the document 1-7

Synplify Pro User Guide, February 2001 Index -1

Go BackRelatedDocuments

Index A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

BB.E.S.T 3-42batch mode 4-2Behavior Extraction Synthesis

Technology. See B.E.S.Tblack box

pin attributes 4-21black boxes 4-15

adding constraints 4-19EDIF naming consistency 4-21for IP cores 4-60internal startup blocks 4-22using Stamp models 4-22Verilog 4-15VHDL 4-17

bookmarksin source files 3-7using in log files 3-73

browsers 3-44, 3-45

Cclassic mode 4-52clock constraints, setting 3-32clock DLLs 4-60clock-to-clock constraints, setting 3-32colors, setting 3-52column editing 3-7comments in source files 3-7constraint files 4-9

See also SCOPEcreating in a text editor 4-11creating with SCOPE 3-29opening 3-30vendor-specific 4-12when to use 4-9

constraintsadding for Xilinx (tutorial) 2-27, 2-41adding in Tcl files 4-11black box 4-19defaults 3-33define_clock 4-11define_clock_delay 4-11define_reg_input_delay 4-11forward-annotating 4-12kinds of 3-30module-level 4-77options 3-25RLOCs 4-64setting 3-31setting in tutorial 2-17, 2-30syn_reference_clock 4-11

CoreGen 4-60cores, instantiating in Xilinx

designs 4-60critical paths

analyzing for Altera (tutorial) 2-25analyzing for Xilinx designs

(tutorial) 2-39viewing 3-67

crossprobing 3-54allowing to place-and-route file 3-50and retiming 4-36filtering text objects for 3-59from FSM viewer 3-60from log file 3-73from text files 3-9Hierarchy Browser 3-55importance of encoding style 3-60paths 3-58RTL view 3-56Technology view 3-56Text Editor view 3-56text file example 3-58to FSM Viewer 3-60Verilog file 3-56VHDL file 3-56within RTL and Technology views 3-55

Cypress netlist 3-109

Index-2 Synplify Pro User Guide, February 2001


IndexA B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Ddefine_clock constraint 4-11define_clock_delay constraint 4-11define_false_paths constraint 4-12define_input_delay constraint 4-12define_multicycle_path constraint 4-12define_output_delay constraint 4-12define_reg_input_delay constraint 4-11define_reg_output_delay constraint 4-12design entry 1-5design flows

FPGA 1-4Synplify Pro 3-2tutorial 2-3

design guidelines 3-106design size

amount displayed on a sheet 3-50device options

See alsoimplementation optionssetting for Altera (tutorial) 2-20setting for Xilinx (tutorial) 2-32

directivesadding 3-95

Verilog 3-96VHDL 3-95

black box 4-19for FSMs 3-87syn_state_machine 3-85syn_tco 4-19syn_tpd 4-19syn_tsu 4-19

driverspreserving duplicates with

syn_keep 3-102selecting 3-66

EEABs, inferring 4-57Edit menu commands

for editing source files 3-7

Editing window 3-6encoding styles

and crossprobing 3-60default 3-27FSM Compiler 3-84

errorsdefinition 3-6source files 3-5Verilog 3-5VHDL 3-5

ESBs, inferring 4-57

Ffalse paths, setting constraints 3-32fanouts

setting global limit 3-101using syn_maxfan 3-101

features 1-2files

*.acf 4-13*.lp 4-13*.ncf 4-13.data 4-22.mod 4-22.prf 4-14.sdc 3-30.v 3-3.vhd 3-3adding Stamp files 4-23adding to tutorial project file 2-7fsm.info 3-85input. See source fileslog 3-72output 3-109rom.info 3-47Stamp 4-22statemachine.info 3-93synplify.ini 3-51Tcl 4-4

See also Tcl commandsTcl batch script 4-3

Filter Schematic icon 3-64

Synplify Pro User Guide, February 2001 Index-3



Find commandin RTL and Technology views 3-43in the Editing window (tutorial) 2-10

flatteningusing syn_hier 3-100

FLEX netlist 3-109forward annotation

frequency constraints in Xilinx 4-59vendor-specific constraint files 4-12

FPGA configuration 1-6FPGA design flow 1-4FSM Compiler 3-82

advantages 3-82enabling 3-83

FSM Explorerrunning 4-27when to use 4-26

FSM Viewer 3-89crossprobing 3-60

fsm.info file 3-85FSMs

See also FSM Compiler, FSM Explorerattributes and directives 3-87defining in Verilog 4-24defining in VHDL 4-25definition 4-24optimizing with FSM Compiler 3-82properties 3-92state encodings 3-91transition diagram 3-89viewing 3-89

Gglobal optimization options 3-25

HHDL Analyst

See also RTL view, Technology viewchanging the colors used 3-51critical paths 3-67crossprobing 3-54filtering schematics 3-64Push/Pop mode 3-45, 3-48setting colors 3-51sheet connectors 3-49using 3-61

HDL file icon 3-3hierarchy

flattening 3-62traversing 3-44

Hierarchy Browsercontrolling display 3-50crossprobing from 3-55defined 3-44

II/Os

packing in Apex designs 4-58packing in Xilinx designs 4-62

implementation options 3-22constraint 3-25device 3-22global optimization 3-25part selection 3-22specifying results 3-26

implementationscopying 3-105deleting 3-105renaming 3-105

input constraints, setting 3-32input files. See source filesinstances

preserving with syn_noprune 3-102IP cores 4-60




Kkeyboard shortcuts

Alt-c 3-7Ctrl+F2 3-8Ctrl+Shift+F2 3-8Ctrl-d 3-33Ctrl-f 3-7Ctrl-F5 3-6Ctrl-g 3-7Ctrl-n 3-3Ctrl-o 3-6Ctrl-s 3-3Ctrl-Shift-u 3-7Ctrl-w 3-34F12 3-64F2 3-8, 3-45Shift+F2 3-8Shift+F8 3-5shift-F7 3-5Shift-left arrow 3-49Shift-right arrow 3-49Tab 3-7

keywords, completing in source files 3-7

Llatches

warning message 3-77Lattice netlist 3-109license, setting up with the wizard 1-9log files

checking (tutorial) 2-38checking errors 3-5checking for Altera (tutorial) 2-25checking for Xilinx (tutorial) 2-37checking FSM descriptions 4-28checking information 3-72pipelining description 4-31retiming report 4-38state machine descriptons 3-84viewing 3-72

Log Watch window 3-74multiple implementations 3-105

logic removalpreserving with syn_preserve 3-102warning message 3-80

logic, expanding 3-65LPMs, Altera 4-55Lucent

constraint file 4-13forward annotation 4-12output netlist 3-109

MMax netlist 3-109mixed language files 3-17modular flow 4-71

design entry (leader) 4-72design entry (module) 4-75directory structure after module

synthesis 4-77directory structure after top-level

synthesis 4-74final assembly phase 4-80initial design budgeting 4-71module synthesis 4-75place and route (module) 4-78planning 4-72top level synthesis 4-78

multicycle paths, setting constraints 3-32

multiple implementations 3-104multipliers, pipelining 4-30multisheet schematics 3-49

Nnetlists for different vendors 3-109nets

preserving for probing with syn_probe 3-102

preserving with syn_keep 3-102selecting drivers 3-66




ngdbuild commandfinal assembly 4-80module level 4-78

notes, definition 3-6

Ooptimization

for area 3-107for timing 3-107preserving hierarchy 3-103preserving objects 3-102tips for 3-106

output constraints, setting 3-32output files 3-109

specifying 3-26

PP icon 3-13par command

final assembly 4-80module level 4-79

part selection options 3-22paths, crossprobing 3-58pipelining

adding attribute 4-31definition 4-29prerequisites 4-30whole design 4-31

placement, description of 1-6platforms 1-3preferences

crossprobing to place-and-route file 3-50

displaying Hierarchy Browser 3-50displaying labels 3-50RTL and Technology views 3-50setting colors 3-51setting label font 3-51sheet size (.ini file) 3-52sheet size (UI) 3-50

probesadding in source code 4-38

project filesadding files 3-14adding files to 3-16batch mode 4-2creating 2-6, 3-13definition 2-6deleting files from 3-16opening 3-15replacing files in 3-17

Push/Pop mode 3-45HDL Analyst 3-45

QQuickLogic netlist 3-109

RRAMs, inferring 4-41

advantages 4-42Altera EABs and ESBs 4-57Altera Flex details 4-46Xilinx block RAMs 4-49

register balancing. See retimingregister constraints, setting 3-32register packing

Altera 4-58Xilinx 4-62

resource sharingoptimization technique 3-107

retimingexample 4-37overview 4-34report 4-38

return codes 4-2RLOCs 4-64rom.info file 3-47ROMs

inferencing in Altera designs 4-56pipelining 4-30viewing data table 3-47




routing, description of 1-6RTL view 3-39

See alsoHDL Analystadding attributes 3-99crossprobing 3-54, 3-56crossprobing from Text Editor 3-57crossprobing to 3-9defined 3-40difference from Technology view 3-40filtering 3-64finding objects 3-43flattening hierarchy 3-62icon 3-41opening 3-41sequential shift components 4-68setting preferences 3-50state machine implementation 3-85traversing hierarchy 3-44viewing (tutorial) 2-11

Sschematic page size 3-50SCOPE

adding attributes 3-97adding probe insertion attribute 4-40creating constraints 3-29pipelining attribute 4-32specifying RLOCs 4-64state machine attributes 3-87using in tutorial 2-17, 2-30using the wizard 3-30, 3-34

scope of the document 1-7selection, in RTL and Technology

views 3-42sensitivity list

warning message 3-79sentinel driver 1-10sequential shift components 4-67

mapping 4-68Verilog 4-70VHDL 4-69

set_option command 3-24

sheet connectors 3-49sheet size

setting number of objects 3-50setting number of objects (.ini file) 3-52

shift register lookup table. See sequential shift components

shortcutschecking source files 3-11editing text 3-11project-level operations 3-21

Show Critical Path icon 3-67slack

handling 3-68setting margins 3-68

source codeadding pipelining attribute 4-31crossprobing from Tcl window 3-60defining FSMs 4-24fixing errors 3-8opening automatically to

crossprobe 3-57optimizing 3-106specifying RLOCs 4-64supported standards 1-3when to use for constraints 4-9

source filesSee also Verilog, VHDL.adding files 3-14checking 3-5checking in the tutorial 2-9column editing 3-7creating 3-3crossprobing 3-9, 3-10, 3-57editing operations 3-7mixed language 3-17navigating with bookmarks 3-8resolving errors in the tutorial 2-10specifying default encoding style 3-27specifying top level 3-14specifying top-level file 3-27state machine attributes 3-87using bookmarks 3-7

SRL16 primitives 4-68




SRLs See sequential shift componentsSTAMP 4-22

model files 4-22restrictions 4-23

state machinesSee also FSM Compiler, FSM Explorer,

FSM viewer, FSMs.attributes 3-87descriptions in log file 3-84implementation 3-85

statemachine.info file 3-93syn_allow_retiming attribute

using for retiming 4-36syn_edif_bit_format attribute 4-60syn_edif_scalar_format attribute 4-60syn_encoding attribute 3-88syn_forward_io_constraints

attribute 4-12syn_hier

controlling flattening 3-100preserving hierarchy 3-103

syn_keeppreserving nets 3-102preserving shared registerss 3-102

syn_maxfansetting fanout limits 3-101

syn_noprunepreserving instances 3-102

syn_pipeline attribute 4-31syn_preserve

logic removal warnings 3-80preserving FSMs from

optimization 3-87preserving logic 3-102

syn_probeinserting probes 4-38preserving nets 3-102

syn_reference_clock constraint 4-11syn_romstyle attribute 4-56syn_srlstyle attribute

mapping sequential shift components to registers 4-67

syn_state_machine directive 3-85syn_tco directive 4-19syn_tpd directive 4-19syn_tsu directive 4-19syn_useioff attribute


Synplify Prodesign flow 3-2features 1-2overview 1-2starting 1-8starting tutorial 2-4

synplify.ini file 3-51syntax

checking source files 3-5checking Verilog 3-5checking VHDL 3-5

synthesischecking source files 3-5checking Verilog 3-5checking VHDL 3-5rerunning for Altera (tutorial) 2-27rerunning for Xilinx (tutorial) 2-40running for Altera (tutorial) 2-22running for Xilinx (tutorial) 2-35

TTcl commands

batch script 4-3batch scripts return codes 4-2entering in SCOPE 3-32running 4-4




Tcl files 4-4adding constraints 4-11creating 4-5for bottom-up synthesis 4-7guidelines 4-9naming conventions 4-10recording from commands 4-5using variables 4-6wildcards 4-10

Tcl Script windowcrossprobing 3-60, 4-4

Tcl scriptsSee Tcl files.

technology mapping, description 1-6Technology view 3-39, 3-85

See also HDL Analystadding attributes 3-99critical paths 3-67crossprobing 3-54, 3-56crossprobing from source file 3-57crossprobing to 3-10defined 3-40difference from RTL view 3-40filtering 3-64finding objects 3-43flattening hierarchy 3-62opening 3-41setting preferences 3-50traversing hierarchy 3-44viewing Altera design (tutorial) 2-22viewing Xilinx design (tutorial) 2-35

Text Editor viewcrossprobing 3-56

text files, crossprobing 3-9timing constraints 4-11timing failures, handling 3-68timing models

Stamp 4-22timing optimization 3-107tracing paths 3-65tutorial 2-2

Altera flow 2-17

analyzing critical pathsAltera 2-25Xilinx 2-39

analyzing resultsAltera 2-22Xilinx 2-35

checking timingAltera 2-24Xilinx 2-37

design flow 2-3device options


prerequisites 2-2rerunning synthesis


running synthesisAltera 2-22Xilinx 2-35

starting 2-4Xilinx flow 2-29

UUNIX commands, synplify_pro 1-8unused input, warning message 3-80

Vvendor-specific netlists 3-109Verilog

adding attributes and directives 3-96adding probes 4-38black boxes 4-15checking 3-5clock DLLs 4-61creating source files 3-3crossprobing 3-56defining FSMs 4-24editing operations 3-7mixed language files 3-17RAM structures for inference 4-42RLOCs 4-64sequential shift components 4-70supported standards 1-3




VHDLadding attributes and directives 3-95adding probes 4-38black boxes 4-17checking 3-5clock DLLs 4-61creating source files 3-3crossprobing 3-56defining FSMs 4-25editing operations 3-7mixed language files 3-17RAM structures for inference 4-42RLOCs 4-64sequential shift components 4-69supported standards 1-3

Virtexblock RAM 4-50clock DLLs 4-60I/O buffers 4-66netlist 3-109PCI core 4-60

Wwarning messages

async load 3-76handling 3-76latch generation 3-77logic removal 3-80sensitivity list 3-79unused input 3-80

warning messages, definition 3-6

Xxc_clockbuftype attribute 4-60xc_fast attribute 4-59xc_map attribute 4-64xc_modular_region attribute

determining area range 4-85xc_ncf_auto_relax attribute 4-12xc_padtype attribute 4-66xc_rloc attribute 4-64, 4-65xc_uset attribute 4-64, 4-65Xilinx

analyzing critical paths (tutorial) 2-39block RAMs 4-49clock DLLs 4-60CoreGen 4-60design guidelines 4-59design tips 4-59device options (tutorial) 2-32forward-annotation 4-13I/O buffers 4-66IP cores 4-60netlist 3-109packing registers 4-62

