Survey of Discrete Cosine Transform Implementations

andExample Hardware 1-D DCT/IDCT

Implementation

Vijay Sundar Srinivasan

Electrical and Computer Engineering

ECE734 Fall 2000 Project

Project Goals

• Survey : (deliverable - report)– Brief description of where DCT fits into image processing and how 1-

D DCT often forms core of fast 2-D DCT implementations

– Quantitative comparisons between 4 types of HW/SW 1-D DCT implementations based on 4 criteria

• Implementation : (deliverable - design schematic)– 8-point 1-D Discrete Cosine Transform

– Direct computation of formula, design entry in Vhdl + schematic

Approach for Survey• Main information resource : internet

• Comparison categories :– Performance : Speed/Power/Area/Precision

– Implementation : GPMicroprocessor(S/W),DSP based, FPGA-HDL based/ ASIC based

• Comparison considerations

power speed

area

precision

-Voltage-Complexity-Switching

-algorithm-architecture

(pipelining/DA..) -Component Reduction

-feature size

-data formatI/P – O/P resolution,

internal resolution

Implementation Schematic entry->synthesis, simulation : Altera

MaxPlusII Baseline 10.0

Vhdl entry->synthesis : Synopsys Fpga Express

– Direct Implementation : Multiply-Accumulate

– Altera library components used (multiplier/rom/adder)

– Control block in Vhdl

1-Dimensional DCT/IDCT

X(7:0)

Enable

Start

Clk

Rst

Idct

Y(7:0)

Ready

Progress / Schedule / Improvements

• Survey : data is being collected on all types of DCT implementations and categorized

• Implementation : Appropriate Altera devices are being studied for best speed; currently datapath is being put together using Altera components

– Further tentative improvements : Precision, Pipelining

• Forecast : Completion in the first half of January 2001