support across the board a practical guide to ddr2 design with spartan-3a dsp featuring ise 9.2 and...

Support Across The Board™

A Practical Guide to DDR2 Design with Spartan-3A DSP

Featuring ISE 9.2 and the Xilinx Spartan-3A DSP 1800A Starter Platform

Avnet SpeedWay Design Workshop™ 2

Course Objectives

By the end of the day, you will

• Build a functioning DDR2 controller in hardware

• Know what’s required to design your own board


Morning Agenda

• Memory, FPGAs, and Memory Controllers– Memory trends– DDR2 signaling– Xilinx FPGA memory controllers – Memory Interface Generator (MIG)

• Lab 1 – Generate a DDR2 controller core

• Real-world Design with a MIG DDR2 Controller– Interface to the MIG controller– Logically simulate– Hardware debug

• Lunch Break


Afternoon Agenda

• Lab 2 – Build and verify a DDR2 controller in hardware

• PCB Considerations – FPGA pinout– Factors impacting signal quality and crosstalk– PCB simulation example for DDR2– Trace requirements– Power

• Customizing and Verifying the MIG Results – Pinout rules– Pin-swapping– Verifying a new design

• Lab 3 – Analyze and Fix Customized MIG Controllers



Memory, FPGAs, and Memory Controllers


Memory, FPGAs, and Memory Controllers




• Lunch Break


The FPGA/Memory Interface

• Memory interface success in an FPGA is dependent on many things– FPGA fabric– Controller– Memory– Clock– PCB Layout– Power

• We’ll cover all these topics today

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FPGAT

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Clock


DDR2 Interface Covered Today

• FPGA– Spartan-3A DSP

XC3SD1800A

• Memory– Micron DDR2

MT47H32M16

• Controller– Xilinx Memory

Interface Generator (MIG)

• PCB/Power/ Terminations– Avnet-designed

Spartan-3A DSP 1800A Starter Platform


Why DDR2?

• Compared to DDR-1– Less expensive– More readily available– Lower power– Larger varieties– On-die termination (ODT)

• We’ll show details on this later

– Differential strobes

• Compared to DDR-3– More mature– Easier to get– Better controller support


DRAM Market and Technology Trend

• DDR2 is the prevalent architecture 2007-2009

• DDR is still widely used (low end applications)

• DDR3 is the upcoming technology

Data Source: iSupply

DRAM Shipments by Memory Technology Type

0

1000

2000

3000

4000

5000

6000

7000

8000

2002 2003 2004 2005 2006 2007 2008 2009

Forecast Year

Un

its

(M

illi

on

s)

DDR3

DDR2

DDR

SDRAM

RDRAM

EDO

FP / EDO

Note: The DDR3 forecast seems very optimistic

Slide Courtesy Xilinx


DDR SDRAM Component Comparison

Voltage Speed* DensityOn-Die

Termination (ODT)

CAS Latency

DDR 2.5V / 1.25V167 - 400

Mbps128 Mb –

1 GbNone 2, 2.5, 3

DDR2 1.8V / 0.9V250 - 1066

Mbps256 Mb –

2 GbData (Nominal) 3, 4, 5

DDR3 1.5V / 0.75V600 Mbps

– 1.6 Gbps

512 Mb – 4 Gb

Data (Nominal

& Dynamic), Address,

Control on DIMMs

5, 6, 7, 8, 9, 10

*Raw speed of memory device, NOT necessarily the speed the FPGA controller can run


Memory Organization

• Organized as– Banks– Rows– Columns

• Each needs addressing

Ro

w

Column

Bank 0

Bank 1

Bank 2

Bank 3

DDR2


Bank Management

• Latency to open a row• Latency to close a row

4 or 8 banks per memory device

Any 1 row per bank can be open

Other devices can have different

rows open

Slide courtesy Xilinx


Bank Interleave

• Left side has bank/row conflicts – same row in bank -> conflict!• Right side shows banks changing, but no conflict• Higher throughput with bank interleave

Conflicts (gaps for activate, precharge) No Conflicts (no gaps)



Row/Column Addressing

• Interface on S3ADSPSK is 32Mx32 (128 MB or 1 Gbit)– Two chips (each 32Mx16)– Each chip consists of 4 banks– Each bank has 8K rows and 1K columns– Each memory location stores 16 bits– 2 chips * 4 banks * 8K rows * 1K columns * 16 bits = 1Gbit

• Linear addressing requires 25 address bits• Our interface has 15 total address bits

– 13 ADDRESS (A) and 2 BANK ADDRESS (BA)

• BA[1:0] selects one of four banks• A[12:0] with RAS selects one of 8K rows in the bank• A[9:0] with CAS selects one of 1K columns in the row


Control Signals

• Combination of RAS, CAS, and WE determine action– RAS asserted = Open Row

• Bank Address and Row Address latched in

– CAS and WE asserted = Write• Column address latched in• Write enabled

– CAS asserted = Read• Column address latched in

– RAS and WE asserted = Close Row (PRECHARGE)

• Row deactivated

• ‘1’ means asserted (which is active low)

RAS CAS WE

Open Row

1 0 0

Write 0 1 1

Read 0 1 0

Close Row

1 0 1


Read Example

• RAS asserted opens row• Latches bank and row addresses

– Bank 3– Row 0x000C

• CAS asserted by itself identifies the operation as read• Latches the column address

– Column 0x0000

• With row open, multiple reads can be performed by re-asserted CAS– Column 0x0008

.....


Multiple Reads

• Five subsequent reads from the same row shown• Burst length for this example is 8

– Each time CAS asserts, 8 words are read– 40 total words are read in this diagram

• Close row (Pre-charge) shown after reading– RAS and WE simultaneously asserted


Write Example

• RAS asserted opens row• Latches bank and row addresses

– Bank 3– Row 0x000C

• CAS and WE asserted together identifies the operation as write• Latches the column address

– Column 0x0000

• With row open, multiple writes can be performed by re-asserted CAS and WE

– Column 0x0008

.....


Multiple Writes

• Five subsequent writes from the same row shown• Burst length for this example is 8

– Each time CAS/WE assert, 8 words are written– 40 total words are written in this diagram

• Close row (Pre-charge) shown after reading– RAS and WE simultaneously asserted


Data Interface

• One strobe (DQS) per 8 bits of data (DQ)– DQS is a local clock for each data byte

– Can be differential

• One mask (DM) per 8 bits of data (DQ)– Selects which bytes are active during a write (byte enable)

• 32-bit interface has 32 DQ, 4 DQS, and 4 DM bits• FPGA outputs DQS center aligned to the data for a write• FPGA receives DQS edge aligned from the memory on a read

DQS

DQ

DATA WRITE

FPGA DDR2

DQS

DQ

DATA WRITE

DDR2 FPGA


Clock

• Differential – CK and CK#• Address and control signals are registered at every

positive edge of CK• DQ and DQS outputs from DDR2 aligned with clock

– DDR2 uses an internal Delay Locked Loop (DLL)– DLL has both a minimum and maximum frequency– DDR2 specifications based on operating within this

frequency range (125 MHz to 533 MHz)


On-Die Termination

• ODT = On-Die Termination

• Enables built in stub termination on DDR2’s data interface

• Eliminates need for stub termination resistors on the DDR2 side for data

• Adjustable: 50Ω, 75Ω, or 150Ω


FPGA Interface

CLK

CLK_EN

CS

ADDRESS

BANK ADDRESS

RAS

CAS

WE

DQ

DQS

DM

ODT

RST_DQS_DIV

FPGA DDR2SDRAM


Why Do I Need a Controller?

• Easier to interface to a controller than directly to the memory

• Manages multiple operations– Initialization

• See the DDR2 datasheet excerpt

– Calibration• Shift outgoing DQS by 90 degrees• Shift incoming DQS by 90 degrees

– Refresh DRAMs

• Simplified interface– 4 potential commands instead of 15– Initialize command to MIG controller spawns 13 commands

to DDR2

Reduces the design effort


Memory Interface Generator (MIG)

• Free utility to create a custom FPGA/memory interface• Based on real, working, tested hardware

– Documented in Xilinx Application Notes (XAPP)

• Customized outputs include– RTL source for the memory controller in Verilog or VHDL– Simulation testbench and support– User Constraint File (UCF)

• Pinout specific for chosen FPGA device/package• Logic block locations• FPGA timing constraints

– Batch files for processing1. Run ISE tools in command line mode2. Convert to ISE Project Navigator Project

– Timing analysis– Documentation


MIG v2.0 Component Controllers

Fastest clock rate in fastest FPGA speed gradeSee http://www.xilinx.com/support/answers/29446.htm

DDR DDR2 RLDRAM-IIQDR-II SRAM

DDR-II SRAM

Virtex-5 200 MHz 333 MHz 300 MHz

Virtex-4 175 MHz 300 MHz 250 MHz 250 MHz 250 MHz

Spartan-3A/ 3AN/3ADSP

166 MHz 166 MHz

Spartan-3E 166 MHz

Spartan-3 166 MHz 166 MHz


MIG v2.0 DIMM Controllers

DDR DDR2

Virtex-5 200 MHz 333 MHz

Virtex-4 175 MHz 267 MHz

Spartan-3A/ 3AN/3ADSP

166 MHz 166 MHz

Spartan-3E

Spartan-3 166 MHz 166 MHz

Fastest clock rate in fastest FPGA speed gradeSee http://www.xilinx.com/support/answers/29446.htm


Spartan-3/3A DDR2 Controller

• Performance– Up to 166 MHz / 333 Mbps in -5 Speed grade device

• 200 MHz specific implementation documented in XAPP458– 133 MHz/266 Mbps in -4 Speed grade device– Spartan-3A only supports left and right sides

• Data Width– Based on total available pins– Component

• Up to 72-bit in Spartan-3• Up to 64-bit in Spartan-3A/3AN/3ADSP

– DIMM• 64- and 72-bit in Spartan-3• 64-bit in Spartan-3A/3AN/3ADSP

• DQ to DQS Ratio is 8:1• No built-in bank management for Spartan controllers

– Virtex-5 has 4-bank Least Recently Used option


Embedded Processor Controllers

• Interface DDR2 to a MicroBlaze processor

• Embedded Development Kit (EDK) 9.2– Includes the Multi-Port Memory Controller v3 (MPMC3)– MIG used for the physical layer– All MIG rules and constraints apply

• See Answer Record 29221– http://www.xilinx.com/support/answers/29221.htm – Still set XIL_ROUTE_ENABLE_DATA_CAPTURE – Use script to include MIG UCF in MicroBlaze system UCF– Verify design built correctly (see Lab 3)


Where do I get MIG?

• MIG is included with ISE Foundation/WebPACK – Part of CORE Generator

• Graphical User Interface (GUI) provides access to– Core library– Datasheets– 3rd party contact information– Available Xilinx Solution Records

• Must Install ISE IP update– MIG v2.0 in ISE 9.2 IP Update 2– Get IP Updates at www.xilinx.com/download

• Find more information at www.xilinx.com/memory• WebPACK

– WebPACK is free!– WebPACK supports XC3SD1800A on S3ADSPSK– www.xilinx.com/webpack


MIG Documentation

• MIG User’s Guide (UG086)• Xilinx Application Notes

– XAPP768c (Spartan DDR)– XAPP454 (Spartan DDR2)– XAPP458 (Spartan-3A Starter 200 MHz DDR2)– XAPP858 (Virtex-5 DDR2)– XAPP701 & XAPP702 (Virtex-4 DDR2 Direct Clocking)– XAPP721 & XAPP723 (Virtex-4 DDR2 SERDES)

• Virtex-5 ML561 Memory Interfaces User’s Guide (UG199)


MIG Design Flow With Project Navigator...

Project Navigator

Core Generator

MIG

MIG Outputs

Integrate Design

Download Design to Hardware

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Lab 1 – Generate a DDR2 Controller with MIG


Lab 1 Overview

• Run COREGen• Run MIG• Configure controller• Generate• Convert to Project

Navigator• Review raw outputs

– HDL– UCF– Build scripts

Project Navigator

Core Generator

MIG

MIG Outputs

Integrate Design

Download Design

to Hardware


Lab 1 Review

• What are the benefits of using MIG?

• What is required to use Project Navigator with a MIG design?

• Other observations?– Pinouts match our board?– What else did you notice about the UCF?– Properties match between ProjNav and command-line

script?



Real-world Design with a MIG DDR2 Controller


Real-world Design with a MIG DDR2 Controller




• Lunch Break


MIG Output Block Diagram

Memory

MIG Outputs

Memory Controller

Use

r Log

ic

FPGA

ClockClock Management

Calibration

.


User Logic Operating Modes

• Initialize– User instructs controller to set up the DDR2 for operation– Controller programs DDR2 with operating parameters

• Parameters established by user during MIG generation

• Write– User instructs controller to write data to memory– Controller writes the data to the DDR2

• Read– User instructs controller to read data from memory– Controller reads the data from the DDR2

• Refresh– Controller tells user a refresh is needed– User pauses while controller handles refresh


Clock Domains in the User Logic

• 90-degree phase of DDR2 clock– Used for all data-related signals– Generated by a DCM– Referred to as CLK90

• 180-degree phase of DDR2 clock– Used for all control-related signals– Generated by negative edge of 0-phase clock– Referred to as CLK180 or Falling Edge CLK0

• Why is this important?– User logic controls interaction between domains– User must manage multiple clocks and resets


User Interface Signals

Initialization Complete

Auto Refresh Request

Write Data

Write Mask

Address

Burst Done

Command

Read Data

Data Valid

Command Acknowledge

Auto Refresh Done

User Logic Controller

Clocks & Resets Clocks & Resets


Initialize

Initialization Complete

Command




How to Initialize

• Wait for RST_90 and RST_180 to deassert• Set USER_CMD to b’010 on CLK180 for one clock• Wait for INIT_DONE to assert• Minimum of 200 s


Write

Write Data

Write Mask

Address

Burst Done

Command

Command AcknowledgeUser Logic Controller



How to Write

• Set USER_CMD to b’100 and Address on CLK180• Wait for USER_CMD_ACK• Set the DATA and MASK on CLK90

– A dataword is double the memory interface

– Provide BURST_LENGTH/2 datawords (BL=8 4 words)

• Set the next address and data• Assert BURST_DONE on CLK180 after the last address• Deassert USER_CMD after BURST_DONE


Read

Address

Burst Done

Command

Read Data

Data Valid

Command AcknowledgeUser Logic Controller



How to Read

• Set USER_CMD to b’110 and Address on CLK180• Wait for USER_CMD_ACK• Set the next address• Assert BURST_DONE on CLK180 after the last address• Deassert USER_CMD after BURST_DONE• Watch for Data Valid to indicate when data is good (CLK90)


Refresh

Auto Refresh Request

Auto Refresh Done




How to Refresh

• At all times, check for auto refresh request (AR_REQ) in the CLK180 domain

• If AR_REQ, then do not start a new transaction• Wait for AR_DONE (CLK180)• Go back to what you were doing


User Logic Address

• Starting address for burst– DDR2 auto-increments address for burst

• Combines addresses for bank, row, and column– [ (row) : (column) : (bank address) ]

• 32M x 32 example– Address bus is 26 bits– User_A[25:13] is the Row Address– User_A[12:2] is the Column Address– User_A[1:0] is the Bank Address

• Why is Column Address 11 bits?– 1K columns per row only requires 10 bits


Column Address A10

• Column address bit A10 is special• PRECHARGE is the DDR2 “Close Row” command

– Deactivates current row– Returns bank to the idle state

• Auto-PRECHARGE– DDR2 automatically closes the row after the current operation– MIG does not support auto-precharge, but still reserves A10

• To set Auto-PRECHARGE, assert column address A10• What if a column needs 11 or more address bits?

– Rare, but if so, A10 gets skipped

• What if a column needs 9 or fewer address bits?– Extra address bits added up to A10

• 32Mx32 has 11 column address bits– A[9:0] for the address– A[10] reserved for user to create custom, auto-precharge logic


User Interface Commands

Command[2:0] Description

000 NOP

010 Initialize Memory

100 Write Request

110 Read Request

Others Reserved


User Logic Interface -- 32Mx32 Example

Function User Guide Name Direction Width

Data (Write) cntrl0_user_input_data To controller 64

Mask cntrl0_user_data_mask To controller 8

Address cntrl0_user_input_address To controller 26

Command cntrl0_user_command_register To controller 3

Burst Done cntrl0_burst_done To controller 1

Command Acknowledge cntrl0_user_cmd_ack To user 1

Data (Read) cntrl0_user_output_data To user 64

Data Valid cntrl0_user_data_valid To user 1

Initialization Complete cntrl0_init_val To user 1

Auto Refresh Request cntrl0_auto_ref_req To user 1

Auto Refresh Done cntrl0_ar_done To user 1


DDR2

SDRAM

Lutdelay

FIFO

Lutdelay

FIFO

Address, Command, & Control

Controller

User Interface

Write Datapath

LUT delay Calibration Monitor

Read CaptureUser_output_data

FPGA Clock

User_input_data

User_address

LUT delay select

User_command

User_burst_done

User_cmd_ack

User_data_mask

User_data_valid

DCMInput_clock

Clocks all modules in fabric

DQS, DQ

DM

Spartan-3x FPGA

Spartan-3x Memory Interface Architecture


.


System Reference Clock

• MIG assumes this to be differential– SYS_CLK and SYS_CLKb

• MIG assumes it to be the controller frequency• User must connect the real system clock• Single-ended clock is acceptable

– Differential has less jitter

• Can a DCM synthesize the proper frequency?– Yes, if you account for jitter in timing calculations

• User must edit several MIG RTL files– Shown in Lab 2


MIG’s Two Output Designs

• user_design– For the user who wants to

instantiate the MIG controller– Top-level exposes all DDR2

external signals and User Logic interface

– No instantiation template provided

• example_design– Adds a User Logic example– Top-level only exposes DDR2

external signals• Adds wrapper layers to connect

controller, calibration, clock management, and User Logic

– More practical starting point


example_design File Hierarchy

• Memory controller• User Logic• Clock management• Calibration


Logical Simulation

• MIG generates logical simulation files

– VHDL or Verilog testbench

– ModelSIM “do” file

– Micron memory model• Assuming the Micron license agreement is checked

• Verilog only

• Newer versions available directly from Micron


Simulator Support

Verilog VHDL

ISE Simulator Yes – Requires modifications to the

HDL. No modifications

required in 10.1

No – Scheduled to work in ISE 10.1

ModelSIM-XE Verilog

Yes NA

ModelSIM-XE VHDL NA No – Need mixed language simulator

due to Micron’s Verilog model

ModelSIM-SE Yes Yes


VHDL Options

• Use a mixed-language simulator– ModelSIM SE

• tested and supported by Xilinx

• Get 3rd party VHDL models for the memory– http://www.freemodelfoundry.com/– Not tested or supported by Xilinx

• Wait for ISE 10.1 to consider ISE Simulator


Hardware Debug

• External logic analyzer – Consider adding Agilent Soft Touch connectorless probes– Invaluable for performing full-speed measurements

• External scope– Probe directly at the memory or FPGA– Leave break-out vias exposed for BGAs on prototypes– Critical for measuring signal integrity

• Embedded logic analyzer– Extremely versatile and inexpensive option– ChipScope Pro


Debug Logic Anywhere Within the FPGA

• Identify logic that you need to debug and verify• ChipScope Pro cores are placed directly within the logic and …

– Function as “virtual test headers”

– Provide access any signal or node with the FPGA

– Debug at the system clock rate

ClockClock

Trigger 0Trigger 0

Trigger 1Trigger 1

Trigger 2Trigger 2

Trigger 3Trigger 3

Trigger OutTrigger Out

Memory

Controller

Memory

Controller

AddressAddress

DataData

ClockClock

ILAILAXilinx



ChipScope in Spartan

• ChipScope cores take up FPGA resources– Consider using a larger FPGA in prototypes

• ChipScope logic must meet timing– Limited to around 200 MHz for Spartan

• ChipScope must run faster than DDR2 to see double data rate– DDR2 lower limit is 125 MHz– Not practical to run ChipScope at 250 MHz– Consider violating 125 MHz limit

• Run DDR2 at 50 MHz• Run ChipScope at 100 MHz or 200 MHz• See this in Lab 2

• High-speed measurements need to be taken with a high-speed logic analyzer


LUNCH



Lab 2 – Build and verify a DDR2 controller in hardware


Lab 2 Overview

• Modify the example design– UCF to match the

hardware– Connect correct

system clock– Integrate new user

logic

• Add ChipScope logic analyzer

• Build, download, and verify hardware

Project Navigator

Core Generator

MIG

MIG Outputs

Integrate Design

Download Design

to Hardware


User Test Logic

• Initialize the memory

• Write to fill the memory with incrementing pattern

• Read back the memory

• Handle auto-refresh when necessary


User Test Logic State Machine

Power On

Initialize Memory

Write

ReadCompare


Xilinx Spartan-3A DSP 1800A Starter Platform

Micron 32Mx32 DDR

EXP

Spartan-3A DSPFPGA

National 10/100/1000 PHY

Texas Instruments Regulators

..

RS232

Intel Flash


• Expansion slot for custom development• Consists of two high-speed Samtec mezzanine connectors

– Two connectors = full expansion module– One connector = half expansion module

• Each connector has– 84 I/Os (mix of single-ended and differential)– Access to one or more FPGA clock input pins– 2.5V and 3.3V source power

• Use one from Avnet– EXP Prototype– EXP High-speed Analog– EXP Video– EXP Interface

• Develop your own– Specification available from Avnet

www.em.avnet.com/exp


Lab 2 Review

• Why did we do simulation in Verilog?

• What’s the penalty for using a DCM to synthesize the system clock?

• Other observations?– Did your design pass timing?– How was the new UCF different from the original?– How does adding ChipScope affect a design?



PCB Considerations


FPGA Pinout

• A random pinout will not work– Pinout relationship of DQS to DQ is critical– LUT delay line placement is critical

• MIG follows all the pinout guidelines

• To modify the MIG-generated pinout, you must understand the pinout rules

• The pinout rules are covered later


Simultaneous Switching Outputs (SSO)

• Limits the number of outputs on a bank• If violated, ground bounce can occur• MIG doesn’t check this for you• Read XAPP689• For DDR2, we use SSTL 1.8V Class I & II IOSTANDARDs• For XC3SD1800A-FG676 Bank 3 (Left)

– Datasheet Table 26 shows 9 equivalent Vcco/GND pairs

– SSTL18_I allows 15 SSO per Vcco/GND pair (135 total)

– SSTL18_II allows 3 SSO per Vcco/GND pair (27 total)

• Spartan-3A DSP 1800A Starter Platform– Using Class II for all 32 data bits is a problem

– Use Class I instead


Calibration Loopback

• MIG calls this rst_dqs_div– One output: rst_dqs_div_out– One input: rst_dqs_div_in

• Not a DDR2 signal!• Used for Spartan-3x controllers to calibrate timing

– Write enable for readback from DDR2

• Must be placed on two I/Os in the center of the DQ bus• Trace length equal to sum of average DQS and clock trace

lengths– Basically one roundtrip from FPGA to memory and back

• NOT the same as clock feedback required by pre-EDK 9.2 DDR2 controller– If using EDK 9.1 or earlier, design a separate clock feedback

• Both MIG loopback and EDK 9.1 clock feedback are on Spartan-3A DSP 1800A Starter Platform


Factors Impacting Signal Quality

• The 3 T’s– Technology

• Use slowest possible driver switching speeds

– Topology• Select optimal topology for signal integrity, timing, and EMC

• Shorten traces or stubs to their critical length or shorter

– Termination• Select optimal termination for signal integrity, timing and EMC

• Match end of line to Z0 using passive components


Technology’s Influence on SI

• Smaller dies mean faster edge rates• Faster edge rates mean reflections, and signal quality problems

– Even when the package hasn’t changed and your clock speed hasn’t changed

– A problem for legacy designs and redesigns

• Setup: length = 7 inchesTrace Topology

• Overshoot using SSTL18 Class II driver (red) = 675 mV peak-peak

• Overshoot using LVCMOS18 Fast driver (green) = 47 mV peak-peak


Topology’s Influence on SI

• Topology is critical– Analyze prior to layout

• Longer traces more susceptible to reflections

• Overshoot for 2.5 inch trace

(red) = 670 mV peak-peak

• Overshoot for 0.25 inch trace (green) = 114 mV peak-peak

Trace Topology


Termination’s Influence on SI

• Impedance discontinuities cause reflections– Changes in trace width– BGA breakouts– Stubs– Vias– Loads– Connector transitions

• Basic Termination Guidelines– Source termination is useful in point-to-point– Far-end termination is useful in multi-point connections– Distributed termination is useful with variable configurations

– Improper terminations– No termination– Large power plane

discontinuities– Changes in trace height above

power planes– Changing layers


Termination Example

• Setup: length = 7 inches

Trace Topology without Termination

• Overshoot for unterminated net (red) = 674 mV peak-peak

• Overshoot for series terminated net (green) = 90 mV peak-peak

Trace Topology with Termination


ClockA

ClockB

Net Topologies

CoupledRegion

Factors Impacting Crosstalk

• Crosstalk occurs when 2 or more neighboring traces couple together• The following affect crosstalk performance on a PCB

– Stackup, Signal Integrity, Fast Edge Rates, and Trace Separation

Net ClockA inducing crosstalk on ClockB

ClockA(Aggressor)

ClockB(Victim)

Sending a signal down one trace

causes a signal to appear on the 2nd

trace


Stackup’s Impact on Crosstalk

• Microstrips (surface layer) traces are more susceptible to crosstalk

• Striplines (internal layer) traces are less susceptible to crosstalk– Multiple reference planes– Reduces trace to trace coupling

• Consider extra layers for reference planes– A divided voltage plane is a poor reference


Microstrip vs. Stripline

• Crosstalk on TL2 for microstrip (green) = 257.4 mV peak-peak

• Crosstalk on TL2 for stripline (blue) = 79 mV peak-peak

• Setup: length = 7 inches, spacing = 8 mils, TL1 and TL3 Aggressor, TL2 = Victim


Signal Integrity’s Impact on Crosstalk

• Reflections lead to higher signal swings • Termination improves SI and crosstalk.

Unterminated nets

Terminated nets

• Crosstalk on TL2 when nets were unterminated (red) = 637 mV peak-peak

• Crosstalk on TL2 when nets were terminated (green) = 257.4 mV peak-peak


Edge Rates’ Impact on Crosstalk

• Fast edge rates lead to increased coupling between traces– Crosstalk is higher– Slowest driver that meets timing requirements is

recommended

• Drive strength– Large drive strength values and singled ended swing also

increase the coupling between traces– Lower drive strength to minimum that meets requirements


SSTL18_I vs SSTL18_II

• Setup: length = 7 inches, spacing = 8 mils, TL1 and TL3 Aggressor, TL2 = Victim

• Crosstalk on TL2 using SSTL18 Class II drivers (red) = 118 mV peak-peak

• Crosstalk on TL2 using SSTL18

Class I drivers (green) = 89 mV peak-peak


DDR2 Termination

• DDR2 uses the SSTL standard– Stub Series Termination Logic– JEDEC

• Rules are simple– Stub termination to 0.9Vtt on all receiving

nodes• Resistor value equal to board impedance

– Series termination on all driving nodes• Sum of termination and output driver

impedance should equal board impedance

• What about bi-directional signals?– Sometimes driving, sometimes receiving– Series and stub terminations required at

both ends

• Differential signals have 100-ohm termination at load

• EXCEPTION: Any or all terminations can be eliminated if proven during board-level simulation


DDR2 On Die Termination (ODT)

• New feature in DDR2• Termination added inside DDR2

– DQ, DQS, DM

– Multiple termination values for different configurations

• None, 50 Ohm, 75 Ohm, 150 Ohm

• Not included for address or control– That comes with DDR3

• Eliminates the need for stub terminations at the DDR2 for the data lines


Spartan-3A DSP Starter Termination


When Can Terminations Be Relaxed?

• When simulating proves that it can!

• See Micron TN4614

• Some examples– Trace length < 2”– Only 1 or 2 memory devices– Relaxed timing allows weaker drivers

• Reduced DDR2 drive strength

• Use SSTL 1.8V Class I FPGA I/O Standard


Board-level Simulation

• A must for any serious, high-speed design

• Investigate the following– Differing layout topologies– Trace lengths– Resistor values– Resistor placement

• Examples– Determined we could eliminate all

terminations on Spartan-3MB board

• Trace lengths < 1”

– Determined some stub terminations on Spartan-3A DSP 1800A Starter Platform were not necessary


Example Simulation Flow

Simulate after each step until acceptable results are achieved

1. Create driver/receiver topology with no termination2. Can the trace be shortened?3. Is a reduced drive strength possible?4. Turn on ODT at the DDR2

• Experiment with all three options (50, 75, and 150ohm)

5. Add series termination at driver• For bi-directional signals, experiment moving series

termination to other side• Add series termination on both sides

6. Add stub termination at receiver(s)


DDR2 Signal Integrity Simulation Demo

Pre-Layout Analysis for Data Topology


DDR2 Crosstalk Simulation Demo

Pre-Layout Analysis for Data Topology


Recommended PCB Design Flow

System Design,

Part Selection,

and Schematic

Entry

System Design,

Part Selection,

and Schematic

Entry

Prototype

PRE-LAYOUT LAYOUT

Full BoardPlace-and-

route

FunctionalTesting

&Debugging

PROTOTYPING

EMITesting

&Debugging

Linesim Boardsim

Mentor HyperLynxwww.hyperlynx.com


For More Information

• Talk to a Mentor Graphics Representative in your area– http://www.mentor.com/products/pcb/pads/resellers/index.cfm

• Get a HyperLynx evaluation– http://www.mentor.com/products/pcb/analysis_verification/hyperlynx/hyperlynx_software_eval.cfm – Good tutorials– Easy to use– No license required for eval


Other SI Resources

• Terry Fox & Associates (Issaquah, WA, USA)– www.siemc.com– Signal integrity training– Project consulting– Disaster recovery

• CircuitCraft (Calgary, Canada)– [email protected] – Schematic and layout design review– Post-layout board simulation (using HyperLynx Boardsim)– Full electrical and physical design

• Or check with your Mentor Graphics Rep for a local resource


Simulation Models

• Board-level simulation tools typically require IBIS models

• Xilinx provides IBIS models for free– Available from the Download Center (www.xilinx.com/download

) – Make sure you are using the correct I/O standard– Or, generate an IBIS model directly from ISE

• Micron provides IBIS models for free– See product web page


Trace Length Matching Requirements

• Members of a differential pair matched to +/-10mil

• DQ, DQS, DM and CK matched to +/- 45mil

• Address/Control matched to +/- 100mil of CK

• RST_DQS_DIV and MB_FB_CLK matched to +/- 45mil of sum of average DQS and average CK


Power

• Three independent supplies required

• DDR2 and FPGA I/O supply is 1.8V

• Source/sink 0.9V termination supply– Resistor divider is possible– Regulator is recommended

• 0.9V reference supply – Resistor divider is possible– Regulator is recommended


Texas Instruments TPS51116

• Used on Spartan-3A DSP 1800A Starter Platform • Provides 1.8V up to 10A• Provides 0.9V Vtt up to 3A• Provides 0.9V Vref

FPGA

DDR2

TPS51116

DDR2

1.8V 0.9Vtt

0.9Vref


National DDR2 Termination

3.0 – 5.5V

DDR2

Termination Regulator

LP2997PSOP-8

1.8V

VTT = 0.9V

Vref = 0.9V

DDR2

Memory

System

Buck Converter

LM283XSot-23

1, 1.5, 2A


Decoupling Capacitors

• For the FPGA, follow Xilinx XAPP623– Example for the Spartan-3A

DSP 1800A Starter Platform (XC3SD1800A-FG676) shown in table

• For the DDR2, see Micron TN4602

FPGA Decoupling 1.8V 1.2V 0.9V

Total # Pwr/Gnd Pairs 9 23 9

Tantalum Capacitor 470uF 1 1 0

4.7uF (0603) 2 4 0

1.0uF (0402) 3 7 5

.01uF (0201) 5 13 5


Stackup

• Power planes on S3ADSPSK are multi-rail– Not good for a return path

• Extra ground planes used



Customizing and Verifying the MIG Results


Customizing the MIG Pinout

• What if the MIG output doesn’t match an existing board?

• What if I’m designing a board and don’t like the pinout MIG gives me?

• What about pin-swapping during layout?

• Why does it matter?– Calibrating strobes with data bits


If You Want to Change the I/Os

• Know the pinout rules

• Use FPGA Editor to find suitable alternatives

• Modify the UCF accordingly

• Verify the implemented result


Spartan-3x Pinout Rules

• The IOBs for DQ bits must be placed five tiles above or six tiles below the IOB tile for the associated DQS bit– See XAPP768c– See AR24935– Unbonded IOBs count (can’t simply use datasheet pinout)

• Loopback must be in the middle of the DQ bus• Keep even/odd DQs oriented in the same top/bottom

tile pattern– One CLB column is dedicated for the odd numbered bits and

one is dedicated for the even numbered bits

• CK/CK_N, address, RAS_N, CAS_N, WE_N, CS_N, and ODT must be placed together in bank that are on the same side of the device


What’s a Tile?

• IOBs are grouped together

• Each grouping is called a tile

• Example shows a 2 IOB tile

• “Five tiles above” means 10 total IOBs above in this case IOB Tile


Common Pin-swapping

• A DQ byte can be swapped with another byte – Strobe and data swapped together

• DQ bits can swap within a byte– Swap even-numbered bits with other even-numbered bits– Swap odd-numbered bits with other odd-numbered bits

• Control, address, data mask, and clock can be swapped at will– Spreading too far apart may cause timing issues though

• Anything besides these requires checking against the pinout rules


Using FPGA Editor

• Tool to view internal device layout• Shows things that are hidden in other

tools– Unbonded I/Os

– Detailed routing

• What will we use it for?– Creating or customizing a pinout that

follows the MIG rules

– Verifying a design was implemented properly

• Where is it?– Start Programs Xilinx ISE

Accessories FPGA Editor

– Within Project Navigator, “View/Edit Placed Routed Design”


Adjusting the UCF

• Use FPGA Editor to find acceptable new pin locations

• Pin location changes must be reflected in the UCF

• These pin location changes will affect SLICE location constraints as well


Verify the Result

• Pass UCF timing constraints– MAXDELAY– FROM/TO– PERIOD

• Examine data routing– Compare routes in FPGA Editor with AR25245– Analyze delays in FPGA Editor

• Examine clock routing– Compare routes in FPGA Editor with AR25245– Inspect Clock Section in PAR report


Verify Data (DQ) Routing

DQ0DQ1

Keep even/odd DQs oriented in same top/bottom I/O tile pattern

Once this pattern is established, it must be repeated for all DQ lines

EVEN DQCLB

COLUMN

ODD DQCLB

COLUMN

Keep even/odd DQ bits in the

same CLB Columns

(as seen in FPGA Editor)

Even on top of I/O Tile Pair.

Odd on bottom


Data Skew and Delay

• Use FPGA Editor– Instructions outlined in AR25245

• Data net skew < 75 ps• Total delay range = 300-700 ps• In this example

– Delays range from 411 to 464 ps– Skew = 53 ps

• Data net skew is less than 75 ps• Total delay range is within 300-

700 ps range


Clock Routing

• Clock routing must follow a specific pattern

• Details are shown in AR25245– Example of proper

routing shown


Clock Report

• Inspect Clock Report section in PAR report file– Net Skew < 65 ps (this example = 64 ps)– Max Delay ~ 400 ps (this example’s range is 465 to 491 ps)

**************************Generating Clock Report**************************...+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/dqs0_delayed_col | | | | | || 1 | Local| | 11 | 0.018 | 0.465 |+---------------------+--------------+------+------+------------+-------------+|main_00/top0/data_pa | | | | | ||th0/dqs1_delayed_col | | | | | || 1 | Local| | 11 | 0.064 | 0.488 |+---------------------+--------------+------+------+------------+-------------+...



Lab 3 – Analyze and Fix Customized MIG Controllers


Lab 3 Overview

• Verify a “known-good” design (Lab 2)– Verify with FPGA Editor and examining PAR

report– Practice looking at something correct

• Fix a “broken” design– Open “broken” design in FED– Figure out what’s wrong– Fix it in your UCF– Re-implement– Re-verify


Lab 3 Review

• What happens when you violate the +5/-6 tile rule?

• How did you determine the correct SLICE location after changing DQ/DQS?

• What are the pins to avoid when selecting new sites in FPGA Editor?

• How were those unsuitable pins highlighted?

• How were the new pin locations verified?



Conclusion


To Proceed with a MIG Design

• Get the Xilinx Spartan-3A DSP 1800A Starter Platform• Get ISE 9.2, IP Update #2, and ChipScope Pro• Evaluate options for logical simulation• Prepare for board-level simulation• Get IBIS and HDL models• Read the documentation

– Xilinx• Previously listed

– Micron• DDR2 datasheet

• TN4602, TN4605, TN4606, TN4614, TN4720


SpeedWay Kit Specials

* Must purchase a “-SK” kit Other specials available – see the kit specials handout

• Spartan-3A DSP Starter Kit $285 (save $109)

– Xilinx Spartan-3A DSP Starter Kit and SpeedWay attendance– AES-SPEEDWAY-S3ADSP-SK

• Spartan-3A Starter Kit $200 (save $124)

– Xilinx Spartan-3A Starter Kit and SpeedWay attendance– AES-SPEEDWAY-S3A-SK

• Virtex-5 LX50T PCIe Starter Kit $995 (save $499)

– Avnet Virtex-5 LX50T PCIe board and SpeedWay attendance– AES-SPEEDWAY-LX50T-SK

• EDK Software Bundle* $200 (save $295)

– 12-month EDK software license– AES-SPEEDWAY-EDK

• ISE Foundation Bundle* $995 (save $1500)

– 12-month ISE software license– AES-SPEEDWAY-ISE


Course Objectives Review

You now have…• Built a functioning DDR2 controller in hardware

– Generate the DDR2 controller IP– Incorporate into ISE Project Navigator– Connect the design to custom logic– Download and operate on the Spartan-3A DSP 1800A

Starter Platform

• Learned what’s required to design your own board– Connect the FPGA to DDR2 components– Power and decoupling– Signal integrity and crosstalk– Create a custom DDR2 pinout for the FPGA



Thank you!

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