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EE-166 Super Buffer and Schmitt Trigger

David W. ParentSJSU

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Super Buffer

• We know that to drive large loads we increase the widths of our transistors.

• How do we drive these larger transistors?– Scale a chain of inverters.

( )g

d

CC

=−1lnαα

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Super Buffer

• How do we know how many to use in the chain and how to we scale up?

• If the Drain Capacitance is close to zero, the scaling factor reduces to e=2.718.

• What do we do when it is not?– Solve numerically for α.

( )g

d

CC

=−1lnαα

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Super Buffer• Rearrange the design equation.

equation. second theintoA Plug A, Calculate

for guess a Make αα

α

α

A

g

d

e

CC

A

=

+=

• Repeat until the equations converge to 2 decimal places.

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Design flow of a Super Buffer

• Use the equivalent inverter technique to design symmetric propagation delays of the the logic gate you need to buffer

• Calculate the capacitive load the circuit needs to drive (This may be given to you.)

• Find α or calculate or if the situation warrants it use α=3.• Calculate the number of stages

– Add an extra inverter to the beginning of the chain if the output needs to be inverted (depending upon an odd or even number of stages.

• Scale each buffer stage by α.• Calculate power and area

– Does this make sense? if ok then enter into schematic capture and follow the rest of the design flow.

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Example

• You have a NAND3 that needs to drive a 1000 identical NAND3s with a minimum propagation delay. – The output of the buffer should not logically invert the

out put of the NAND3.– Assume that WP=1.5µm and WN=1.8µm and that Ln

and Lp are minimum sized and that the propagation delays for the worst case transitions are symmetric for the NAND3.

– Assume that this will give you symmetric rise and fall times.

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Find the equivalent inverter of the NAND3

• In the worst case only 1 PMOS conducts for charging and all nmos have to turn on to discharge and that the input that is controlling the state is closest to ground– In this example WN and WP are given and we

assume that they already have symmetric propagation delays.

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Calculate the load you need to drive

• Find the input capacitance of the NAND2• Multiply by 1000.

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Find the scaling factor αFind the COUT of the NAND3

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Find the scaling factor α

Numerically solve for α

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Find the number of stages

In order to be non invertingwe need an extra inverterat the beginning.

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Calculate WN and WP

Ignore the 0.

Are these widths acceptable?

Remember we scaled WN by 3to take into account Leff=3LN.We divide by 3 to get a regularinverter.

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Calculate the load for each stage

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Calculate the delay for each stage and the total delay.

Is this delay acceptable?

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Check the power

Is this power acceptable?

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Continue with normal design flow. • If the circuit is

acceptable then we proceed.

Use calculated capacitance.1000 NAND3’swould take a long time to simulate.

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Schematic

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Results

• The propagation delays were ~1ns with 4% difference.– This was 14% slower than we predicted.

Should we adjust the A constant by 1.14?• If we do then the error between our hand

calculations and our spice results drops to 2%.

• The rise and fall times were ~600ps with 10% difference.

• The power consumption was ~60mW.

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Layout

• This is tricky because we are going from something that is small to something that is large.– Keep the cell height the same as the smallest

inverter and use multipliers– This will cause the last buffer to have at least 6*6=36

fingers which will lead to a long poly line

CellHeight

Width changes by αn

INPUTOUTPUT

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Layout Continued• Keep the same cell height but

break up the last inverter into manageable chunks chunks

Try dividing it up into three.

INPUT

OUTPUTThis causesthe in and outports to be onthe same side.(Maybe you want this.)

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More options for layout

INPUT

OUTPUT

Hard to fill blank space.

INPUTOUTPUT

Maybe harder to fill.

Ever played Tretris?

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Lets pick a floor plan and go!

INPUT

OUTPUT

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Design the first inverter

Leave extra room to expand NMOS and PMOSwidths.

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Stamp down a copy and wire.

There is some wasted space,but lets fix it later.

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Now we make the next inverter in the buffer

We need an integer number of fingersbut our scaling factor is 6.24.

We come up with a new width that gives us the closest to 6 fingers.

In this case WP is 10.05µm, and WN=4.05µm.

See why we left extra space between the power rails!

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Now the final layoutThe finalbuffer wassplit into 2 instead ofthree becauseit gave an evennumber of fingers.

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Extract/LVS

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Now the final layoutThe finalbuffer wassplit into 2 instead ofthree becauseit gave an evennumber of fingers.

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Let’s tighten up the layout

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Final thoughts

• Are the poly lines too long?– Antenna rules

• Are lines wide enough?• What would the power be if we had 40

output pins switching at the same time?

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Results (extracted)

• The propagation delays were ~1ns with 3% difference.

• The rise time was 509ps and the fall time was ~600ps (14% difference.)

• The power consumption was ~53mW.• The total area was 53 by 72 µm.

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EE167 Super Buffer For Driving Output Pins.

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CMOS Schmitt Trigger

• Cleans up slow rising/falling noisy signals.– Hysteresis

VIDVIU

VID

VIU

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CMOS Schmitt TriggerWNF LNF

VHLTRIP VTN−

VDD VHLTRIP−

2

⋅WNI

LNI⋅:=

WPF LPFVDD VTP+ VLHTRIP−

VLHTRIP

2

⋅WPI

LPI⋅:=

VID

VIU

Slow Rising Noisy Signals(Like on an Input Pin)_

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Alternate Implementation

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CMOS Schmitt Trigger

Design a Schmitt Trigger to have trip voltages of 1 and 3, that candrive a 100fF Load at a propagation delay of .5ns.

I tried to use the equations but they were really off. I had to use aparametric analysis to find WNI and WPI. WNF and WPF were set from equation. Once the timing was right, I adjusted WNF andWPF to get the trip voltages right. This of course altered the timing, but I was closer. The equations were useful as a starting and helped me understand weather to increase or decrease thewidth of a transistor.

The total time to test get a working schematic was 3 hours. It will probably take another three to get it to LVS and post extractionsimulation. (Note: It took 1.5 hours)

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Final Schematic

Propagation Delay was .49nsVTRIPHL=.976V 2% ErrorVTRIPLH=3.13V 4% Error

WNI WPI WNF WPF8.5 22.1 8.78 133.8

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VTRIPLH

Analysis

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VTRIPHL

Analysis

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LAYOUT

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Results from Post Extraction Simulation

Propagation Delay was .45ns 10%

VTRIPHL=.981V 2% Error

VTRIPLH=2.0V 4% Error