summer 2011 cave3 news - auburn...

Summer 2011

cave3 News NSF Center for Advanced Vehicle and Extreme Environment Electronics

cave.auburn.edu; tele: (334) 844-3424

INSIDE

1 Message from Director 2 CAVE3 Review 3-8 Research Highlights 9-10 Announcements 11 Selected Publications

SAMUEL GINN COLLEGE OF ENGINEERING

Mission Statement

CAVE is dedicated to working with industry in developing and implementing new technologies for

the packaging and manufacturing of electronics, with special emphasis on the cost, harsh environment,

and reliability requirements of the automotive, aerospace, military, computing, portable and other in-

dustries.

Message from Director

We are off to a flying start to 2011. I am glad to report that CAVE3 Center publications have received two notable accolades including best-of-conference proceedings paper awards at the ECTC 2010 and SMTAI 2010. The specific citations are: (a) Cai, Z., Zhang, Y., Suhling, J., Lall, P., Johnson, R. W., Bozack, M., Reduction of Lead Free Solder Aging Effects using

Doped SAC Alloys, 60th ECTC, Las Vegas, Nevada, pp. 1493-1511, June 1-4, 2010. (b) Lall, P., Vaidya, R., More, V., Goebel, K., Interrogation Of Damage-State In Lead-Free Electronics Under Sequential Ex-posure To Thermal Aging And Thermal Cycling, SMTAI Technical Conference, Orlando, FL, pp. 405-418, Oct 24-28, 2010. Both awards will be formally conferred at the respective 2011 Conference Events. The papers are in the area of leadfree electronics and prognostics health management of electronic systems. The recognition is a reflection of the quality of re-search being conducted by CAVE³ researchers. The area of leadfree electronics is of strategic impor-tance to both the consumer electronics and military electronics applications and a major focus for the Center. Military applications often have a harsher environment, longer life-expectancy and higher costs associated with catastrophic electronic system failure. It is for this reason that the military electronic com-munity has been focused on identifying the knowl-edge gaps in research needs through the PERM con-sortium. CAVE3 has been an active participant pre-senting research overviews at various meetings. CAVE3 also participated as part of in a Lockheed Martin Technology Review on Leadfree Electronics

on October 22, 2010. A fairly extensive test matrix is been run in the center on a variety of leadfree elec-tronic packaging architectures and under a variety of harsh environmental and usage conditions. CAVE3 researchers are studying fundamental aspects of lead-free electronics including tin-whisker mitigation strategies, high-strain rate behavior of leadfree alloys and aging-effect mitigation strategies. Center re-search and reports are available through the secure area of the CAVE3 website.

The Center membership spans companies and fed-eral agencies with interests in space, ground-based vehicles, missiles, aircraft and sea-based applications. Prognostics health management methods (PHM) be-ing developed by CAVE3 have wide applicability in a broad-range of applications. The Center researchers have developed techniques for assessment of prior accrued damage in field deployed assemblies without need for acquisition of prior stress histories. The CAVE3 PHM Toolbox provides the membership a turn-key method to compute residual life. The leader-ship position of the Center in PHM is reflected in the heavy involvement of the Center researchers in IEEE PHM 2011 Conference to be held in Denver from June 20-23, 2011.

The Center has a long history of strengths in the general area of shock and vibration. The center is in the process of testing new interconnect structures for survivability in high-g aerospace environments. Once such example is the NASA micro-coil interconnect which is currently under test in g-levels typical of space applications. Recently, the center has studied fully-instrumented ball-grid array assemblies with high-speed video at g-loadings of 12,000 G's.

I am pleased to announce the Engent, Inc has joined the Center as a full-member. Pradeep Lall Thomas Walter Professor and Center Director

CAVE3 Consortium Spring Technical Review The Center for Advanced Vehicle and Extreme Environment Elec-tronics (CAVE3) held its Spring Technical Review and Project Planning Meeting on March 9-10, 2011 in Auburn University Hotel & Conference Center. Current members of the Consortium at-tended the review. The detailed agenda for this event and review proceedings are available at cave.auburn.edu under CAVE3 Re-views through the member login area. The following projects were be presented at the meeting: Acceleration Factors and Life Prediction Models for on-chip

and off-chip Failure Mechanisms Advanced Interconnect Systems and 3D-Packaging Architec-

tures in Harsh Environments Prognostic Health Monitoring Methodologies for Damage Esti-

mation in Leaded and Lead-Free Solder Alloys PHM for Field-Deployed Electronics Subjected to Multiple

Thermal Environments Leadfree Part Reliability, Crack Propagation and Life Predic-

tion under Extreme Environments The Effects of Environmental Exposure on Underfill Behavior

and Flip Chip Reliability Models for Underfill Stress-Strain and Failure Behavior with

Aging Effects Insitu Die Stress Measurements in Flip Chip Packaging Modeling and Material Characterization for Flip Chip Packag-

ing Theoretical and Experimental Investigation on Fretting Corro-

sion and Thermal Degradation for Hybrid and Electric Vehicles Complaint Pin/Press Fit Technology Model Simulation and Validation for Vibration-Induced Fret-

ting Corrosion Vibration Based Interfaces for Information Transmission Microstructural and Mechanical Studies of SAC/Sn-37Pb

Mixed Solders Aging Behavior of Next Generation Pb-Free Alloys Extreme Low Temperature Behavior of Solders Composition, Microstructure, and Reliability of Mixed Formu-

lation Solder Joints QFP Reliability on Powered and Non-powered Thermal Cycle

Environment Harsh Environment Substrate Performance Module Overmolding for Harsh Environments Systems Reliability of Lead Free for Harsh Environment The Fall-Review is on September 14-15, 2011. A block of rooms has been reserved for Review attendees at the preferred group rate. Room block will expire on September 3, 2011. Contact Information: Auburn University Hotel & Conference Center 241 South College Street Auburn, AL 36830 Call: (334) 821-8200

SPECIAL EVENTS 2011 IEEE International Conference on Prognostics and Health Management (Sponsored by the IEEE Reliability Society) Contact: Pradeep Lall, CAVE3, Auburn University

June 20-23, 2011 Hyatt Regency Denver Tech Center, Denver, Colorado Meeting Overview The IEEE Reliability Society is proud to sponsor its annual 2011 International Conference on Prognostics and Health Management (IEEE PHM2011)! The IEEE PHM Conference is bringing to-gether the expertise of relevant technical and management commu-nities for facilitating cross-fertilization in this broad interdiscipli-nary technical area. Benefits attending the conference include: Networking among companies Business opportunities Sharing of manufacturing best practices Information on issues impacting the industry Information on advances in technology and continuous im-

provement Paper Awards candidates – up to 10 Awards Around 10% of authors will be selected for paper submittal for

annual PHM Special Edition Section within the IEEE Transac-tions on Reliability

Non-selected papers will be reviewed for publication within the new PHM section of the RS Newsletter, per author agreement

Conference focuses on following activities: Scientific methodologies for PHM research Collaboration and communication between academic, govern-

ment, and industry PHM communities across the globe Innovative business PHM approaches Lead investigator successes and lessons learned in PHM devel-

opment / implementation All aspects of PHM – testability, diagnostics, prognostics,

health management Across all its pertinent disciplines – system engineers, PHM

engineers, design engineers, software system / design engi-neers, device / sensor engineers, safety engineers, CAE appli-cations designers, and measurement scientists

Technologies at all levels – from sensors (HW) and logic (SW) to system of systems

Broad product utilization aspects

CAVE3 Review

CAVE3 NEWS Summer 2011 2

Determination of RUL in Field Deployed Electronics Subjected to Sequential thermal aging and cycling Electronic assemblies deployed in harsh field environments may be exposed to multiple thermal environments during their service life. Aging has been previously shown to effect the reliability and con-stitutive behavior of second-level lead-free interconnects. Deployed systems may be subjected to cyclic thermo-mechanical loads subse-quent to deployment. Prognostication of accrued damage and as-sessment of residual life is extremely critical for ultra-high reliabil-ity systems in which the cost of failure is too high. In this paper, micro-processor assemblies previously deployed in the field envi-ronment have been procured and interrogated for accrued thermo-mechanical damage. The remaining useful life has then been as-sessed in these assemblies in a future desired thermo-mechanical environment. The presented methodology uses leading indicators of failure based on micro-structural evolution of damage to identify impending failure in electronic systems subjected to sequential stresses of thermal aging and thermal cycling.

Figure: (a) Problem definition (b) Image Analysis (c) Result of LM algorithm (d) Prognostic Metric Examples of damage pre-cursors include micro-structural evolution of second level solder interconnects, inter-metallic com-pound growth, stress and stress gradients. Pre-cursors have been developed for both eutectic 63Sn37Pb and various lead-free alloy compositions like Sn4Ag0.5Cu, Sn3Ag0.5Cu, Sn1Ag0.5Cu, Sn0.3Ag0.7Cu, Sn3Ag0.5Cu-Bi, Sn3Ag0.5Cu-Bi-Ni, 96.5Sn3.5Ag alloy systems on a variety of area-array architectures. Developed PHM technique is based on non-linear least-squares method called Levenberg-Marquardt Algorithm. Results of interrogation of system state have been compared with a second set of experimental-matrix to validate the proposed methodology. A subset of assemblies has been tested to failure in the future environment to validate the as-sessed remaining useful life. Prognostic metrics including α-λ met-

ric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to compare the performance of the damage proxies. High Strain-Rate Mechanical Properties of SnAgCu Lead-free Alloys Electronic products are subjected to high G-levels during mechani-cal shock and vibration. Failure-modes include solder-joint fail-ures, pad catering, chip-cracking, copper trace fracture, and under-fill fillet failures. The second-level interconnects may be experi-ence high-strain rates and accrue damage during repetitive exposure to mechanical shock. Industry migration to lead-free solders has resulted in a proliferation of a wide variety of solder alloy composi-tions. Few of the popular tin-silver-copper alloys include Sn1Ag0.5Cu, Sn2Ag0.5Cu and Sn3Ag0.5Cu. The high strain rate properties of lead-free solder alloys are scarce. Typical material tests systems are not well suited for measurement of high strain rates typical of mechanical shock. Previously, high strain rates techniques such as the Split Hopkinson Pressure Bar (SHPB) can be used for strain rates of 1000 per sec. However, measurement of materials at strain rates of 1-100 per sec which are typical of me-chanical shock is difficult to address. In this work, a new test-technique developed by the authors has been presented for measure-ment of material constitutive behavior. The instrument enables attaining strain rates in the neighborhood of 1 to 100 per sec. High speed cameras operating at 300,000 fps have been used in conjunc-tion with digital image correlation for the measurement of full-field strain during the test. Constancy of cross-head velocity has been demonstrated during the test from the unloaded state to the speci-men failure. Solder alloy constitutive behavior has been measured for SAC105, SAC305 solders. Constitutive model has been fit to the material data. In addition, a bi-material specimen has been de-veloped for characterization of interface properties with various notch angles to simulate the effect of joint geometry in the vicinity of the PCB pad or the package pad. Samples have been tested in pristine condition just after fabrication and after various periods of time in thermal aging. The constitutive model has been embedded into an explicit finite element framework for the purpose of life-prediction of lead free interconnects. Test assemblies has been fab-ricated and tested under JEDEC JESD22-B111 specified condition for mechanical shock. Model predictions have been correlated with experimental data. Figure: Comparison of Strain measured at failure location and extensometer

Research Highlights


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Reliability Studies and Life Prediction Models for Package-On-Package Components in Drop and Shock Environments The consumer electronics industry stands at a critical juncture where manufacturers strive to incorporate more functionality in smaller packages. In the highly competitive consumer electronics market, a continued demand for products with smallest possible form-factor yet high functionality has led to the proliferation of 3D packaging technologies. Package-on-Package (PoP) architectures, in particular have attracted a lot of interest, especially in portable electronics industry. Accounting for the lack of in-plane space for package landings in compact electronic assemblies, the PoP tech-nology allows for vertical integration of memory modules and logic dies into a single stack. The advantages of these stacked 3D archi-tectures include simplified and compact design, savings of board space allowing for more package landings, reduced pin counts and optimized production costs. Despite rapid growth of PoPs especially in portable electronics industry, the reliability issues associated with their shock and thermal performances and dependence of reliability on production variables hinders their wide acceptance. Previously, researchers have outlined package stacking process guidelines for Reliable PoP assembly and studied the war-page issues associated with package stacking processes. Different PoP package types like bare-die PoP, Embedded Solder On Pad (eSOP) PoP, and Laser-Via PoP have been compared in terms of their ease of assembly and feasibility of adoption as the package stacks become more compact. The effects of molding compound and substrate material properties on package warpage during reflow and underfill dispensing type and POP ball alloy type on the drop/shock and thermal reliability of POP devices has also been evalu-ated. While a lot of recent research, in the field of PoP architec-tures has been focused on development of optimum production methods and warpage control during reflow, the reliability issues associated with PoP assemblies in drop and shock environments have largely been neglected. Since PoP architectures find their ap-plications mainly in portable electronics, which are susceptible to frequent drops and careless handling at the hand of the consumer, the reliability of Pop architectures in environments representative of the real world is critical to their success in the industry. As a part of this study, Single component PoP test vehicles have been fabricated as per JEDEC standards for quantifying the reliability of PoP packages in drop and shock. Daisy chained double-stack PoP components have been used with the IOs in the assembly classified into three different net-lists for precise failure isolation and subsequent drop/shock performance analysis. Experimental strain data acquired using Digital Image Correlation and high speed continuity data- for identifying failure is to be used in conjunction with validated FE simulations of drop test events; for development of life prediction models for PoP architectures. Validated FE simu-lations are to be used to predict strains in critical solder balls in both layers of the PoP stack. The experimental failure counts along with FE predicted strains in critical IOs will be used, along with non-linear programming methodologies for development of strain-life based life prediction models for PoP assemblies. The drop/shock

reliability studies and life prediction models to be developed as a part of this study, will present an insight into PoP failures and elimi-nate the need for exhaustive testing procedures.

Figure: PoP Assembly Prognostics Using Kalman-Filter Models and Met-rics for Risk assessment in BGAs Under Shock and Vibration Loads Structural damage to BGA interconnects incurred during vibration testing has been monitored in the pre-failure space using resistance spectroscopy based state space vectors, rate of change of the state variable, and acceleration of the state variable. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-of functionality are too high to bear. Future states of the system has been estimated based on a second order Kalman Filter model and a Bayesian Framework. The measured state vari-able has been related to the underlying interconnect damage in the form of inelastic strain energy density. Performance of the prognos-tication health management algorithm during the vibration test has been quantified using performance evaluation metrics. The method-ology has been demonstrated on leadfree area-array electronic as-semblies subjected to vibration. Model predictions have been corre-lated with experimental data. The presented approach is applicable to functional systems where corner interconnects in area-array packages may be often redundant. Prognostic accuracy, precesion and error metrics have been used to assess the performance of the damage proxies. The presented approach enables the estimation of

Research Highlights


Image Courtesy: Indium Corporation

residual life based on level of risk averseness. The described meth-odology for predicting remaining useful life of an electrical compo-nent, and determining the appropriate time to schedule maintenance and the performance of the prediction scheme are shown in the Figure below. Figure : Methodology for predicting remaining useful life in an electrical component and scheduling maintenance Figure: Performance evaluation of PHM method using resistance spectroscopy for BGA components The Effects of Variations in Manufacturing on PCB Thermal Properties The thermal performance of an electronic device is heavily depend-ent on the properties of the printed circuit board (PCB) to which it is attached. However, even small variations in the process used to fabricate a PCB can have drastic effects on its thermal properties. Therefore, it is necessary to experimentally verify that each stage in the manufacturing process is producing the desired result. Two vendors were asked to produce PCBs from the same design. The steady state thermal resistances of 1” by 1” sections of these PCBs were then measured with a comparative cut bar appara-tus based on ASTM D 5470-06 and the thickness of each of the layers was measured. Despite being fabricated from the same de-sign, there were significant differences between the stack-ups of the two boards, as shown in the Figures, and the thermal resistances varied by as much as 30%. The vendor with the higher thermal resistance was then asked to produce a second set of boards with an identical stack-up to the one used by the other vendor. However, even with the same design and identical stack-ups, the thermal re-sistance still varied by as much as 20%.

Figure : Cross sections showing variations in stack up between vendors. Figure : Cross sections of filled and unfilled vias showing a thicker layer of copper lining the inside wall of the vias in the unfilled boards than in the filled boards. A vendor was asked to produce two identical PCBs with the exception that one was to have the vias filled with an epoxy while the vias in the other boards were to be left empty. It was ex-pected that, even though the epoxy did not have an especially high thermal conductivity, it would still conduct more heat than the air it was replacing, and therefore the PCBs with the filled vias would have a lower thermal resistance that the PCBs with the unfilled vias. However, after measuring the thermal resistances with a compara-tive cut bar apparatus, the opposite turned out to be true: the un-filled vias had a lower thermal resistance than the filled vias. After further investigation, it was found that the PCBs with the epoxy filled vias had a thinner layer of copper around the walls of the vias than did the unfilled vias, as shown in the Figure. This was a side effect of the order in which the vendor chose to perform the fabrica-tion steps, i.e. the vias were filled prior to the final plating step. As a result, the thermal improvement provided by the epoxy was coun-teracted by the degradation of the thermal path through the via walls.

Research Highlights


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SIF Evaluation using XFEM and Line Spring models under High Strain Rate Environment for Lead-free alloys In this paper, fracture properties of Pb-free alloys at dynamic condi-tions are evaluated and validated with those from experimental methods. Bi-material and single material Copper-Solder specimen are tested at strain rates typical of shock and vibration with Uniaxial tensile testing machine. Models for crack/flaw initiation and propa-gation are developed using Line spring method and extended finite element method (XFEM). Critical stress intensity factor for leadfree alloys such as Sn3Ag0.5Cu and Sn1Ag0.5Cu are extracted from line spring models. Stress intensity factor at Copper pad and bulk solder interface is also evaluated in ball grid array packages. Dis-placements and derivatives of displacements are measured at crack tip and near interface of bi-material specimen using high speed im-aging in conjunction with digital image correlation. Specimens are tested at various strain rates and event is monitored using high speed data acquisition system as well as high speed cameras operat-ing more than 50,000 fps. Previous researchers have applied the technique of XFEM and DIC for predicting failure location and to develop constitutive models in leaded and few leadfree solder alloys [Lall 2010]. Previous researchers have also applied XFEM in vari-ous other fields such as concrete, composite materials [Unger 2007, Hettich 2008]. In this work fracture properties such as SIF and J integral are measured using simulation techniques and correlated with experimental results. Also fracture properties at IMC layer for BGAs under shock environment is something new.

Figure: Initiation and Propagation in Bimaterial Copper-Solder specimen under Uniaxial Tensile Test

Monitoring In Portable Electronics under Mechani-cal Shock Electronic systems under extreme shock and vibration environments including shock and vibration may sustain several failure modes simultaneously. Previous experience of the authors indicates that the dominant failure modes experienced by packages in a drop and shock frame work are in the solder interconnects including cracks at the package and the board interface, pad cratering, copper trace fatigue, and bulk-failure in the solder joint. In this project, a neural network baes frame work is developed for failure mode classifica-tion in electronics under mechanical shock. Figure-below represents the designed network used for fault mode parity in test assemblies. The prefailure feature space is de-correlated using KL-transform. Hard parity between different faulire modes is achieved using step-wise supervised training of a perceptrons. Pre-failure feature space has been formed by joint time frequency distribution for the classi-fication of different fault modes in electronic assemblies subjected to drop and shock. Since the cumulative damage may be accrued under repetitive loading with exposure to multiple shock events, the area array assemblies have been exposed to shock and feature vec-tors constructed to track damage initiation and progression. The classified failure modes and failure regions belonging to each par-ticular failure modes in the feature space are also validated by simu-lation of the designed neural network used for parity of feature space. The methodology adopted in this paper can perform real-time fault monitoring with identification of specific dominant fail-ure mode. The supervised learning approach presented in this work is scalable to system level reliability. Supervised methodology pro-posed in this work is capable/inclusive of addressing damage initia-tion and progression as well as fault isolation is new in prognostics and health management framework for electronics.

Figure: Designed Neural network for Fault isolation in test assem-blies.

Research Highlights


T=3.4412msT=3.4411ms

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Statistical Modeling for predicting life and accel-eration factor for BGAs Life-prediction models for lead-free solders are being developed based on statistical methods such as regression for reliability predic-tion and part selection of area-array packaging architectures under thermo-mechanical loads. Methods such as Ridge regression, PCR are being used to address the multi-co linearity between input ge-ometry, material, and environmental variables which exist in data-sets preventing incorporation of several input terms in regular mul-tiple linear regression models. Models have been developed in con-junction with Stepwise Regression Methods for identification of the main effects. Package architectures studied include, BGA packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. Packages with different SAC solder alloy interconnects have been examined. The models have been devel-oped based on perturbation of accelerated test thermo-mechanical failure data. Data has been gathered on several different thermal cycle conditions with SAC alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature and minimum temperature. In addition, model predictions have been validated against validation data-sets which have not been used for model development. Convergence of statistical models with experi-mental data has been demonstrated using a single factor design of experiment study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated.

Figure: (a) ModelValidation(T) (b) Ridge Regression

Reduction of Lead Free Solder Aging Effects using Doped SAC Alloys The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolv-ing when exposed to isothermal aging and/or thermal cycling envi-ronments. In our prior work on aging effects, we have demon-strated that large degradations occur in the material properties (stiffness and strength) and creep behavior of Sn-Ag-Cu (SAC) lead free solders during aging. These effects are universally detrimental to reliability and are exacerbated as the aging temperature and aging time increases. Conversely, changes due to aging have been shown to be relatively small in conventional Sn-Pb solders. Aging effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing

Research Highlights


and in automotive, aerospace, and defense applications. In the cur-rent investigation, we have extended our previous studies to include a full test matrix of aging temperatures and SAC lead free solder alloys. In an attempt to reduce the aging induced degradation of the material behavior of SAC solders, we are also exploring various doped SAC-X alloys. These materials are SAC solders that have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, Zn, etc.) has become widespread to enhance shock/drop reliability, wetting, and other properties; and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on solder sam-ples that were aged for various durations (0-6 months) at room tem-perature (25 oC), and several elevated temperatures (50, 75, 100, and 125 oC). Four “standard” SAC alloys have been examined in this work including SAC105, SAC205, SAC305, and SAC405. This selection has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). The doped SAC solder materials being considered in our ongoing stud-ies include SAC0307-X, SAC105-X, and SAC305-X. In this work, we will concentrate on presenting the results for SAC0307-X (SAC-X), where X is 0.1%Bi. This alloy has been proposed as a lower cost SAC variation suitable for enhancing drop reliability. For all of the solders, variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. Our findings show that the doped SAC-X alloy illustrates reduced degradations with aging for all of the aging tem-peratures considered. The stress-strain and creep mechanical prop-erties of SAC-X are better than those of SAC105 after short dura-tions of aging, and approach those of SAC205 with longer aging times. After long term aging, the SAC-X alloy was found to have more stable behavior than all of the standard SACN05 alloys. Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes.

Figure: SAC-X Creep Rate Evolution with Aging at 100C, and Comparisons to SAC105 and SAC205

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Figure: Variation of Ultimate Tensile Strength of SAC-X with Aging at 100 oC, and Comparisons to SAC105 and SAC205 Finite Element Modeling of the Buildup of Compres-sive Stresses in a Microprocessor Chip by Packaging and Heat Sink Clamping Microprocessor packaging in modern workstations and servers of-ten consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configu-ration features a complex stack up of flip chip area array solder in-terconnects, underfill, ceramic substrate, lid, heat sink, thermal in-terface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packag-ing architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free sol-der joints, higher level of power generation, and larger heat sinks. Die stress effects are of concern due to the possible degradation of silicon device performance (mobility/speed) and due to the possible damage that can occur to the copper/low-k top level interconnect layers. In this work, we have used finite element analysis to pre-dict the stresses induced in microprocessor die after various steps of the assembly process, as well as to as well as due to heat sink clamping and subsequent powered operation (stress evolution dur-ing thermal cycling and power cycling). The developed normal stresses are compressive (triaxial compression) across the die sur-face, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, un-derfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa and approach-ing 1 GPa have been observed for extremely high heat sink clamp-ing forces. A novel sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. The numerical results were correlated with experimental measurements using test chips containing piezoresistive sensors. The utilized (111) silicon test chips were able to measure the com-plete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. With

suitable detail in the finite element models, excellent correlation has been obtained with the sensor data throughout all packaging proc-esses and during heat sink clamping.

Figure: (a) Quarter symmetric model for assembly process. (b) Cir-cular non-uniform pressure distribution applied on the top surface of the lid in heat sink clamping simulation.

Whisker Growth In Controlled Humidity Exposure Studies of Sn whiskers under controlled, calibrated humidity condi-tions shows that the highest whisker densities occur for ~ 85% RH. The whisker specimens were 1500 Å Sn films sputtered under com-pressive stress conditions on silicon and electrochemically polished brass. Subsequently, the samples were exposed to a series of satu-rated aqueous salt solutions (which generated calibrated relative humidity values of 33, 43, 70, 76, 85, 98% RH) for ~140 days at room temperature. The Sn on brass case at 85% RH produced 6X greater whisker densities than Sn on brass exposed to pure O2, which in turn produced 9X greater whisker densities than Sn on brass exposed to ambient room temperature/humidity. The longest average whiskers lengths (6.1 µm for Sn on brass and 9.3 µm for Sn on Si) occurred for 70% RH on both substrates. Some corrosion was seen on all samples, but the 98% RH samples by far experi-enced the greatest amounts of corrosion. Thus, we find a dramatic increase in whisker density at >60% RH and especially around 85% RH, in general agreement with batch processed whisker experi-ments involving humidity [H. Reynolds et. al., IEEE Trans. Elec-tron. Packag. Manuf. 33 (2010) 1., and P. Oberndorff et. al., IEEE Electronic Comp. and Tech. Conference (2005) 429].

Figure: Whisker growth for a Sn film on brass after 92 hrs

Research Highlights


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Die with 900 Solder Balls

Global

CAVE3 Researchers receive Best of Conference-Proceedings Paper Award at SMTAI 2010, Orlando, FL SMTA celebrated its 26th anniversary in 2010. CAVE³ researchers were awarded the “Best of Proceedings” award for their paper titled “Interrogation Of Damage-State In Lead-Free Electronics Under Sequential Exposure To Thermal Aging And Thermal Cycling” co-authored by Pradeep Lall, Rahul Vaidya, Vikrant More, Kai Goebel. The award will be presented on October 16-20, 2011 at the SMTAI Opening Ceremony during SMTA International in Ft. Worth, Texas.

CAVE3 Researchers Win Best-Paper of Conference Award at ECTC 2010 CAVE3 Researchers received the Best of Session-Paper Award for their paper titled: Reduction of Lead Free Solder Aging Effects us-ing Doped SAC Alloys, Zijie Cai, Yifei Zhang, Jeffrey C. Suhling, Pradeep Lall, R. Wayne Johnson, Michael J. Bozack, at the 60th Electronic Component and Technology Conference held in Las Ve-gas, Nevada, June 1-4, 2010. The ECTC comprises papers covering a wide spectrum of topics, including electronic components, materi-als, assembly, interconnections, packaging, system packaging, opto-electronics, reliability, and simulation.

Dr. Evans Chairs CAVE3-SMTA Harsh Environments Symposium at the SMTAI 2010, Orlando, FL SMTAI-AIMS conference was held in conjunction with the SMTAI Conference. The conference had an exceptional group of authors and speakers. This years technical program included papers and presentations that cover a wide range of topics including BGA’s, chip scale packaging, prognostics, component and substrate issues, and manufacturing excellence. Tom Sharpe from SMT Corporation gave keynote on “Counterfeit Components Are Everywhere - What’s Your Strategy?”. Harsh Environment Track was chaired by Dr. John Evans.

Dr. Lall to give Technical Keynote and Tutorial at Eu-roSimE 2011 Dr. Pradeep Lall is invited for a technical keynote on the topic of Prognostics Health Monitoring of Electronic Systems at the 12th IEEE European Conference on Thermal, Mechanical and Mul-tiphysics Simulation and Experiments in Micro-Nanoelectronics and Systems to be held in Linz, Austria, April 18-20, 2011. He will also give a professional development short-course on the topic of “Prognostics and Health Monitoring of Electronic Systems in Shock, Vibration and Thermo-mechanical Environments”.

Dr. Lall Appointed to the IEEE Reliability Society Advi-sory Committee (AdCom) Pradeep Lall was appointed to the Reliability Society Advisory Committee to lead the Prognostics Health Management thrust for the IEEE Reliability Society. In this capacity he will be developed the new Prognostics Section of the IEEE Reliability Society News-letter and developing the Professional Development Short-Courses for the IEEE PHM 2011 Conference to be held in Denver Colorado, June 20-23, 2011.

Ryan Lowe along with Dr. Refai-Ahmed Gamal, at EPPD Reception at ASME-IMECE2010 Vancouver, BC, Canada.

CAVE3 Student receives ASME Student Member Award at ASME-IMECE 2010 CAVE3 Researcher Prashant Gupta, was selected as ASME Student Member Award by Electronic Packaging and Photonic Division (EPPD) of ASME. Prashant Gupta is a doctoral student advised by Professor Pradeep Lall, in Mechanical Engineering Department at Auburn University. His dissertation work focuses on Prognostics and Health Monitoring of Electronic Systems under Drop and Shock. The award was presented at EPPD Wine and Cheese Recep-tion at ASME-IMECE in Vancouver, BC, Canada on Wednesday, November 17, 2010. NSF-CAVE3 group on LinkedIn Join NSF-CAVE3 group on Linkedin. The group is now live and can be used for expanding your professional network. It gives mem-ber companies an active forum for discussion, a chance to connect to CAVE3 students who are looking for active career opportunities, interactions and discussions. Member interested in joining the group should submit a join-request through LinkedIn. CAVE3 Students Invited to Present Posters at NSF-Symposium, ASME-IMECE 2010 CAVE3 Researchers Prashant Gupta, Ryan Lowe, Arjun Angral advised by Professor Pradeep Lall presented posters at NSF sympo-sium at IMECE2010. The symposium consisted of over 40 students from various field of mechanical engineering. The poster of CAVE3 researchers focused on prognostics of electronic assemblies in harsh environments. The presentation was well received by panel of judges. The invitation included stipend which allowed CAVE3 stu-dents to attend a week long conference.

CAVE3 Faculty Guest Editor for Special Issue of ASME Journal of Electronic Packaging on PHM Pradeep Lall is the Guest-Editor for the Special Issue of ASME Journal of Electronic Packaging on Prognostic Health Management of Electronic Systems. PHM has emerged as a key enabling tech-nology to provide an early warning of failure. Early warning may be used to forecast planned-maintenance and assess the potential for life extensions. PHM has been applied to machines, aircraft, bridges, electronics, and bio-implantable systems. Topics to be


Announcements

included in this special section on Prognostic Health Management for Electronics include: Component and system level prognostic health monitoring for electronics, Prognostic methods for electron-ics subjected to harsh environments, Prognostic sensors for elec-tronics, Real time monitoring of leading indicators of failure in electronics, Fault mode classification in electronics based on prog-nostic sensors, Uncertainty management for decision-support based on prognostic information for electronics, Prognostics for lead, lead-free, and re-balled components, Adaptive control and risk mitiga-tion based on prognostic information in electronics, and Imple-mented prognostic health management systems for electronics.

Lall Serves as General Chair of the ASME International Mechanical Engineering Congress 2010 Dr. Lall served as the General Chair for the ASME Mechanical En-gineering Congress and Exposition at Vancouver, BC from Novem-ber 12-18, 2010. The technical program focused on the engineer-ing's cutting-edge research and development and how it will deter-mine the evolution of technology worldwide. In part of preparation for the Congress over the past one-year, Lall has worked as member of the Congress Steering Committee to develop a strategic vision for multi-disciplinary content and future direction of the IMECE. The 2010 Congress is focused on cross-pollination between disci-plines, research and innovation over four days.

CAVE3 Researchers at ASME-IMECE2010. From left to right: Prashant Gupta, Ryan Lowe, Arjun Angral. Lall Appointed Track-Co-Chair for the ASME Inter-PACK 2011 Professor Lall will serve as the Track Co-Chair for the ASME Inter-PACK 2011 Conference to be held in Portland, Oregon, July 6-8, 2011. CAVE3 researchers are scheduled to present 8-technical Pa-pers at the conference. InterPACK'11 is an international forum for exchange of state-of-the art knowledge in research, development, manufacturing, and application on the packaging and integration of Electronic and Photonic Systems, MEMS, and NEMS. This confer-ence will be the 11th in the InterPACK series that began in 1993. It is the flagship technical meeting of the ASME Electronic and Photonic Packaging Division (EPPD), with the participation of JSME, IEEE-CPMT, and iNEMI.

Dr. Lall and Ryan Lowe to Give Professional Shortcourse at PHM 2011 Professor Lall and doctoral candidate Ryan Lowe will give a short-course at the PHM 2011 to be held in Denver, Colorado, from June 20-23, 2011. The short course is on the topic of Prognostics Health Management of Electronic Systems in Harsh Environments. Top-ics covered include Approaches for monitoring system health Methods for data analysis Leading indicators of failure for various types of failure mecha-

nisms Algorithms for data reduction and parameter extraction Approaches for residual life estimation Statistical assessment of uncertainty of system survivability in

future deployment The course is intended to introduce the students to PHM solutions for electronic systems using early indicators of failure for scheduled maintenance and assessment of system survivability of a deployed system. Specifically the students will have the knowledge needed to: Identify solutions for health monitoring of products and sys-

tems Use leading indicators-of-failure for various electronic failure

mechanisms Develop algorithms and models for data reduction and parame-

ter extraction Implement methods for assessment of accrued damage Use statistical techniques for assessment of uncertainty


Announcements

1. Lall, P., Gupta, P.; Kulkarni, M.; Hofmeister, J.; Time–Frequency and Autoregressive Techniques for Prognostication of Shock-Impact Reliability of Implantable Biological Elec-tronic Systems, Electronics Packaging Manufacturing, IEEE Transactions on, Volume: 33 , Issue: 4, Page(s): 289 - 302, 2010.

2. Lall, P., Bhat, C., Hande, M., More, V., Vaidya, R., Goebel, K., Prognostication of Residual Life and Latent Damage Assess-ment in Lead-free Electronics Under Thermo-Mechanical Loads, IEEE Transactions on Industrial Electronics, Volume 99, DOI: 10.1109/TIE.2010.2089936, pp. 1-13, 2010.

3. Lall, P., Vaidya, R., More, V., Goebel, K., Assessment of Ac-crued Thermo-Mechanical Damage in Leadfree Parts During Field-Exposure to Multiple Envts, SMTA Journal, Vol. 23(2), pp. 11-24, 2010.

4. Lall, P., Gupta, P., Failure-Mode Clustering for Electronics Under Shock and Vibration Using Neural-Net Based Self-Organized Maps ASME-IMECE-40666, pp. 1-15, Vancouver, BC, Canada, Nov. 12-18, 2010.

5. Lall, P., Vaidya, R., More, V., Goebel, K., Prognostic Health Monitoring of Damage Progression in Leadfree Electronics Under Sequential Exposure to Thermal Aging and Thermal Cycling, ASME-IMECE-40668, pp. 1-14, Vancouver, BC, Canada, Nov. 12-18, 2010.

6. Lall, P., Lowe, R., Goebel, K. Residual Life Estimation of Lead-Free Electronics in Shock and Vibration using Kalman Filter Models, SMTAI Technical Conference, pp. 118-131, Orlando, FL, Oct 24-28, 2010.

7. Lall, P., Kulkarni, M., Angral, A., Survivability Assessment Of Advanced Interconnects And Lead-Free Electronics Subjected To Shock And Vibration With XFEM And CZM, SMTAI Technical Conference, pp. 163-178, Orlando, FL, Oct 24-28, 2010.

8. Lall, P., Vaidya, R., More, V., Goebel, K., Interrogation Of Damage-State In Lead-Free Electronics Under Sequential Ex-posure To Thermal Aging And Thermal Cycling, SMTAI Technical Conference, pp. 405-418, Orlando, FL, Oct 24-28, 2010.

9. Li, Z., Lee, S., Lewis, B.J., Houston, P.N., Baldwin, D.F., Stout, G., Tessier, T., Evans, J.L., Pb-Free Reflow Process Study for High Yield, High Reliability Flip Chip on Silicon Substrate Assembly., SMTAI Technical Conference, pp. 207-214, Orlando, FL, Oct 24-28, 2010.

10. Lall, P., Gupta, P., Kulkarni, M., Hofmeister, J., Time–Frequency and Autoregressive Techniques for Prognostication of Shock-Impact Reliability of Implantable Biological Elec-tronic Systems IEEE Transactions on Electronics Packaging Manufacturing, Vol. 33, No. 4, pp. , 289-302, October 2010

11. Bozack, M. J., Crandall, E. R., Rodekohr, C. L., Dean, R. N., Flowers, G. N. Suhling, J. C., High Lateral Resolution Auger Electron Spectroscopic ( AES) Measurements on High-Aspect Ratio Sn Whiskers on Brass, IEEE Trans. Components and Packaging Technologies, Vol. 33, 3, p. 198-204, May 2010.

12. Crandall, E.R., Flowers, G.T., Bozack, M.J.,Oxidation-Induced Growth of Sn Whiskers Due to Pure Oxygen Gas Exposure,

Proc. 56th IEEE Holm Conference on Electrical Contacts, Charleston, SC, Oct 4-7, 2010.

13. Crandall, E.R., Flowers, G.T., Bozack, M.J., Growth of Sn Whiskers on Semiconductor and Insulator Surfaces, Proc. 56th IEEE Holm Conference on Electrical Contacts, Charleston, SC, Oct 4-7, 2010.

14. Maddox, J. F., Knight, R.W., Bhavnani, S.H., Non-Uniform Thermal Properties of an Alumina Granule/Epoxy Potting Compound, ITherm '10, pp. 1-6, Las Vegas, NV, June 2-5, 2010.

All other published CAVE3 articles are available at cave.auburn.edu under Publications

Selected Recent Publications


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