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Built-In Self-Test (BIST) and Built-In Self-Repair

(BISR) techniques in syncronous memory devices

Alberto Rui Frutuoso BarrosoIntegrated Master in Electrical and

Computers Engineering

Faculdade de Engenharia da Universidade do Porto

Porto, Portugal

Email: http://www.fe.up.pt/ee07094

AbstractThe use of a symmetrical BIST system in prefetchedmemory architectures, associated with BISR adaptative field pro-grammable redundancy mechanisms, can increase the productionyield at wafer level, transfer auto-test operations to the exteriorof the microprocessor, and will allow to auto-repair or replacememory cells during the normal operation on the end product.

I. INTRODUCTION

The current CMOS manufacturing processes using sub

100nm resolutions allows the development of Multi-Gigabit

discrete memory devices, and to integrate several megabits of

memory in microprocessors and in application specific inte-

grated circuits (ASIC). Due to the fact that the number of dies

without defects present in the wafer diminish with the increase

of the number of storage cells [1], BISR and BIST mechanisms

must be implemented in RAM products to rescue dies from

wafers that have a yield of zero (all dies are defective before

wafer level repair operations). Integrated in standard JEDEC

RAM devices [2], the BIST and BISR mechanisms proposed

in this paper will introduce a new production flow for devices

that are partially tested during the front-end and back-end man-ufacturing operations. This new production flow will be added

to the current low power, industrial/military temperature and

high speed test flows, recovering RAM devices that my be used

as main memory in embedded systems with parallel processing

architectures in price competitive consumer, communications

and computers (CCC) products. This new type of RAM (with

mirror BIST) can be used in mechatronic equipment used in

harsh and remote environments, allowing to soft repair failing

memory locations in the power on self-test (POST), and as a

background task during normal operation.

ARFB

July, 2008

I I . MIRROR BIST

A. Description

The mirror BIST mechanism developed in this work was

projected to be integrated in multiple banks prefetched mem-

ory devices, with the addition of soft repair capabilities to the

conventional hard repair (laser fusing or electrical anti-fuses)

redundant memory elements. Using a remapping scheme to

store a n bit wide failing address in a typical m bits wide

data bus (m

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B. Implementation

To evaluate the area used in the die to implement the mirror

BIST mechanism, a Xilinx Spartan-3 (X3S400) FPGA was

used to sinthetize a reference datapath and the datapath with

mirror BIST. The reference datapath is similar to the datapath

used in DDR devices: minimal control pins, multiplexing of

the address lines, and burst operations counter. In a DDR

device this datapath is normally located between the output ofthe sense amplifiers, and the DDR FIFO and output registers.

The datapath with Mirror-BIST have the same structure as

the reference datapath, with the additional inclusion of bus

multiplexers and BIST control logic. Both datapath implemen-

tations where done in Verilog, and sinthetized and tested in the

developed FPGA system.

Fig. 1. Mirror BIST: state machine

A bare bones version of the mirror BIST was implemented

using a symmetrical state machine (figure1), with the objec-

tive to obtain a solution with a minimal die overhead. This

value will be used as a base reference for comparison with

more complete (with checkerboard and stripes test topologygeneration) microcode implementations of the mirror BIST.

The area occupied by the storage cells was not included in

the calculation of the die overhead, because this is a mixed

signal area using distinct cell topologies (8F2, 6F2, 4F2)

with different types of sense amplifiers (folded, open, hybrid).

The die overhead was calculated using the area taken in the

placement of logic cells in the exterior of the matrix of storage

cells (the spine of the die), comparing the area needed to

implement a normal data path and a data path with the mirror

BIST. The Verilog HDL used to design this two data paths, was

synthesized in the FPGA using the Xilinx XST, and physically

(AMS 0.35m) using the Synopsis Design Compiler, and

the Cadence SOC encounter. The BIST data path synthesisreached operating frequencies equivalent to the reference data

path; a summary of the synthesis results is presented in the

table I.

III . SOFT AND ADAPTATIVE REFRESH BISR

A. Soft BISR

The main reason for the lack of adequate granularity to

repair single cell fails in RAM devices is the use of a short

number of fuses (laser cut) or anti-fuses (electrically disrupted

TABLE IMIRROR BIST DIE OVERHEAD

Software Units No BIST Mirror BIST Overhead(%)

Xilinx X ST ISE equivalent gate count 570 1622 184

Synopsys D esign C om piler total cell area 22422 37291 66

Synopsys D esign C om piler total area 25644 44086 72

Ca den ce SOC Enco unt er area 0,0233 0,0385 65

dielectric). There are physical restrictions that limit the maxi-

mum number of fuses and anti-fuses, and both suffer somereliability issues after been used. The proposed soft-BISR

(integrated with the mirror BIST) gives maximum flexibility

to the self repair mechanism present in all DRAM/SRAM

discrete devices[3]. The granularity of this soft-BISR will be

defined after some statistical evaluation of the number of SCF

present in the cell matrix, for a particular process-technology.

The repair registers will be accessed via test modes, with a

maximum number limited by die overhead issues and address

location access delay.

B. Adaptative refresh BISR

This BISR solution uses programmable refresh controllers

(PRC) distributed in the memory array, this solution wasdesigned to be used in pseudo static RAM (PSRAM), and in

the self refresh circuit of DRAM devices. In a PSRAM device,

the PRC can be integrated in the partial array refresh (PAR)

circuit and replace the temperature self refresh controller

(TCSR) used in the standby mode. The core component of the

PRC is a time measurement unit (TMU), designed to measure

the retention time of the cells failing to operate at nominal

temperature and refresh times. This TMU was implemented

in the FPGA system, using a 16 positions state machine.

IV. CONCLUSION

The feasibility of integrating a basic mirror BIST mecha-

nism in memory devices, with a die overhead in the spine zoneless than 72%, became proved using the synthesis results of

a typical DDR data path as a reference, and implementing a

state machine mirror BIST solution in this data path. Using

this BIST and BISR mechanisms we can rescue devices with

single cell fails that are tormenting the yield of the DRAM

industry, and extend the operational life of degraded memory

devices in end products.

ACKNOWLEDGMENT

I am extremely grateful to Professor Joao Canas Ferreira

for his constant support, and to Herr Christian Seibert for the

huge interest in this work.

REFERENCES

[1] A. Miczo, Digital Logic Testing and Simulation, 2nd ed. Wiley, 2003.[2] JEDEC, Joint electron device engineering council, July 2008, http://

www.jedec.org/.[3] R. Adams, High Performance Memory Testing, 1st ed. Kluwer Academic

Publishers, 2002.