SubprogramsSubprogramsSubprogramsSubprograms

SubprogramsSubprograms Similar to subprograms found in other languagesSimilar to subprograms found in other languages

Allow repeatedly used code to be referenced multiple times without Allow repeatedly used code to be referenced multiple times without rewritingrewriting

Break down large blocks of code into small, more manageable partsBreak down large blocks of code into small, more manageable parts

VHDL provides functions and proceduresVHDL provides functions and procedures

Subprograms (cont’d)Subprograms (cont’d)Subprograms (cont’d)Subprograms (cont’d) Contain sequential statements similar to processesContain sequential statements similar to processes

May declare local variables, constantsMay declare local variables, constants

Executed when called from a sequential statement.Executed when called from a sequential statement.

Local Variables are re-initialized every time a subprogram is called.Local Variables are re-initialized every time a subprogram is called.

Parameters of calling routine are known as Parameters of calling routine are known as actualactuals, while the parameters of the s, while the parameters of the declared subprogram are known as declared subprogram are known as formalformals.s.

Up level referencing to higher level variables and signals is allowed.Up level referencing to higher level variables and signals is allowed.

Recursive calls by functions and procedures are allowedRecursive calls by functions and procedures are allowed

Attributes of signals cannot be accessed within subprogramsAttributes of signals cannot be accessed within subprograms

FunctionsFunctions Produce a single return valueProduce a single return value Called by expressionsCalled by expressions Cannot modify the parameters passed to themCannot modify the parameters passed to them Require a RETURN statementRequire a RETURN statement

FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT IS VARIABLE result : BIT; -- variable is local to function

BEGINresult := (a XOR b);RETURN result; -- the two functions are equivalent

END add_bits2;

FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT IS VARIABLE result : BIT; -- variable is local to function

BEGINresult := (a XOR b);RETURN result; -- the two functions are equivalent

END add_bits2;

FUNCTION add_bits (a, b : IN BIT) RETURN BIT ISBEGIN -- functions cannot return multiple values

RETURN (a XOR b);END add_bits;

FUNCTION add_bits (a, b : IN BIT) RETURN BIT ISBEGIN -- functions cannot return multiple values

RETURN (a XOR b);END add_bits;

FunctionsFunctionsFunctionsFunctions

x

FunctionsFunctionsFunctionsFunctions

FunctionsFunctionsFunctionsFunctions

FunctionsFunctionsFunctionsFunctions

FunctionsFunctionsFunctionsFunctions

Example of a FunctionExample of a FunctionExample of a FunctionExample of a Function

Example of a Function (cont)Example of a Function (cont)Example of a Function (cont)Example of a Function (cont)

FunctionsFunctions

Functions must be called by other statementsFunctions must be called by other statements Parameters use positional associationParameters use positional association

ARCHITECTURE behavior OF adder ISBEGIN

PROCESS (enable, x, y)BEGINIF (enable = '1') THENresult <= add_bits(x, y);carry <= x AND y;

ELSEcarry, result <= '0';

END PROCESS;END behavior;

FUNCTION add_bits

(a, b : IN BIT)

ProceduresProceduresProceduresProcedures

Procedures (cont)Procedures (cont)Procedures (cont)Procedures (cont)

Procedures (cont)Procedures (cont)Procedures (cont)Procedures (cont)

Example of a ProcedureExample of a ProcedureExample of a ProcedureExample of a Procedure

Another Example of a ProcedureAnother Example of a ProcedureAnother Example of a ProcedureAnother Example of a Procedure

Summary on Sequential StatementsSummary on Sequential StatementsSummary on Sequential StatementsSummary on Sequential Statements

ProceduresProcedures May produce multiple output valuesMay produce multiple output values Are invoked by statementsAre invoked by statements May modify the parametersMay modify the parameters

PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT) IS

BEGIN -- procedures can return multiple valuestemp_result <= (a XOR b) AND en;temp_carry <= a AND b AND en;

END add_bits3;

PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT) IS

BEGIN -- procedures can return multiple valuestemp_result <= (a XOR b) AND en;temp_carry <= a AND b AND en;

END add_bits3;

Do not require a RETURN statement

Procedures Procedures (Cont.)(Cont.) With parameter With parameter

passing, it is possible passing, it is possible to further simplify the to further simplify the architecturearchitecture

ARCHITECTURE behavior OF adder ISBEGIN

PROCESS (enable, x, y)BEGINadd_bits3(x, y, enable, result, carry);

END PROCESS;END behavior;

PROCEDURE add_bits3

(SIGNAL a, b, en : IN BIT; SIGNAL temp_result,

temp_carry : OUT BIT)

The parameters must be compatible in terms of data flow and data type

Signal Resolution and BusesSignal Resolution and Buses

Bus Resolution Function

OR

AND

Execution phase Signal update phase

Resolvedsignal

Transaction queue

Bus ResolutionBus ResolutionSmoke GeneratorSmoke Generator

VHDL does not allow multiple concurrent signal VHDL does not allow multiple concurrent signal assignments to the same signalassignments to the same signal Multiple sequential signal assignments are allowedMultiple sequential signal assignments are allowed

LIBRARY attlib; USE attlib.att_mvl.ALL;-- this code will generate an errorENTITY bus IS

PORT (a, b, c : IN MVL; z : OUT MVL);END bus;

ARCHITECTURE smoke_generator OF bus ISSIGNAL circuit_node : MVL;

BEGINcircuit_node <= a;circuit_node <= b;circuit_node <= c;z <= circuit_node;

END smoke_generator;

LIBRARY attlib; USE attlib.att_mvl.ALL;-- this code will generate an errorENTITY bus IS

PORT (a, b, c : IN MVL; z : OUT MVL);END bus;

ARCHITECTURE smoke_generator OF bus ISSIGNAL circuit_node : MVL;

BEGINcircuit_node <= a;circuit_node <= b;circuit_node <= c;z <= circuit_node;

END smoke_generator;

Bus Resolution FunctionsBus Resolution Functions Are used to determine the assigned value when there are multiple Are used to determine the assigned value when there are multiple

signal drivers to the same signalsignal drivers to the same signal

FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL ISVARIABLE accumulate : MVL := '1';

BEGINFOR i IN drivers'RANGE LOOPaccumulate := accumulate AND drivers(i);

END LOOP;RETURN accumulate;

END wired_and;

FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL ISVARIABLE accumulate : MVL := '1';

BEGINFOR i IN drivers'RANGE LOOPaccumulate := accumulate AND drivers(i);

END LOOP;RETURN accumulate;

END wired_and;

Bus resolution functions may be user defined or called from a package

Bus ResolutionBus ResolutionSmoke Generator FixedSmoke Generator Fixed

A signal which has a bus resolution function associated with it may have multiple driversA signal which has a bus resolution function associated with it may have multiple drivers

LIBRARY attlib; USE attlib.att_mvl.ALL;USE WORK.bus_resolution.ALL;

ENTITY bus ISPORT (a, b, c : IN MVL; z : OUT MVL);

END bus;

ARCHITECTURE fixed OF bus ISSIGNAL circuit_node : wired_and MVL;

BEGINcircuit_node <= a;circuit_node <= b;circuit_node <= c;z <= circuit_node;

END fixed;

Null TransactionsNull Transactions How can a driver be disconnected (i.e. not influence the output at all)?How can a driver be disconnected (i.e. not influence the output at all)?

Use the null waveform elementUse the null waveform element

ExampleExamplebus_out <= NULL AFTER 17 ns;bus_out <= NULL AFTER 17 ns;

What happens if all drivers of a resolved signal are disconnected?What happens if all drivers of a resolved signal are disconnected? Use Use registerregister kind in signal declaration to keep most recently determined value kind in signal declaration to keep most recently determined value Use Use busbus kind in signal declaration if resolution function will determine the value kind in signal declaration if resolution function will determine the value

ExampleExamplesignal t : wired_bus BUS;signal t : wired_bus BUS;

signal u : BIT REGISTER;signal u : BIT REGISTER;

Concurrent Concurrent StatementStatement

Concurrent Concurrent StatementStatement

Exists outside of a process but in an architectureExists outside of a process but in an architecture

The process is itself a concurrent statement all processes The process is itself a concurrent statement all processes scheduled to run concurrentlyscheduled to run concurrently

Concurrent signal assignment Concurrent signal assignment is a short hand form for a single is a short hand form for a single statement process -- equivalent to process containing one statement process -- equivalent to process containing one statement, sensitive to changes on the right hand side.statement, sensitive to changes on the right hand side.

Used frequently in DATAFLOW style descriptionsUsed frequently in DATAFLOW style descriptions

The ProcessThe ProcessThe ProcessThe Process

Concurrent Signal Concurrent Signal AssignmentAssignment

Concurrent Signal Concurrent Signal AssignmentAssignment

Concurrent Assignment Concurrent Assignment StatementsStatements

Concurrent Assignment Concurrent Assignment StatementsStatements

Concurrent Signal SensitivityConcurrent Signal SensitivityConcurrent Signal SensitivityConcurrent Signal Sensitivity

Concurrent Statements are sensitive to all signals on Concurrent Statements are sensitive to all signals on the input sidethe input side

If a signal appears on both sides, the statement is If a signal appears on both sides, the statement is sensitive to changes in its own output. sensitive to changes in its own output.

A <= A+B; will be evaluated when B changes. This A <= A+B; will be evaluated when B changes. This will change A and the statement will be evaluated will change A and the statement will be evaluated again.again.

Time will not be able to advance because the Time will not be able to advance because the statement keeps executing.statement keeps executing.

Conditional Signal Conditional Signal StatementStatement

Conditional Signal Conditional Signal StatementStatement

Example of Conditional Example of Conditional Signal StatementSignal Statement

Example of Conditional Example of Conditional Signal StatementSignal Statement

Selected Signal Selected Signal StatementStatement

Selected Signal Selected Signal StatementStatement

Example of Selected Signal Example of Selected Signal AssignmentAssignment

Example of Selected Signal Example of Selected Signal AssignmentAssignment

Concurrent Procedure CallConcurrent Procedure CallConcurrent Procedure CallConcurrent Procedure Call IN, OUT and INOUT parameter modesIN, OUT and INOUT parameter modes

Allows return of more than 1 value (unlike function Allows return of more than 1 value (unlike function call)call)

Considered a statementConsidered a statement

Equivalent to a process containing the single Equivalent to a process containing the single procedure call followed by a wait on parameters of procedure call followed by a wait on parameters of mode in or inoutmode in or inout

Example of Concurrent Example of Concurrent Procedure CallProcedure Call

Example of Concurrent Example of Concurrent Procedure CallProcedure Call

Sequential vs. ConcurrentSequential vs. ConcurrentStatement in Simulation CycleStatement in Simulation Cycle

Sequential vs. ConcurrentSequential vs. ConcurrentStatement in Simulation CycleStatement in Simulation Cycle

VHDL is inherently a concurrent languageVHDL is inherently a concurrent language All VHDL processes execute concurrentlyAll VHDL processes execute concurrently Concurrent signal assignment statements are actually Concurrent signal assignment statements are actually

oneline processesoneline processes VHDL statements execute sequentially VHDL statements execute sequentially within a processwithin a process Concurrent processes with sequential execution within a Concurrent processes with sequential execution within a

process offers maximum flexibilityprocess offers maximum flexibility Supports various levels of abstractionSupports various levels of abstraction Supports modeling of concurrent and sequential events Supports modeling of concurrent and sequential events

as observed in real systemsas observed in real systems

BlocksBlocksBlocksBlocks

BlocksBlocksBlocksBlocks Blocks are concurrent statements and provide a mechanism Blocks are concurrent statements and provide a mechanism

to partition an architecture descriptionto partition an architecture description

Items declared in declarative region of block are visible Items declared in declarative region of block are visible only inside the block, e.g. :only inside the block, e.g. : signals, subprogramssignals, subprograms

Blocks may be nested to define a hierarchical partitioning of Blocks may be nested to define a hierarchical partitioning of the architectural descriptionthe architectural description

Blocks may contain Guards for disabling drives.Blocks may contain Guards for disabling drives.

BlocksBlocksBlocksBlocks

Nested BlocksNested BlocksNested BlocksNested Blocks

End of this fileEnd of this file

Modeling StylesModeling Styles Behavioral ModelingBehavioral Modeling

Explicit definition of mathematical relationship between Explicit definition of mathematical relationship between the input and outputthe input and output

No implementation informationNo implementation information Structural ModelingStructural Modeling

Implicit definition of I/O relationship through particular Implicit definition of I/O relationship through particular structurestructure

Interconnection of componentsInterconnection of components

Behavioral ModelingBehavioral Modeling All VHDL processes execute concurrentlyAll VHDL processes execute concurrently Non-proceduralNon-procedural

Data-flowData-flow Concurrent executionConcurrent execution

ProceduralProcedural AlgorithmicAlgorithmic Sequential execution of statementsSequential execution of statements Equivalent to a single concurrent statementEquivalent to a single concurrent statement

Data Flow ModelData Flow Model Concurrent StatementsConcurrent Statements

Execute in arbitrary orderExecute in arbitrary order Execute only when any of input variables changesExecute only when any of input variables changes

Local_Sig_1 Local_Sig_1 <=<= In_1 In_1 ANDAND In_2 ; In_2 ;

Local_Sig_2 Local_Sig_2 <=<= In_1 In_1 OROR Local_Sig_1; Local_Sig_1;

Signal Assignment StatementsSignal Assignment Statements Two TypesTwo Types

Conditional concurrent signal assignment statementConditional concurrent signal assignment statement Selected concurrent signal assignment statementSelected concurrent signal assignment statement

Each of These Has a Sequential Process EquivalentEach of These Has a Sequential Process Equivalent Either Form Can Be Used and Are EquivalentEither Form Can Be Used and Are Equivalent

BIT or BOOLEAN?BIT or BOOLEAN? Logical Types Are Not EqualLogical Types Are Not Equal

BITBIT for signals for signals ‘‘0’ or ‘1’0’ or ‘1’ Character typeCharacter type

BOOLEANBOOLEAN for conditionsfor conditions TRUE or FALSETRUE or FALSE

Conditional Concurrent SyntaxConditional Concurrent Syntax

signal_identifiersignal_identifier <=<= optionsoptions

conditional_waveformsconditional_waveforms ;;

optionsoptions <= <=

[[ guardedguarded ]] [[ delay_mechanismsdelay_mechanisms ]]

conditional_waveformsconditional_waveforms <=<=

{{ waveformwaveform whenwhen conditioncondition elseelse }}

waveformwaveform [[ whenwhen conditioncondition ]]

Waveform SyntaxWaveform SyntaxWaveform SyntaxWaveform Syntax

waveformwaveform <=<=

(( value_expressionvalue_expression [[ afterafter time_expressiontime_expression ]] ))

{ { ,, ... } ... }

Operator PrecedenceOperator Precedence Highest to LowestHighest to Lowest

Unary operator: NOTUnary operator: NOT Relational operators: =, /=, <, <=, >, >=Relational operators: =, /=, <, <=, >, >= Boolean (bitwise): AND, OR, NAND, NOR, XOR, Boolean (bitwise): AND, OR, NAND, NOR, XOR,

XNORXNOR Parentheses Can Be Used toParentheses Can Be Used to

Force particular order of evaluationForce particular order of evaluation Improve readability of expressionsImprove readability of expressions

Type Declaration/DefinitionType Declaration/Definition

typetype identifieridentifier isis type_definitiontype_definition ;;

type_definitiontype_definition <=<=

scalar_type_definitionscalar_type_definition ||

composite_type_definitioncomposite_type_definition ||

access_type_definitionaccess_type_definition ||

file_type_definitionfile_type_definition

Scalar TypeScalar Type

scalar_type_definitionscalar_type_definition <=<=

enumeration_type_definitionenumeration_type_definition ||

integer_type_definitioninteger_type_definition ||

floating_type_definitionfloating_type_definition ||

physical_type_definitionphysical_type_definition

Predefined Enumerated TypesPredefined Enumerated Types typetype severity_level severity_level is ( is ( note, warning, error, note, warning, error, failure failure ));;

type type BooleanBoolean is ( is ( false, true false, true ));; Used to model abstract conditionsUsed to model abstract conditions

type type bitbit is ( is ( '0', '1' '0', '1' ));; Used to model hardware logic levelsUsed to model hardware logic levels

Bit-Vector TypeBit-Vector Type Useful Composite Type Since It Groups Bits Useful Composite Type Since It Groups Bits

Together Which Can Represent Register Contents or Together Which Can Represent Register Contents or Binary Numbers.Binary Numbers.

signalsignal Out_Port_Adx: Out_Port_Adx: Bit_VectorBit_Vector

(( 15 15 downtodownto 0 0 ));;

Specifying Values with String LiteralSpecifying Values with String Literal

Out_Port_Adx Out_Port_Adx <=<= B ”0110_1001”; B ”0110_1001”;

Out_Port_Adx Out_Port_Adx <=<= X ”69” ; X ”69” ;

Out_Port_Adx Out_Port_Adx <=<= O ”151” ; O ”151” ;

HW 2-11HW 2-11LIBRARY LIBRARY ieee ;ieee ;USE USE ieee.std_logic_1164.all ;ieee.std_logic_1164.all ;

PACKAGE PACKAGE Clock_2_11_pkg Clock_2_11_pkg ISIS COMPONENT COMPONENT Clock_2_11Clock_2_11 --GENERIC ( ) --GENERIC ( ) ;; PORT ( PORT ( ClockOut : ClockOut : out bit out bit ::= '= '00' )' );; END COMPONENT END COMPONENT ;;END END Clock_2_11_pkg ;Clock_2_11_pkg ;

HW 2-11HW 2-11

ENTITY ENTITY Clock_2_11 Clock_2_11 ISIS

-- GENERIC ( )-- GENERIC ( );;

PORT ( PORT ( ClockOut : ClockOut : out bit out bit ::= '= '00' )' );;

END END Clock_2_11 ;Clock_2_11 ;

HW 2-11HW 2-11

ARCHITECTURE ARCHITECTURE KJH_Clock KJH_Clock OF OF Clock_2_11 Clock_2_11 ISISBEGINBEGINclock_gen :clock_gen : PROCESS PROCESS BEGINBEGIN ClockOut ClockOut <= '<= '11'';; WAIT FOR 10 ns ;WAIT FOR 10 ns ; Clockout Clockout <= '<= '00'';; WAIT FOR 10 ns ;WAIT FOR 10 ns ; END PROCESS END PROCESS clock_genclock_gen ;;END END KJH_Clock ;KJH_Clock ;

SourcesSourcesSourcesSources

VLSI, Ohio University, Prof. StarzykVLSI, Ohio University, Prof. StarzykProfessor K.J. Hintz.Professor K.J. Hintz.California State University NorthridgeCalifornia State University Northridge

Prof. Krzysztof KuchcinskiProf. Krzysztof Kuchcinski