subhash t.g. joshi crowbar application 1 , vinod john2 thyristor ... · dynamic balancing networks...

IET Power Electronics

Research Article

Thyristor voltage equalising network forcrowbar application

ISSN 1755-4535Received on 3rd January 2018Revised 5th April 2018Accepted on 20th April 2018doi: 10.1049/iet-pel.2017.0932www.ietdl.org

Subhash T.G. Joshi1 , Vinod John2

1Power Electronics Group, Centre for Development of Advanced Computing, Thiruvananthapuram, India2Department of Electrical Engineering, Indian Institute of Science, Bangalore, India

E-mail: [email protected]

Abstract: Many high-voltage applications are realised with series connected thyristors. Voltage imbalance among seriesconnected thyristors during steady state as well as in transients is one of the major concerns. This voltage imbalance ismitigated by using static and dynamic balancing network. Dynamic balancing networks are typically designed based on reverserecovery charge of the thyristor during turn-off, which suits many applications. But this is not the case for a crowbar application,where turn-off of the thyristor is not a major circuit constraint. This study proposes the design method for dynamic balancingnetwork considering gate turn-on delay time and the balancing network component tolerances. The study derives two modelsfor the dynamic balancing network based on its charge–discharge cycle. The importance of charge–discharge cycle in thedesign of dynamic balancing network during high di/dt operation is emphasised. Influence of dynamic balancing resistance andcrowbar current limiting inductance on voltage imbalance, charging current and discharging current is studied using theanalytical model. The proposed design method also offers flexibility to incorporate differences in propagation delays among thethyristor drivers that are used to trigger individual thyristors. Such delays cannot be directly incorporated in the conventionalbalancing network design method based on reverse recovery. Further, it is also analytically shown that designing the dynamicbalancing network based on reverse recovery charge makes the balancing network lossy and bulky for crowbar application.Simulation studies and experimental results on a 12 kV, 1 kA crowbar consisting of six series connected thyristors confirm thetheoretical analysis and validate the proposed approach for crowbar applications.

NomenclatureRs, aR static balancing resistance and its toleranceRd, Cd dynamic balancing resistance and capacitanceac tolerance of dynamic balancing capacitorL di/dt limiting inductor of crowbarN number of thyristors connected in seriesvG thyristor gate to cathode voltageiG thyristor gate currentvAK thyristor anode to cathode voltageiA thyristor anode currentvAK, N Nth thyristor anode to cathode voltageVAK, 1_max maximum voltage across thyristor T1 during

triggering of T2 to TNvCd, L voltage across the first thyristor and LVs operating dc voltage of crowbartdmax, tdmin maximum and minimum turn-on delay timetdTol tdmax − tdmin

ton time taken by vAK to drop from 100% of forwardblocking voltage to 0 V

ich, idis charging and discharging current of dynamicbalancing network

Ich_max, Idis_max maximum charging and discharging current ofdynamic balancing network

1 IntroductionAn increasing number of power electronic systems are being usedin high-voltage applications, such as high power drives, high-voltage un-interruptable power supply, pulse power systems, staticVAR compensator and crowbar switches [1]. Among the varioussemiconductor devices available for design, thyristor is widelyused in various power electronic systems when the operatingvoltages are in the range of kilovolts. Availability of thyristors athigher voltage and current rating makes thyristor a good choice for

such applications. In many high-voltage applications, meeting therequired voltage rating with single thyristor is not feasible. Hence,there is a need for series connection of the thyristor switches [2].

A crowbar is a fault energy-diverting element built withthyristors, connected at the output of high-voltage dc source asshown in Fig. 1a. The dc source feeds power to sensitive loads, likemicrowave or plasma tubes. The triggering of crowbar is initiatedby turning on the thyristors when a fault signal is received fromfault sensing circuits in the load. This can be for conditions ofovervoltage, or short circuit, or any other situations which activatethe protection circuits. When the crowbar receives the triggersignal from a protection circuit, all the series connected thyristorsare turned-on and fault energy, from the storage devices such ascapacitors and the follow-on current from the input power supply,is diverted through crowbar within a few microseconds. Concurrentto this, the trigger signal is also transmitted to open the input circuitbreaker (CB). The crowbar is kept ON until the input CB opens,which can take as long as 100 ms. This along with the triggering ofthe crowbar reduces the dc voltage close to zero [3].

While connecting thyristors in series, sharing of voltage by eachthyristor during steady state as well as in dynamic condition is oneof the major concerns to be addressed [4]. The main cause ofvoltage imbalance in series connected thyristors during steady stateis due to their difference in reverse blocking leakage current. If theV–I characteristics of thyristors connected in series are different,for the same leakage current, the voltage sharing among thyristorswill be unequal as illustrated in Fig. 2a. Passive resistors Rs calledstatic balancing networks are connected across each thyristor asshown in Fig. 1b as a solution for static voltage imbalance. Thevalue of Rs is selected based on the reverse leakage current ofthyristor [5].

When series connected thyristors are turned-off transientvoltage imbalances can occur among them due to mismatch in theirreverse recovery charge [6]. When the thyristor is turned-off, thecharge carriers stored in the device need to be removed completelybefore it recovers its voltage blocking capability [7, 8]. The

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difference in the amount of charge stored in the junction makes theturn-off time to vary from one thyristor to another as illustrated inFig. 2b. Passive resistor–capacitor network (Rd, Cd), shown in Fig.1b, called dynamic balancing network, is used as a solution fortransient voltage imbalance. These are designed based on themismatch in reverse recovery charge of the thyristors [9].

Conventionally, the static and dynamic balancing networks aredesigned by considering two modes of operation of thyristors [10,11]; in mode 1, thyristors are in blocking stage and in mode 2,thyristors are being turned-off. These modes of operation of thethyristors reflect actual operating conditions in most applications.Hence in many literatures the balancing network is designedconsidering turn-off condition also [12–14]. But this is not true incase of crowbar operation, where in mode 1, thyristors are inforward blocking stage and in mode 2, thyristors are being turned-on. This is shown to require new constraints for selection of thestatic and dynamic balancing network components. In [15],switching-on overvoltage across series connected thyristor isdiscussed, but the overvoltage addressed is due to the firingcapacitor connected across gate and cathode. For a three-phasebridge circuit, the turn-on overvoltage during commutation of thecomplementary switch is discussed in [16], but the overvoltage issolved numerically only.

When series connected thyristors are turned-on, voltageimbalance can occur due to difference in gate turn-on delay time.In [17], the design of a dynamic balancing network based on gateturn-on delay time is addressed. The analysis detailed in [17] didnot consider the influence of dynamic balancing resistance and thecrowbar current limiting inductance. In this paper, the analysis isextended by considering the influence of dynamic balancingresistance. The paper derives two models for the dynamicbalancing network based on its charge–discharge cycle. Theimportance of charge–discharge cycle in the design of dynamicbalancing network during high di/dt operation of crowbar is alsoemphasised in the paper. Influence of dynamic balancing resistanceand crowbar current limiting inductance on voltage imbalance,charging current and discharging current is also explored. Theanalysis shows that for high di/dt applications the charging currentof dynamic balancing network can be higher than the dischargingcurrent. Hence by considering only the discharging current as donein the conventional method, the design leads to large deviations inthe results. The paper compares this design with that usingtraditional dynamic balancing component design based on reverserecovery charge. It is also found that the proposed design providesflexibility to include the difference in propagation delays amongthe gate driver circuits used in triggering individual thyristors. Thisallows for a design without complex pulse synchronising circuitused in crowbar applications. Tolerances of components are alsoconsidered in the proposed balancing network design. Theanalytical design results are validated using time-domainsimulations. Experimental results using a laboratory crowbarprototype confirms the theoretical analysis.

2 Thyristor characteristicsTurn-on time of thyristor can be divided into three parts: (i) delaytime, (ii) rise time and (iii) conduction spreading time [18]. Afterinitiating the gate-to-cathode current IG, an appreciable time td isrequired to establish the charge in thyristor to support a currentgreater than its holding current. During rise time, iA rises rapidly ina small area near the vicinity of the gate and a similar decrease involtage occurs between anode and cathode vAK. The area ofconduction spreads during spreading time until the whole cathodestarts conducting. In many applications, evaluating the delays of iArise and vAK fall with respect to gate voltage signal is better suitedthan with respect to gate current signal. Also, while using devicessuch as light triggered thyristor, the gate currents are notaccessible. The datasheet td is defined as the time from start of thetriggering pulse vG to vAK dropping below 90% of the appliedforward off-state voltage [19], as shown in a sample experimentalwaveform given in Fig. 2c. The time during which vAK drops from90 to 20% is referred as turn-on time, whereas during spread time

Fig. 1 Schematic diagram of the crowbar circuit showing(a) High-voltage power supply, crowbar and load connections at dc output, (b) Staticand dynamic voltage equalising network

Fig. 2 Thyristor characteristics showing(a) Mismatch in two thyristor V–I characteristics, (b) Mismatch in two thyristorreverse recovery characteristics, (c) vAK and vG waveforms showing turn-oncharacteristics of thyristor measured in the laboratory

2 IET Power Electron.© The Institution of Engineering and Technology 2018

ts, vAK drops from 20% to forward on voltage. However for theanalysis the variation of vAK is assumed to be linear as shown bydotted line in Fig. 2c. Such an approximation shows a worst casevAK, since the approximated vAK is delayed more than the actualcurve. In the approximated vAK, turn-on time ton is redefined as thetime taken by vAK to drop from 100% of forward blocking voltageto 0 V. Thyristors having smaller td will turn-on earlier than the onehaving higher td. This leads to voltage imbalance among seriesconnected thyristors. Hence, dynamic balancing network consistingof Rd and Cd should be designed based on the gate turn-on delaytime mismatch of the thyristors used. From the datasheet ofthyristors [20], it is found that forward leakage current as well asreverse leakage current are similar. Hence, the method used todesign the static balancing network Rs remains similar to theconventional method. However in the proposed method, the worstcase balancing network component tolerances are also consideredin the design procedure.

3 Proposed design of static and dynamicbalancing networkInductor L connected in series with the thyristor shown in Fig. 1bensures that the slope of the current does not cause any damage tothe thyristor. The upper limit of the value of this inductor is basedon the amount of fault energy that can be tolerated by the load ofthe crowbar shown in Fig. 1a. The lower limit of the value of theinductor is based on the di/dt rating of the thyristor.

3.1 Charging cycle of dynamic balancing network

Let N thyristors connected in series be fed from a dc source, Vs,through a di/dt limiting inductor, L, as shown in Fig. 1b. For thedynamic balancing network analysis the following assumptions aremade:

1. For worst case analysis the thyristor T1 is chosen to havemaximum gate turn-on delay time tdmax and remaining (N − 1)thyristors have minimum turn-on delay time tdmin. Thedifference between the maximum and minimum thyristor turn-on delay time is defined as

tdTol = tdmax − tdmin (1)

2. During the turn-on process of thyristor, anode-to-cathode

voltage varies linearly and the curve is identical for allthyristors except it is delayed by its own gate turn-on delaytime.

3. Influence of the static balancing network Rs on dynamicbalancing network is assumed to be minimal due to its relativehigh impedance.

4. For the worst case analysis the capacitor connected across thefirst thyristor is chosen to have the lowest tolerance limit acwhere ac is defined as Cd ∈ {Cd, nominal(1 ± ac)}.

The voltage appearing across each thyristor during forwardblocking state is Vs/N. ton is the time taken by vAK to reach zerofrom its forward blocking voltage, Vs/N. Then the expression forthe variation of voltage across (N − 1) thyristors at time t, in thetime duration tdmin ≤ t ≤ (ton + tdmin) is given by

vAK, 2(t) = vAK, 3(t) = ⋯ = vAK, N(t) =

− VsNton

(t − (ton + tdmin))(2)

Total voltage appearing across (N − 1) thyristor is

v AK, 2 to N (t) = − (N − 1)VsNton

(t − (ton + tdmin)) (3)

Since the voltage transition across the first device T1 is not yetinitiated, the dynamic balancing network connected across T1 willbe in charging cycle. During this cycle the voltage appearing acrossL and T1, which includes the balancing network, is shown by asimplified equivalent circuit in Fig. 3a and is given by

vCd, L(t) = Vs − V AK, 2 to N (t)

vCd, L(t) = VsN + Vs(N − 1)(t − tdmin)

Nton

(4)

Based on the relative value of ton and tdTol during this cycle, thevCd, L(t) takes following values:

1. If tdTol ≤ ton

vCd, L(t) = VsN + Vs(N − 1)(t − tdmin)

Nton(5)

2. If tdTol > ton, the (N − 1) thyristors turn-on transitions will becompleted at t = (tdmin + ton). Hence

vCd, L(t) =

VsN + Vs(N − 1)(t − tdmin)

Nton, if t ≤ (tdmin + ton)

Vs, if t > (tdmin + ton)

(6)

Hence, the charging cycle of dynamic balancing network includestwo dynamic models based on relative value of ton and tdTol, whichare considered below.

3.1.1 Dynamic model for tdTol ≤ ton: The simplified equivalentcircuit is shown in Fig. 3a where vCd, L(t) is given by (5). If ich(t) isthe charging current of dynamic balancing network, the dynamicequation related to this circuit is given by

Ld2ichdt2 + Rd

dichdt + ich

(1 − ac)Cd= Vs(N − 1)

Nton(7)

The minimum value of tolerance is chosen for Cd across thyristorT1 in (7), as this gives the worst case overvoltage for T1. In mostcrowbar balancing circuits, Rd is much smaller than thecharacteristic impedance that leads to complex solutions to (7). Att = tdmin, choosing the initial conditions as ich(t) = 0 and voltage

Fig. 3 Simplified equivalent circuit of the thyristors and the balancingnetwork when(a) Thyristor T1 is off and other (N − 1) thyristors are triggered on initially, (b)Thyristor T1 is turned on subsequently


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across the inductor is zero, the above dynamic equation can besolved as

ich(t) = Vs(N − 1)(1 − ac)CdNton

× 1 − e−δ(t − tdmin)

ωd L(1 − ac)Cdcos ωd t − tdmin − ϕ

(8)

where δ = Rd/2L, ωd = (1/(L(1 − ac)Cd)) − (Rd/2L)2 andϕ = tan−1(δ/ωd).

Therefore, the voltage appearing across the first device is givenby

vAK, 1(t) = VsN + Vs(N − 1)

Nton(t − tdmin)

− e−δ(t − tdmin)

ωdsin ωd t − tdmin

(9)

The second term in (9) represents the transient term initiated aftertriggering (N − 1) thyristors. Since the first thyristor T1 getstriggered at t = tdmax, the maximum values of ich(t) and VAK, 1(t) areobtained by choosing t = tdmax in (8) and (9), respectively, given by

Ich_max = Vs(N − 1)(1 − ac)CdNton

× 1 − e−δtdTol

ωd L(1 − ac)Cdcos ωdtdTol − ϕ

(10)

VAK, 1_max = VsN + Vs(N − 1)

Nton

× tdTol − e−δtdTol

ωdsin ωdtdTol

(11)

3.1.2 Dynamic model for tdTol > ton: Let t1 be defined aston + tdmin . For t ≤ t1, vCd, L(t) holds the first condition of (6) and

the solutions are given in (8) and (9). For t > t1, vCd, L(t) is given bythe second condition of (6) and the dynamic equation can beexpressed as

Ld2ichdt2 + Rd

dichdt + ich

(1 − ac)Cd= 0 (12)

This can be solved by applying initial conditions (i) ich(t) at t = t1

from (8) denoted as Ich(t1) and (ii) voltage across Cd at t1 denoted byVc(t1) obtained as VAK, 1(t1) − Ich(t1)Rd . VAK, 1(t1) is given by VAK, 1(t) att = t1 obtained from (9). The solution of (12) is

ich(t) = e−δ(t − t1) K1cos ωd t − t1 + K2sin ωd t − t1 (13)

where K1 = Ich(t1) and K2 = (Vs − Vc(t1) − Ich(t1)Lδ)/Lωd.Therefore, the voltage appearing across the first device is given

by

VAK, 1(t) = Vs + L e−δ(t − t1) (K1ωd + K2δ)sin ωd t − t1

+(K1δ − K2ωd)cos ωd t − t1(14)

The maximum value of ich(t) and VAK, 1(t) during this mode ofoperation can be obtained by choosing t = tdmax in (13) and (14),respectively.

3.2 Discharging cycle of dynamic balancing network

When thyristor T1 is turned on at t = tdmax, Cd discharges into thethyristor shown by a simplified equivalent circuit given in Fig. 3b.The slope of vAK of first thyristor is assumed to be same as that of

(N − 1) thyristors. Then the dynamic equation related to Fig. 3b isgiven by

Rddidisdt + idis

(1 − ac)Cd= − Vs

Nton(15)

Depending on the type of model used in (5) and (6), the initialconditions are chosen. The initial condition for idis(t), denoted byIdis(tdmax), is obtained either from (8) for tdTol ≤ ton or from (13) fortdTol > ton by choosing t = tdmax. Using this initial condition thesolution to the dynamic equation (15) is given by

idis(t) = Idis(tdmax) + Vs(1 − ac)CdNton

e−((t − tdmax))/(Rd(1 − ac)Cd)

− Vs(1 − ac)CdNton

(16)

As time t increases idis(t) magnitude increases. Hence, themaximum value of idis(t) can be obtained when thyristor T1 iscompletely turned on. Starting from forward surge voltage, due toturn-on of (N − 1) thyristor, the time taken by the first thyristor toreach its forward conduction voltage is

ton, 1 = VAK, 1_maxNtonVs

+ tdmax (17)

where VAK, 1_max is obtained either from (9) for tdTol ≤ ton or from(14) for tdTol > ton by choosing t = tdmax. The maximum value ofidis(t) can be obtained by choosing t = ton, 1 in (16) and is given by

Idis_max = Idis(tdmax) + Vs(1 − ac)CdNton

e−((ton, 1 − tdmax))/(Rd(1 − ac)Cd)

− Vs(1 − ac)CdNton

(18)

3.3 Static balancing resistance (Rs)

Design of static balancing network is well established in literature[5, 10]. However, even in this case it is important to consider thetolerance of the resistor Rs used in the balancing network. Thestatic balancing resistance across each thyristor is given by

Rs = Vd1 N(1 − aR) + 2aR − (1 + aR)Vs(N − 1)(1 − aR

2 )(IDmax − IDmin)(19)

where Vd1 is the maximum allowable steady-state forward blockingvoltage across thyristor, IDmax and IDmin are the maximum andminimum values of forward leakage current and aR is tolerancelimit of selected resistor such that Rs ∈ {Rs, nominal(1 ± aR)}.

4 Analysis of charge–discharge cycle of dynamicbalancing networkSince many practical thyristor characteristics have tdTol ≤ ton, thissection analyses this case in detail. For the analysis consider acrowbar of 12 kV rating built with six thyristor devices in seriesand a di/dt limiting inductor of 250 μH. The percentageovervoltage appearing across the thyristor T1 is defined as

Vd_ov = Vd1_max − (Vs/N)(Vs/N) 100 (20)

For various values of Cd, the Vd_ov, Ich_max and Idis_max are computedfrom (20), (10) and (18), respectively, where Vd1_max is evaluatedusing (11). The computation is carried out by choosing ton = 5 μsand keeping tdTol of thyristor and Rd as parameters. The curve Vd_ovversus Cd is plotted in Fig. 4a for three different tdTol such as 3, 2and 1 μs and Rd of 0, 15 and 30 Ω. Fig. 4a shows that in all cases,


beyond certain value of Cd there is no significant reduction inVd_ov. Also from Figs. 4b and c higher value of Cd leads to highercharge Ich_max and discharge Idis_max current. But the influence of Cdon discharge current is found to be significant compared to itsinfluence on charging current. Hence, by choosing the minimumrequired value of Cd that is sufficient to meet the required Vd_ov,the discharge current can be limited to the minimum value. Fig. 4aalso shows an increase in Vd_ov with resistance Rd whereas chargeand discharge currents reduce with Rd for a given Cd. Hence, byselecting a minimum value of Rd, the Vd_ov can be further reducedprovided the charge and discharge currents are within the rating of

Cd as well as thyristor. For a given Cd, Vd_ov also depends on tdTolas shown in Fig. 4a. For higher tdTol, the Vd_ov is higher. Similarcharacteristics are observed for charging and discharging current,which are shown in Figs. 4b and c, respectively. However, theinfluence of tdTol on discharge current are found to be minimal forsmaller values of Rd. Figs. 5a–c show the influence of ton on Vd_ov,Ich_max and Idis_max for Rd = 5 Ω. These curves are plotted for threedifferent tdTol such as 3, 2 and 1 μs and ton of 5, 7.5 and 10 μs. TheVd_ov, Ich_max and Idis_max are highly influenced by ton and increaseswhen ton reduces for a given Cd. The rate of increase in Vd_ov,Ich_max and Idis_max for different ton is more when the ratio betweenton and tdTol is less.

Iratio = Ich_max/Idis_max for different Cd and Rd = 5 Ω is shown inFig. 5d. The curves are plotted for three different tdTol such as 3, 2and 1 μs and ton of 5, 7.5 and 10 μs. From Fig. 5d it can beobserved that Iratio is approximately independent of ton. Also forlower Cd from Fig. 5d the charging current is higher than thedischarging current. Hence, for the design of dynamic balancingnetwork Cd, it is necessary to compute both charging ordischarging current.

The influence of L on Vd_ov, Ich_max and Idis_max are shown inFigs. 6a and b, respectively. For a given Cd as L increases Vd_ovand Ich_max reduces whereas Idis_max is independent of 5 μs. Hence,for high di/dt applications charging current can be higher than thedischarging current. This shows the importance of dynamicbalancing network when operating the crowbar at high di/dt andimportance of considering both currents for its design.

4.1 Selection of dynamic balancing network (Rd, Cd)

From the analysis for a given set of conditions, Vd_ov showsminimum value for Rd = 0. Hence, to start, Cd is computed for themaximum allowable transient voltage Vd1_max from (11) keepingRd = 0. From the computed Cd the Ich_max and Idis_max are calculatedfor Rd = 0 from (10) and (18), respectively. If these currents arewithin the acceptable limit then dynamic balancing network willhave only Cd of the computed value. If either Ich_max or Idis_max ishigher than the specified value then from Figs. 4b and c the choiceis to either increase Rd or reduce Cd by compromising on therequired Vd_ov. If significant increase of Rd is required to bringIch_max and Idis_max within limit, then reducing Cd will be preferableapproach. The other parameters Vs, N and L required for thecomputation are known from the crowbar circuit and tdmax, tdmin andton can be obtained from the selected thyristor datasheet.

5 Simulation resultsFrom the system specification, the dc voltage rating of crowbar is12 kV. By connecting six thyristors having part number 5STP03X6500 (ABB) in series, the above voltage rating can beachieved. In nominal operating condition, each thyristor will see avoltage of 2 kV. Other important crowbar design parameters for thethyristor obtained from datasheet are given in Table 1.

5.1 Estimation of dynamic balancing capacitor (Cd)

Choose the maximum allowable overvoltage across the thyristor as50% (1 kV) for a maximum value of ton equal to 5 μs and tdTol of3 μs. Then from Fig. 4a for Rd = 0, the minimum value of Cdrequired to limit Vd_ov with 50% is 40 nF. Also from Fig. 4a withCd of 40 nF, Vd_ov will be < 50% if ton is higher than 5 μs and tdTol< 3 μs. Since the Cd experience 3 kV the voltage rating of Cd ischosen as 4 kV.

5.2 Estimation of dynamic balancing resistor (Rd)

Ich_max and Idis_max for ton = 5 μs, tdTol = 3 μs and Rd = 0 arerecorded from Figs. 4b and c, respectively. From Fig. 4b, the Ich_max

for Cd = 40 nF is 33 A whereas from Fig. 4c the discharging

Fig. 4 Variation in the thyristor peak stress with Cd for different tdTol andRd, with ton = 5μs(a) Percentage of overvoltage Vd_ov, (b) Maximum charging current Ich_max, (c)Maximum discharging current Idis_max


5

current is 15 A. Since these current are small compared to thecurrent rating of thyristor, given in Table 1, Cd, can be directlyconnected without any current limiting resistor. However, a smalldamping resistance of 3 Ω is chosen for Rd. This is sufficientconsidering a parasitic loop inductance of the (Rd, Cd) balancingnetwork and thyristor is of the order of 100 nH.

5.3 Estimation of static balancing resistor (Rs)

Based on the parameter given in Table 1 and limiting the maximumsteady-state voltage across any of the thyristor Vd1 to 135%(2.7 kV), the Rs can be estimated from (19) as 2.5 MΩ.

Simulations are carried out with estimated values of static anddynamic balancing network elements. In simulation, ton and tdTolare chosen as 5 and 3 μs, respectively. The voltage waveformacross each thyristor during turn-on is shown in Fig. 7a. Thecharging and discharging current of Cd are shown by positive andnegative polarity, respectively, in Fig. 7b. Simulation results show

that the maximum dynamic voltage reaches 3 kV and matches thetarget design of Vd_ov of 50% in the analytical design. Also fromsimulation, Ich_max and Idis_max through Cd is found to be 33 and 15 A, respectively, that also matches with the analytical designperformance from Section 5.2.

6 Comparison of the proposed and conventionalmethods for the dynamic balancing networkdesignConventionally, the Cd is designed based on the reverse recoverycharge [5]. Value of Cd based on reverse recovery charge is

Cd = 1 + (N − 1)((1 − ac)/(1 + ac)) (Qmax − Qmin)(1 − ac) Vd1 1 + (N − 1)((1 − ac)/(1 + ac)) − Vs

(21)

Fig. 5 Variation in the following parameters with Cd for different tdTol and ton keeping Rd = 5 Ω(a) Percentage of overvoltage Vd_ov, (b) Maximum charging current Ich_max, (c) Maximum discharging current Idis_max, (d) Ratio of Ich_max and Idis_max

Fig. 6 Variation in the circuit performance factors with Cd, for different tdTol and L, keeping Rd = 5 Ω and ton = 5μs(a) Percentage of overvoltage Vd_ov, (b) Ich_max (positive polarity) and Idis_max (negative polarity)


Using data given in Table 1 and limiting the same maximumallowable overvoltage across thyristor to 50%, the value of Cdbased on reverse recovery charge is computed as 2.25 μF.

From (10) and (18), Ich_max and Idis_max for the above Cd withtdTol = 3 μs and ton = 5 μs is 36 and 810 A, respectively.Comparison with the values obtained from the proposed design ofdynamic balancing network, the Ich_max is comparable whereas theIdis_max is significantly large, closer to the rating of thyristor givenin Table 1. To reduce the discharging current Rd of large value ofresistance and wattage is required.

Comparing the value of Cd designed with the proposed methodwhich is based on turn-on delay time, and the one designed withthe conventional method which is based on reverse recoverycharge, it is found that Cd designed with conventional method is 56times larger than that of Cd obtained with the proposed method. By

Fig. 4a such a large value of Cd will not give any additionalreduction of Vd_ov, instead it significantly increases the dischargingcurrent. To find the loss component, the energy consumed by theconventionally designed dynamic balancing network is representedas a fraction of the energy consumed by the same network designedbased on the proposed method. In the conventional method, the Rdis chosen such that the Idis_max is equal to the value obtained fromthe proposed method. This simplifies the ratio of consumed energyis equal to the ratio of Rd used in the conventional and in theproposed method. Let Rd, 1 be the initial dynamic balancing resistorfor which Idis_max is equal to 810 and 15 A for the conventional andproposed method, respectively. Let Rd, 2 be the additional resistancerequired in the conventional method to bring the Idis_max from 810 to15 A. Since Rd, 1 ≈ 0, then the ratio of Rd, 2 to Rd, 1 is equal to theratio of Idis_max, which is equal to 54. Hence, the ratio of energyconsumed is also equal to 54. The large value of dischargingcurrent and large value of capacitance that result from theconventional method makes the dynamic balancing network lossy,bulky as well as costly. The proposed method allows one to choosethe value of Cd without over-sizing. Comparison between theconventional and proposed design approach for the design ofdynamic balancing network is summarised in Table 2.

7 Experimental validation7.1 Validation methodology

The VAK, 1_max, Ich_max and Idis_max given by (11), (10) and (18),respectively, depend on (i) tdTol, in addition to the parameters, (ii)N, ton, ac, L, Rd, Cd and Vs. To validate (10), (11) and (18), anexperiment is conducted for a given value for tdTol and for a givenvalue for parameters described above in (ii). During the productionof the same rated crowbar, a wider variation is expected in thevalue of tdTol. This is due to the wider range of turn-on delay timespecified in the datasheet of the thyristor. Practically, the variationin the values of parameters described in (ii) is minimum as this canbe easily matched. The minimum and maximum turn-on delayobserved in many thyristors are 0 and 3000 ns, respectively [20].Hence, the experiment is conducted by choosing tdTol close to thesetwo extreme values, keeping the parameters mentioned above in(ii) the same. Experimental validation of (10), (11) and (18) showsthe correctness of various results deduced from these equations inSection 4.

7.2 Experimental results

Static and dynamic balancing networks are fabricated for a crowbarof 12 kV, 1 kA rating. The dynamic balancing components Cd andRd chosen for the experiment are 47 nF and 3 Ω, respectively. Thevalue of static balancing resistance Rs used is 2.2 MΩ. Both staticand dynamic balancing networks required for one thyristor areassembled on a single four-layer PCB, where interconnectingtracks are only routed through inner layers. The top and bottomlayers provide isolation to the inner tracks from external media.The assembled static and dynamic balancing network is shown inFig. 8a. These balancing network PCBs are mounted on crowbarunit as shown in Fig. 8b. The performance of balancing circuit isevaluated in lower voltage by choosing six numbers of thyristors T1to T6 having similar tdTol. A known delay is introduced to the gatesignal of first thyristor T1 and the voltages across all six thyristorsare recorded with and without the voltage balancing network. Theexperiment is carried out with a dc voltage of 480 V and tdTol of800 and 2400 ns. The tdTol of 800 ns emulate the difference inpropagation delay among gate signals of thyristors and 2400 ns istypically the maximum difference in turn-on delay time amongthyristors. The ton observed for the thyristors used for theexperiment is 3 μs. The other parameters are as given in Table 1.The voltage waveforms across the thyristors during turn-on withoutbalancing network for tdTol = 800 ns are shown in Figs. 9a and bwhere Fig. 9a is for T1 and T2 and Fig. 9b is for T3 to T6. Anappreciable overvoltage of 3.75 times its steady-state voltage is

Table 1 Parameters of the crowbar and thyristorsParameters Valuesdc source voltage, Vs 12 kVseries inductance to crowbar, L 250 μHrated dc voltage of thyristor, VD(dc) 3.3 kVnumber of thyristor in series, N 6max. forward leakage current, IDmax 350 μAmin. forward leakage current, IDmin 100 μAmax. turn-on delay time, tdmax 3 μsmin. turn-on delay time, tdmin 0 μsRMS on state current, IT(rms) 550 Apeak non-repetitive surge current, ITSM 4500 Aminimum recovery charge, Qmin 1000 μCmaximum recovery charge, Qmax 2300 μCtolerance limit of capacitor, ac 0.1tolerance limit of resistor, aR 0.05

Fig. 7 Simulation results of the dynamic voltage balancing networkshowing(a) Voltage across all six thyristors, considering worst case delay and parametertolerance for the first thyristor, (b) Charging ich(t) and discharging idis(t) current of thefirst thyristor

Table 2 Comparison of the proposed and conventionalmethodsParameters, units Conventional method Proposed methodVd_ov, % 50 50Cd, nF 2250 40Ich_max, A 36 33Idis_max, A 810 15energy consumed, p.u. 54 1


7

observed across the delayed thyristor T1 even for small value oftdTol. The effectiveness of balancing network is shown in Figs. 9cand d where Fig. 9c is for T1 and T2 and Fig. 9d is for T3, T4, T5 andT6. The overvoltage across T1 with balancing network is found tobe insignificant as shown in Fig. 9c. The overvoltage computedanalytically with (11) is 82 V which is 2% above its steady-statevalue that is close to the experimental result shown in Fig. 9c. Thecharging and discharging current of dynamic balancing networkshown in Fig. 10 were measured to be 0.2 and −1.2 A, respectively.The respective computed values from (10) and (18) are 0.18 and−1.14 A, closely matching with the experimental results.

The experiment is repeated with tdTol = 2400 ns that is close tothe maximum value mentioned in the thyristor datasheet [20]. Thevoltage waveforms across T1 and T2 during turn-on withoutbalancing network are shown in Fig. 11a where as that of T3 to T6are not shown since they are triggered simultaneously. Theovervoltage across T1 is found to be 676 V that is 8.45 times that ofthe steady-state value of 80 V. The voltage waveforms across T1

and T2 with balancing network are shown in Fig. 11b where theovervoltage across T1 is measured to be 112 V that is 1.4 times ofits steady-state value. The computed overvoltage from (11) isfound to be 112.6 V which is close to the experimental result andpercentage of overvoltage is close to the simulation results shownin Fig. 7a. The crowbar is operated by discharging the nominalforward blocking voltage of 10 kV to allow nominal current of1 kA. The applied forward voltage and crowbar current are shownin Fig. 12. The performance of balancing network and crowbar arefound to be satisfactory and the proposed design procedure for thebalancing network is validated with analytical, simulation andexperimental results.

8 ConclusionVoltage balancing networks are often designed by considering twomodes of operation of thyristors which are reverse blocking modeand turn-off mode. Since in a crowbar application, the modes ofoperation of thyristor are different, the conventional method used

Fig. 8 Photographs showing(a) Static and dynamic balancing network where the component (1) is Cd (2) is Rd and (3) is Rs, (b) Fabricated 12 kV, 1 kA solid-state crowbar

Fig. 9 Measured thyristors waveforms when VG of thyristor T1 is delayed by 800ns (tdTol)(a) VG and VAK for T1 and T2 with respective gate signals without balancing network, (b)VAK for T3 to T6 without balancing network, (c) VG and VAK for T1 and T2 with respectivegate signals with balancing network, (d)VAK for T3 to T6 with balancing network


for the design of balancing network if adopted, leads to very bulkybalancing components with higher power loss. This paper proposesa design method for dynamic balancing network based on gateturn-on delay time. The paper derives two models for the dynamicbalancing network and shows its importance in the design ofdynamic balancing network when crowbar operate at high di/dt.The proposed approach for designing that balancing networkresults in a small value of capacitance as well as a small value ofdischarging current which makes the dynamic balancing networkmore efficient and compact. The influence of dynamic balancingresistance and crowbar current limiting inductance on voltageimbalance, charging current and discharging current is explained.This method also allows one to operate a series connected string ofthyristors without any complex pulse synchronising circuit that isnormally found in crowbar applications. The analysis done for thebalancing network includes component tolerance to capture theworst case circuit operating conditions. For the experimental

validation two practically encountered delays, the difference inpropagation delay among gate signals of thyristors and differencein turn-on delay among thyristors, are considered. Experimentalresults on a 12 kV, 1 kA crowbar show excellent results andconfirm the theoretical analysis and the proposed design procedure.

9 AcknowledgmentsThe work is supported by Ministry of Electronics and InformationTechnology, Govt. of India, through NaMPET programme [grantnumber 25(1)/2011-IEAD-Vol-II dated 17.2.2012] and Departmentof Atomic Energy (DAE), Government of India through Institutefor Plasma Research, Gandhinagar, India [PO.4100000466 dated11.2.2013]. The authors thank Mr Rajiv I. at C-DAC,Thiruvananthapuram for support with the experimentalmeasurements.

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Fig. 10 Charging (negative polarity) and discharging (positive polarity) current from dynamic balancing network connected to T1 along with its gate signaland voltage waveform across T1 and T2. Thyristor T1 is triggered with a delay tdTol = 800ns

Fig. 11 Measured thyristors waveforms when VG of thyristor T1 is delayed by 2400 ns (tdTol)(a) VG and VAK for T1 and T2 with respective gate signals without balancing network, (b)VG and VAK for T1 and T2 with respective gate signals with balancing network

Fig. 12 Operation of the crowbar at Vs = 10 kV nominal voltage and at1 kApeak crowbar current


9

http://www.eng.uwi.tt/depts/elec/staff/rdefour/ee33d/index.html

http://www.eng.uwi.tt/depts/elec/staff/rdefour/ee33d/index.html

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