Sub-20nm Hybrid Lithography using Optical + Pitch-Division and e-Beam

J. Belledent1, M. Smayling2, J. Pradelles1, P. Pimenta-Barros1, S. Barnola1, L. Mage1, B. Icard1, C. Lapeyre1, S. Soulan1, L. Pain1 1: CEA – LETI, MINATEC, 17 rue des martyrs, F-38054 GRENOBLE Cedex 9, France 2: Tela Innovations, Inc.485 Alberto Way, Suite 115, Los Gatos, CA 95032

ABSTRACT

A roadmap extending far beyond the current 22nm CMOS node has been presented several times. [1] This roadmap includes the use of a highly regular layout style which can be decomposed into “lines and cuts.”[2] The “lines” can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The “cuts” can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write e-beam.[4] The choice for “cuts” will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure. Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography. With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the “lines and cuts” approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography. For practical reasons, E-Beam lithography is used as well to expose the “mandrel” patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4. The Metal-1 “cut” pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the “cut” patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin. The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.

Keywords: Multiple electron beams, data preparation, 1D gridded design, Self-Aligned Double Patterning

1. INTRODUCTION

Photolithography has aroused strong attention for several years already. It is mainly due to the fact that, since the introduction of the high-NA 193nm immersion scanners, there was no longer an easy path to scale numerical aperture

and exposure wavelength in order to enhance the resolution. This implies that, for advance nodes, several exposures are now required to expose one single critical layer. This simple fact induces obviously huge impact in the economics, the logistics in the fabrics and, not the least, it changes the way the circuits have to be designed. Indeed, they have now to be double patterning compliant and this, in itself, is a notion difficult to specify and to encode in design and verification tools. Fortunately, this process can be very much simplified by adopting a 1D gridded design style. Addressing the metal 1 specific case, known as one of the most resolution demanding, we will demonstrate in this paper that such layouts can be already patterned using today’s tools, up to the 11nm node.

1.1 Gridded design

A gridded design, in our sense, is composed of an array of lines drawn at a single pitch and orientation that are cut with rectangular shapes placed on a grid. The width of the latter polygons is fixed and the height values are equal to a multiple of the line pitch. Figure 1 shows the basic principle that drives 1D gridded design style.

Figure 1: Basic principle of a 1D gridded design. The layout can be decomposed into a line pattern and a cut pattern.

They are many reasons for a process engineer to love gridded design rules. It is possible to make a non-exhaustive list in saying that the process development effort is drastically reduced (e.g. very simple OPC, choice of illumination settings is straight forward…), the CD control is improved (e.g. no etch micro-loading effects, iso-focal illumination…) and it saves cost (e.g. computer power for the OPC, metrology…). But it happens also that they are also beneficial to designers as well. Indeed, they do not have to deal with complex Design Rule Manuals anymore, the resulting layouts are by construction double patterning compliant and they can rely on a better process control which translates into lower risk, better accuracy and reduced work.

From a design point of view, the cut mask defines the circuit functions. For example, only this layer will be updated in case of a design re-spin. From a process point of view, it is the most resolution demanding of the two exposures as techniques already exist to pattern the lines using today’s 193nm immersion scanners (e.g. Self-Align Double Patterning [9], Directed Self Assembly [10]…). These are already two reasons to preferably expose this layer using an Electron Beam Direct Write tool (EBDW) as it can save the cost of one additional mask in the first case and very high resolution can be achieved. Therefore, it has been our equipment of choice for our experience and, according to the authors, it should be considered seriously for production.

Table 1 shows the trend of pitches and cut sizes required to meet the density specifications for several logic nodes. The values reported here are estimates based on scaling trends. In our experiment, we chose to address the metal-1 layer for the 14nm and the 11nm nodes. Therefore, the targeted pitch values for the lines are 44nm and 36nm respectively. The dots have to be patterned on a grid at the gate pitch in the x direction and at the metal-1 pitch in the y direction. Their smallest allowed sizes are given in the bottom row of the table (e.g. 23nm wide, 36nm long for the 11nm node).

Table 1: Design trend versus technology nodes. The values reported in this table are estimates based on published information. In our experiment, the gate lines are vertical and therefore use the x-pitch. Metal-1 lines are placed perpendicular to the gates at the y-pitch.

1.2 Patterning of the lines – Self-Aligned Double, Triple and Quadruple Patterning

Several techniques can be used to make the lines starting from a 193nm exposure. Certainly the most mature one is the so called Self-Aligned Patterning or Sidewall Image Transfer (ref) that makes usage of spacers to divide the lithography pitch. Figure 2 gives a schematic view on how the density of the exposed lines could be increased by a factor of 2 (Self-Align Double Patterning), 3 (Self-Align Triple Patterning) or even 4 (Self-Align Quadruple Patterning).

Figure 2: Various techniques that can be used to divide the exposed pitch by 2 (SADP), 3 (SATP) or even 4 (SAQP). SATP and SAQP require two steps of spacer deposition.

Besides obvious cost differences, these three integration schemes impact differently the CD control and the overlay margins. As many process steps are involved, it is difficult to anticipate what exactly the workable design space is, given one set of tools. In an attempt to clarify this, we had been through the process of conducting a Monte Carlo study on the assumption given in Table 2. All process parameters in Table 2.a are supposed to be normally distributed. The exposure is simulated assuming a polarized dipole illumination optimized for the pitch being considered, meaning that defocus has little impact on the result. The resist effects are approximated using a diffused aerial image model with a diffusion length of 5nm 1σ. The true mask stack was simulated using an FDTD algorithm so topography effects are taken into account.

Figure 3 shows the expected CD variations for a set of chosen conditions. In an attempt to help the interpretation of the results, the values were normalized to the targeted CD values. In case (a), most of the data points fall inside the commonly accepted +/-10% CD variation range, meaning that metal 1 lines at the 14nm node can be patterned using a 193nm exposure + SADP. The 40nm pitch case (b) becomes marginal and pitch should be divided further more to meet the CD specifications for denser lines arrays (c to h). As far as CD control is concerned, the 11nm node (36nm pitch) can advantageously be patterned using an SATP integration flow. However, one should mind that, in this latter case, the CD distribution can no longer be assumed to be normal, two populations of spaces being combined together. This matter of fact makes difficult to decide to what extent SATP can be used – 27nm pitch (g) might be the absolute limit. Finally, if

SAQP would be adopted, designs would have to deal with higher CD variations than the standard +/-10% range, (e) exceeding this limit already.

3σσσσ values

Focus error 50nm Dose error 2.5% Mask CD error 1nm (1X) Mask registration error 1.8nm (1X) Etch CD error 2.4nm Spacer etch back 1.2nm Scanner OVL 1nm

• Polarized dipole illumination

• Opening angle 30°

• σcentre optimised for the pitch being simulated

• σout– σin = 0.3

• Mask stack: OMOG � FDTD

• Diffused Aerial Image (5nm 1σ)

a. Process inputs b. Illumination settings

Table 2: Conditions used in the simulation. Table (a) gives the variation spread of all process parameters used in the Monte Carlo analysis. Inset (b) specify the illumination settings used in the simulation.

Figure 3: Final CD spread for various pitch values. Each box height gives the range within which lies 50 % of the CD values at a given final pitch (x axis in nm). The whiskers give the 99.3% interval confidence if the population would be normally distributed. Black crosses are the data points that fall outside this latter interval. Several process types were used for this study: SADP (white background) SATP (light grey) and SAQP (dark grey). All CD values are normalized to the spacer width which is also the targeted final CD value.

Figure 4 gives the spread of enclosure. To be more accurate, the values reported here are the calculated distances from the location of the simulated spacer inner edge to the drawn position of the dot tip. Similarly to Figure 3, values are normalized to the spacer width so it is possible to visualize directly what the workable design space is. The safe region lies between 0.2 and 0.8 to account for dots length variations and corner rounding. Given this recommendation, one can see that our test cases (a and f) are on the safe side. Additionally, comparing the results obtained with SATP and SAQP (e and f), better CD control does not translate automatically into narrower enclosure spread, meaning that the overlay margin is dominated by the scanner position accuracy and the registration errors on the mask.

Figure 4: Dot to spacer enclosure spread for various pitch values. Significance of background colors, boxes height and whiskers lengths are the same as in Figure 3.

2. EXPERIMENT DESCRIPTION

2.1 Our integration flow

For operational reason, we chose to expose the lines with an electron shaped-beam tool to prevent us from going through the hurdle of ordering a test mask. However we had been careful at taking a wafer stack that would be compatible with an optical exposure. For instance, the reflection was minimised for a wide range of incident angles.

The exposed lines in resist were transferred into a sacrificial layer that was used as mandrel to a standard SADP process (Figure 5). Therefore, the situation before the second exposure is similar to the one that we would obtain after a 193nm exposure plus a SAQP integration flow. At this stage starts our recommended solution for patterning 1D gridded designs. And here, one can already notice that electron lithography have a great advantage over other techniques as it is not sensitive to wafer topography. Basically, it means that the wafer stack can be very much simplified and the resist can be directly coated inside the gap delimited by the spacers, provided there is no filling issue.

Figure 5: Integration flow used in our experiment. The lines were exposed using an electron beam tool for

operational reasons and it is not the recommended solution for production. However the wafer stack is compatible with an optical exposure.

2.2 Choice of resist

Referring to Table 1, pitches, as small as 46nm, have to be resolved in order to pattern the cut mask for the 11nm node. This is about the resolution limit of available electron beam resist. Therefore, we had carefully selected the best processes for the safety of this experiment. Table 3 gives a summary of the results obtained with our champion resists. In the three first columns, we reported the minimum achievable pitch for lines, dots and holes patterns respectively. The fourth column gives information on the corresponding dose to size that made the line patterning successful. The last column shows the resist contrast.

From these results, we had no choice but picking the positive chemical amplified resist for our exposures. This means basically that the open area have to be exposed instead of just the dots, impacting the throughput as well as the amount of backscattered electrons. However the authors do not see any reason why a negative resist could not demonstrate better performance levels as the one shown here and they have the feeling that, lately, development works were more focused towards positive chemically amplified resists.

In an attempt to reduce the number of shots, we had also been testing a Negative Tone Develop process (NTD, 3rd row in Table 3). Unfortunately, the required resolution could not be reached but the results are certainly promising.

Lines 1:1

(nm) Dots 1:1

(nm) Holes

1:1 (nm) Dose

(µC/cm2) Contrast

Best negative resist

32

140 5.5

Best positive resist

24

26 210 18

Best results with NTD

34 36

93.5

Table 3: Summary results of our best processes. All resist are chemically amplified.

Figure 6 shows printed results with our champion process. The results at 50kV were obtained with a shaped beam tool, and the 5keV ones with a raster-scan electron beam piece of equipment. From these pictures, one can say that the resist is able to print 24nm dense lines and the shaped beam tool is already operating at its resolution limit at 26nm half pitch. This later system is the one that was used for patterning our gridded design layout.

a. 50kV results b. 5kV results

Figure 6: Printed results with our champion resist. Comparing results at 50kV (a) and 5kV (b), one can see that the resist is able to print 24nm h.p. lines and spaces and 26nm h.p. is about the resolution limit of our shaped beam tool. Our champion resist happens to be a positive one.

2.3 The layout

The layout to be patterned consists in a set of 6 logic blocks and 6 SRAM arrays; each one is a few tens of microns wide. The intention is to cover all combinations of gate and metal-1 pitches with the relevant cut sizes as presented in Table 1

for the 11nm and 14nm node, plus one intermediate gate pitch at 52nm (the gate pitch is also the minimum pitch for the cut mask in the x-direction).

3. WAFER RESULTS

3.1 Alignment and overlay margin

The alignment of the cut mask is critical towards the lines patterns along the y direction and towards the via or the contact layer along the x direction. However, at this stage, only the edges of the resist patterns printed during the first lithographic step remain on the wafer. They are made of tiny spacers that are very difficult to resolve with available alignment systems. As designed, our shaped beam tool scans the marks at 50keV and detects the secondary electrons bouncing back from the wafer to measure their locations. Unfortunately, this acceleration voltage is too high to reveal the small topography changes at the surface and the resulting signal is by far too noisy as shown on Figure 7.a. Therefore, for the safety of our experiment, we had to rely on alignment marks patterned on an under-layer.

However, an optical microscope can reveal enough of the mark to enable the alignment of the second exposure to the spacers, provided that its design was heavily segmented (Figure 7.b). Indeed, the individual spacers cannot be resolved individually and the alignment system detects only changes in reflection induced by the spacers all together (the denser the pattern, the better the contrast is).

It is also worth saying that all overlay error measurements (litho1 to under-layer, litho2 to litho1and litho2 to under-layer) were successfully measured thanks to segmented AIM mark (e.g. Figure 8). Regular box in box marks work as well.

a. Signal of an segmented alignment mark scanned at 50keV

b. Signals obtained with an optical microscope (highest contrast � standard alignment mark, lowest contrast � alignment marks segmented with spacers)

Figure 7: Example of signals obtained while reading litho 1 alignment marks during the cut mask exposure.

Figure 8: AIM mark used to measure the overlay after the cut mask exposure. The litho 1 mark is segmented to enhance the contrast.

We saw in 2.1 that, in case of an electron beam exposure, the resist could be coated inside the gap delimited by the spacers, simplifying the wafer stack during the cut mask exposure. Another advantage in doing so has to do with the guided diffusion of species that happens along the spacers. This results in higher overlay margin as illustrated on Figure 9. Here, we had exposed the cut mask with programmable y offsets with respect to the line patterns. We had then measured locally the resulting overlay error on a SEM and took pictures of the superposition of layers. It shows that the confinement of the exposure inside the spacers enlarges the overlay margin to, at least, +/- half the final CD value.

Figure 9: Study of the overlay margin. The pattern consists in two dots of resist inside the gap separating two consecutive spacers. They are resulting from the exposure of the cut mask with the photoresist coated directly on top of the spacers. The numbers at the bottom of the pictures give the measured overlay error normalized to the spacer width value.

3.2 Top down SEM images

Finally, Figure 10 shows an example of the wafer results that we obtained on the most aggressive logic test case (metal-1 pitch 36nm and gate 46nm). The SEM pictures were taken at various magnification levels in order to show the density of patterns (large view) and the achieved CD values which are on target (close-up view). The enclosure is just fine on this example for which we had failed in filling the gaps with resist. Obviously, it will be part of future works for the authors.

Hopefully, the resist could be coated successfully inside the spacers for the 44nm test cases as shown on Figure 11 although the lines CD was not on target making every two gaps to be very narrow. At this stage, the dots are still made of resist although they show up with the same contrast on the SEM images. The 36nm SRAM dots bridge sometimes, especially on the densest array, but the location happens to be situated on top of the spacers and, hopefully, the failure is not expected to be transferred into the substrate. It also should no longer be visible once a way could be found to make the resist to penetrate the trenches delimited by the spacers.

Figure 10: Top-down SEM pictures of the 11nm logic test case. The metal 1 pitch is equal to 36nm, the gate pitch 46nm and so, the minimum pitch for the dots.

Figure 11: Top-down SEM images of all the SRAM arrays designed for this experiment. The gate pitch varies from 46nm to 58nm; it is also the minimum pitch in the x-direction for the dots. The resist patterns of the 36nm SRAM happen to bridge sometimes. Hopefully the failure is located on top of the spacers and therefore, won’t be transferred into the substrate.

4. CONCLUSION

We saw that 1D gridded design style improves drastically the patterning process. Resulting layouts can easily be split into two layers: one made of lines and one of dots or holes. Many options already exist to address the first (line) patterning step with today’s optical scanners that can extend their lifetime indefinitely. The most mature technique makes usage of spacers to divide the exposed pitch by 2, 3 or even 4. But, Directed Self Assembly is also promising provided it can meet the defect specifications in a near future. We can then concentrate on the cut mask which is truly the one demanding resolution and the most important from a design point of view as it defines the functions of the circuit.

We also saw that the cut mask can be advantageously be exposed with an electron beam tool because the required resolution is already sufficient to pattern the 11nm technology node, the wafer stack is simplified, the overlay margin is enlarged compare to other optical techniques and it saves the cost of an additional mask in case of a design re-spin.

Finally, much better results could have been obtained if we had access to a negative resist with similar performance level as the one used for this experiment. It would also improve the throughput until a real breakthrough comes eventually from one of the multi electron beams tools that are being developed right now.

REFERENCES

[1] Y. Borodovsky, “Lithography 2009: Overview of Opportunities,” SemiCon West, 2009 [2] M.C. Smayling, C. Bencher, H.D. Chen, N. Dai, M.P. Duane, “APF Pitch-Halving for 22nm Logic Cells using

Gridded Design Rules,” Proc. SPIE Microlithography, 2008. [3] H. Yaegashi, “The self-aligned Spacer DP process towards 11nm node and beyond,” Lithography Workshop

2010. [4] V. Axelrad, M.C. Smayling, K. Tsujita, “Optical lithography applied to 20nm CMOS Logic and SRAM,” Proc.

SPIE Advanced Lithography, 2011.

[5] T.H.P. Chang, “Proximity effect in electron-beam lithography”, Journal of Vacuum Science Technology, 12(6), 1271-1275, 1975

[6] S.J. Lin, W.C. Wang, P.S. Chen, C.Y.Liu, T.N.Lo, Jack J.H. Chen, Faruk Krecinic, Burn J. Lin, “Characteristics Performance of Production-Worthy Multiple-E-Beam” ", SPIE Advanced Lithography 7637_43 (2010).

[7] L. Pain, “Transitioning of direct e-beam write technology from research and development into production flow”, Microelectronic Engineering 83, pp. 749-753, 2006.

[8] L. Pain, B. Icard, S. Tedesco, B. Kampherbeek, G. Gross, C. Klein, H. Loeschner, E Platzgummer, R. Morgan, S. Manakli, J. Kretz, C. Holhe, K-H Choi, F. Thrum, E. Kassel, W. Pilz, K. Keil, J. Butschke, M. Irmscher, F. Letzkus, P. Hudek, A. Paraskevopoulos, P. Ramm, J. Weber, “MAGIC: a European program to push the insertion of maskless lithography”, SPIE 6921_49 (2008).

[9] C. Bencher, H. Dai, L. Miao, Y. Chen, P. Xu, Y. Chen, S. Oemardani, J. Sweis, V. Wiaux, J. Hermans, L.-W. Chang, X. Bao, H. Yi, H.-S. Wong “Mandrel-based patterning: density multiplication techniques for 15nm nodes”, SPIE Advanced Lithography 2011 [7973-19]

[10] L. Oria, A. Ruiz de Luzuriaga, X. Chevalier, J. Alduncin, D. Mecerreyes, R. Tiron, S. Gaugiran, F. Perez-Murano “Guided self-assembly of block-copolymer for CMOS technology: a comparative study between grapho-epitaxy and surface chemical modification” ”, SPIE Advanced Lithography 2011 [7970-24]

AKNOWLEDGEMENTS

The authors would like to thank Luc Martin from Aselta Nanographics and the eBeam Innitiative consortium for help and support.