studies on performance limitations in cmos dacs - andersson

Linköping Studies in Science and TechnologyThesis No. 976

STUDIES ON PERFORMANCELIMITATIONS IN CMOS DACS

K Ola Andersson

LiU-Tek-Lic-2002:49

Department of Electrical EngineeringLinköpings universitet, SE-581 83 Linköping, Sweden

Linköping, November 2002

Studies on Performance Limitations in CMOS DACs

Copyright © 2002 K Ola Andersson

Department of Electrical EngineeringLinköpings universitetSE-581 83 Linköping

Sweden

ISBN 91-7373-452-7 ISSN 0280-7971

Printed in Sweden by UniTryck, Linköping, 2002

i

AbstractThe digital-to-analog converter (DAC) is a bottle neck in broadband communica-tion systems. High update rates are required in combination with high accuracy.In this work, we study factors that limit the performance of current-steeringDACs, focusing on the linearity properties of DACs for telecommunication appli-cations like digital subscriber lines (DSL).

There are many different sources of nonlinear behavior in current-steering DACs.Static errors dominate the low-frequency behavior, whereas the high-frequencybehavior is dominated by dynamic errors. The static errors are mainly caused bymismatch between components and finite output resistance in the current sources.The dynamic nonlinearity caused by parasitic capacitance in transistors and wiresis of special interest in this work. Two closely related types of models of thisdynamic nonlinearity were developed.

The linearity requirements on the converters for high-speed telecommunicationapplications can be hard to meet using a straightforward approach. Various meth-ods for improving the linearity of DACs are studied in this work. Some of themethods, like dynamic element matching (DEM) and a novel differential DACarchitecture, rely on redundant coding to improve the linearity. Two methods uti-lizing models of the dynamic nonlinearity caused by the parasitic capacitance inthe current sources were also developed. One of the methods utilizes a feedbacksimilar to delta-sigma modulation to spectrally shape the distortion. The othermethod is a type of predistortion where the input is modified in order to yield animproved output that is closer to the desired output, compared with using theoriginal input.

CMOS technology is popular for implementation of integrated circuits. Twomain advantages of CMOS, compared with, e.g., bipolar technology, is low costand the possibility of designing circuits with relatively low power consumption.

ii

CMOS is also the preferred technology for implementing large systems on a sin-gle chip with both analog and digital blocks. Three different current-steeringCMOS DACs were developed in this work, and are presented in the thesis. Mea-surement results show close resemblance with the simulation results obtainedfrom the developed models.

iii

AcknowledgmentsMany people deserve my gratitude for helping me during the years. First of all Ithank my supervisor, Prof. Mark Vesterbacka, for his guidance.

Dr. J Jacob Wikner, has taught me a lot about data conversion, mixed signaldesign, IT tools, and other things that have simplified my work. All help fromhim, M.Sc. Niklas U Andersson, and Dr. Mikael Karlsson Rudberg, all from Infi-neon Technologies Wireless Solutions Sweden (former Ericsson Microelectron-ics), is greatly appreciated.

I also thank Dr. Gunnar Björklund and M.Sc. Magnus Hägglund for supportingmy work during the years I spent doing research at Ericsson Microelectronics.

I appreciate the help and inspiration from all my colleagues at Ericsson Micro-electronics and Electronics Systems, Linköping University.

Finally, I thank my family, especially my wife Helena, for their support.

The work was financially supported by the Microelectronics Research Center(MERC) at Ericsson Microelectronics and the Center for Industrial InformationTechnology (CENIIT) at Linköping University.

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Table of Contents

Chapter 1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 The analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Outline of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Scientific contribution of the author . . . . . . . . . . . . . . . . . . . . . 31.4 Publications related to the author . . . . . . . . . . . . . . . . . . . . . . . 3

1.4.1 Conference publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2 Journal publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.3 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.4 Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 2DACs in Telecommunication . . . . . . . . . . . . . . . . . . . . 7

2.1 The DSL Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.1 Signals and modulation in ADSL . . . . . . . . . . . . . . . . . . . . 9

Distorted signals 102.1.2 DAC requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 The ideal DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.1 Representation of digital signals . . . . . . . . . . . . . . . . . . . 122.2.2 Digital-to-analog conversion . . . . . . . . . . . . . . . . . . . . . . 132.2.3 Nyquist rate DACs vs. oversampled DACs . . . . . . . . . . . 14

vi

2.3 DAC performance measures . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.3.1 Performance measures in the code domain . . . . . . . . . . . 16

Differential nonlinearity, DNL 16Integral nonlinearity, INL 17

2.3.2 Measures in the frequency domain . . . . . . . . . . . . . . . . . . 17Signal-to-noise ratio, SNR 19Signal-to-noise-and-distortion ratio, SNDR 19Effective number of bits, ENOB 19Spurious-free dynamic range, SFDR 20Total harmonic distortion, THD 20Multi-tone power ratio, MTPR 20

Chapter 3Modeling of Current-Steering DACs . . . . . . . . . . . . . 23

3.1 Classification of systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.2 The ideal current-steering DAC . . . . . . . . . . . . . . . . . . . . . . . . 243.3 Modeling of static errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3.1 Component mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Influence of graded element matching errors 28Modeling of random matching errors 34

3.3.2 Finite output resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.4 Modeling of dynamic errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4.1 State-space model of a current-steering DAC . . . . . . . . . 35Modeling of nonideal DAC components 35Circuit-level model of the DAC 38Simulations 42

3.4.2 A low-complexity model . . . . . . . . . . . . . . . . . . . . . . . . . 44A simple DAC model 45Model structure 46Simulation of the low-complexity model 48

3.5 Combined models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Chapter 4Compensation and Correction of Errors . . . . . . . . . . 51

4.1 Compensation and correction of static errors . . . . . . . . . . . . 514.1.1 Calibration of the MSBs . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Basic idea 52

vii

Proposed implementation 54Qualitative comparison with other calibration techniques 55

4.1.2 Distributed biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.1.3 Dynamic element matching . . . . . . . . . . . . . . . . . . . . . . . 56

Generalized DEM 57DEM utilizing switching trees 58Partial randomization DEM 59Mismatch shaping DEM 60

4.2 Compensation and correction of dynamic errors . . . . . . . . . . 614.2.1 Differential DACs with variable common mode . . . . . . . 62

Proposed redundant architecture 62Dithering of the common-mode level 64DC level minimization 64Common-mode level reduction with boundary conditions 66

4.2.2 Modulation of expected errors . . . . . . . . . . . . . . . . . . . . . 67Delta-sigma modulator basics 68Spectral shaping of nonlinearities 70Simulations 71Measurements 72

4.2.3 Predistortion of dynamic errors . . . . . . . . . . . . . . . . . . . . 72Predistortion block 73Simulation results 74

4.2.4 Implementation issues . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Chapter 5Current-Steering DAC Implementations . . . . . . . . . . 77

5.1 CMOS processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.1.1 Large signal models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

NMOS transistors 78PMOS transistors 79Notes on large signal models 80

5.1.2 Small signal models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805.2 Analog DAC building blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.2.1 CMOS current sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Single transistor current source 81Cascode current source 82

5.2.2 CMOS switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835.3 Digital DAC building blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.3.1 Binary-to-thermometer encoding . . . . . . . . . . . . . . . . . . . 84

viii

Thermometer coded and segmented structures in general 84Implementation of binary-to-thermometer encoders 87

5.3.2 Switch signal generators . . . . . . . . . . . . . . . . . . . . . . . . . . 905.4 DAC design strategies and measurement setup . . . . . . . . . . . 91

5.4.1 Overall layout structure . . . . . . . . . . . . . . . . . . . . . . . . . . 925.4.2 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935.4.3 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.5 A 14-bit DAC in 0.35 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . 945.5.1 Chip description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945.5.2 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5.6 A 14-bit PRDEM DAC in 0.35 µm CMOS . . . . . . . . . . . . . . . 975.6.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985.6.2 Simulations and comparison with measurements . . . . . . 100

Simulation setup and results 100Measurement results 101Comparison of SFDR performance 101

5.7 A dual 14-bit DAC in 0.25 µm CMOS . . . . . . . . . . . . . . . . . . 1025.7.1 Architecture and implementation . . . . . . . . . . . . . . . . . . 1035.7.2 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.8 Summary of implemented DACs . . . . . . . . . . . . . . . . . . . . . . 105

Chapter 6Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

1

1 IntroductionStrict requirements are imposed on the transmitting and receiving circuits forbroadband communication. A bottle neck in these communication systems is thedata converters, i.e., digital-to-analog converters (DACs) and analog-to-digitalconverters (ADCs). In this work we study performance limitations in DACs forhigh-speed applications. This chapter is an overview of the work and an introduc-tion to the thesis. In Sec. 1.1 we give a brief introduction to the analog front end(AFE) in which the DAC is an important building block. The different parts ofthe thesis are outlined in Sec. 1.2. The author’s scientific contribution to the areais outlined in Sec. 1.3, and the publications related to this thesis are listed inSec. 1.4. This chapter ends in Sec. 1.5 with a list of abbreviations used through-out the thesis.

1.1 The analog front end

Among the technologies that have emerged in recent years for broadband tele-communication are the different digital subscriber line (DSL) technologies. Asimplified view of a typical AFE used in digital subscriber line (DSL) applica-tions is shown in Fig. 1.1. There are a number of blocks with different functions.The multi-tone input signal to the DAC is constructed with an inverse fast Fouriertransform (IFFT) circuit, which is one of the digital signal processing (DSP)blocks. The DAC converts this signal to an analog signal which is the input to thefollowing analog transmitting circuits, consisting of lowpass (LP) filters and aline driver. The line driver is an amplifier with good driving capability used tofeed the signal into a twisted-pair copper wire. In the receive path there is areceive amplifier, whose output is connected via an LP filter to an ADC convert-

Introduction

2

ing the analog data to digital. The digital data is processed by a fast Fourier trans-form (FFT) circuit to determine the correct points in the different constellations,as will be discussed in Sec. 2.1.1.

1.2 Outline of the thesis

Below follows a brief outline of the different parts of the thesis.

Chapter 2 is an introduction to DACs in general and to their application in tele-communication. The requirements imposed on the DACs are presented and moti-vated. The performance measures that will be used throughout the thesis arepresented, as well as some terminology.

Chapter 3 deals with behavioral-level modeling of errors occurring when fabri-cating current-steering DACs in complementary metal oxide semiconductor(CMOS) technology. The errors that are studied are, e.g., caused by componentmismatch and parasitic components.

In Chapter 4 we use the models developed in Chapter 3 to develop and analyzemethods aiming for improving the linearity of DACs. The methods include cali-bration and biasing techniques, as well as predistortion and techniques based onredundant coding.

Three different current-steering CMOS DACs were developed in this work. Theimplementations are presented in Chapter 5 together with measurement resultsand discussions on the implementation of various building blocks. The work isconcluded in Chapter 6.

Figure 1.1 AFE for DSL applications.

DSP blocks

DAC

ADC

LP

LP

A

A

channel

line driver

receive amplifier

AFE

Scientific contribution of the author

3

1.3 Scientific contribution of the author

The text on DACs in telecommunication applications in Chapter 2 is intended asa background and introduction to the topic. The modeling of nonideal compo-nents discussed in Chapter 3 is a compilation of known models and modelsdeveloped by the author. The modeling of the influence of graded matchingerrors presented in Sec. 3.3.1 is original work of the author, along with all of thework presented in Sec. 3.4 regarding dynamic errors.

The discussions on error correction and compensation in Chapter 4 is also a com-pilation of known methods and methods developed by the author. The calibrationscheme presented in Sec. 4.1.1 is original work of the author. The remaining partof Sec. 4.1 discusses distributed biasing and dynamic element matching, whichare priorly known methods that have been implemented in two of the DACs pre-sented in Chapter 5. The techniques for reducing the impact of dynamic errorspresented in Sec. 4.2 were developed by the author.

The implementations of DACs presented in Chapter 5 were all designed in coop-eration with Niklas U Andersson and Dr. J Jacob Wikner. The DAC presented inSec. 5.5 was designed mainly by the author, the DAC in Sec. 5.6 mainly byNiklas U Andersson, and for the DAC in Sec. 5.7 the work was evenly distributedbetween the author and Niklas U Andersson. Dr. J Jacob Wikner has supervisedthe design work and provided some sub circuits and scripts useful for designautomation.

1.4 Publications related to the author

Publications, patents, and a tutorial, authored or coauthored by the author, relatedto the work presented in this thesis are listed below in chronological order foreach category.

1.4.1 Conference publications[1] K.O. Andersson and J.J. Wikner, “Modeling of the influence of graded

element matching errors in CMOS current-steering DACs,” Proc.NORCHIP Conference, pp. 399-404, Oslo, Norway, Nov. 8-9, 1999.

[2] K.O. Andersson and J.J. Wikner, “Characterization of a CMOS current-steering DAC using state-space models,” Proc. 43rd Midwest Symposiumon Circuits and Systems (MWSCAS’00), pp. 668-671, Lansing, MI, USA,Aug. 8-11, 2000.

Introduction

4

[3] K.O. Andersson, N.U. Andersson, and J.J. Wikner, “Spectral shaping ofDAC nonlinearity errors through modulation of expected errors,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’01),vol. 3, pp. 417-420, Sydney, Australia, May 6-9, 2001.

[4] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,“Models and implementation of a dynamic element matching DAC,” Proc.NORCHIP Conference, pp. 155-160, Kista, Sweden, Nov. 12-13, 2001.

[5] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, “Adifferential DAC architecture with variable common-mode level,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’02),vol. 1, pp. 113-116,Scottsdale, AZ, USA, May 26-29, 2002.

[6] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner,“Combining DACs for improved performance,” Proc. 4th IEEInternational Conference on Advanced A/D and D/A ConversionTechniques and their Applications, Prague, Czech Republic, June 26-28,2002.

[7] M. Vesterbacka, K.O. Andersson, N.U. Andersson, and J.J. Wikner,“Using different weights in DACs,” Proc. 4th IEE InternationalConference on Advanced A/D and D/A Conversion Techniques and theirApplications, Prague, Czech Republic, June 26-28, 2002.

1.4.2 Journal publication[8] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,

“Models and implementation of a dynamic element matching DAC,” toappear in Kluwer International Journal of Analog Integrated Circuits andSignal Processing, Special Issue: Selected Papers from the NORCHIP2001 Conference.

1.4.3 Patents[9] K.O. Andersson, “Improved current-steering D/A conversion,” Swedish

patent 0000731-0, 2000.

[10] K.O. Andersson, “Current Steering DAC”, pending Swedish patent, 2001.

[11] K.O. Andersson and J.J. Wikner, “Digital-to-analog converter having errorcorrection,” pending Swedish patent, 2002.

Abbreviations

5

1.4.4 Tutorial[12] J.J. Wikner, N.U. Andersson, K.O. Andersson, and M. Vesterbacka,

Compilation of error prevention and correction techniques for DACs,Tutorial IEEE 7th Int. Conf. on Electronics, Circuits, and System(ICECS’01), Malta, Sep. 2, 2001.

1.5 Abbreviations

Below is a list of the abbreviations used in the thesis.

ADC Analog-to-digital converter

ADSL Asymmetric digital subscriber line

AFE Analog front-end

CMOS Complementary metal oxide semiconductor

CO Central office

CPE Customer premises equipment

DAC Digital-to-analog converter

DCVS Differential cascode voltage switch

DEM Dynamic element matching

DMT Discrete multi-tone

DNL Differential nonlinearity

DSL Digital subscriber line

DSP Digital signal processing

ECH Echo canceled hybrid

ENOB Effective number of bits

FDM Frequency division multiplexing

FFT Fast Fourier transform

FIR Finite impulse response

FRDEM Full randomization dynamic element matching

GPIB General purpose interface bus

IFFT Inverse fast Fourier transform

INL Integral nonlinearity

LP Lowpass

Introduction

6

LSB Least significant bit

LTI Linear, time invariant

LVDS Low voltage differential signalling

MSB Most significant bit

MTPR Multi-tone power ratio

OSR Oversampling ratio

PC Personal computer

PCB Printed circuit board

POTS Plain old telephone service

PRDEM Partial randomization dynamic element matching

PSD Power spectral density

QAM Quadrature amplitude modulation

RF Radio frequency

SFDR Spurious-free dynamic range

SNDR Signal-to-noise-and-distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion

VDSL Very high speed digital subscriber line

WLAN Wireless local area network

7

2 DACs inTelecommunication

The main emphasis in this thesis is on the linearity of current-steering DACs. Thework is focused on converters for telecommunication applications, and this chap-ter is an introduction to DACs in general, and their application to telecommunica-tion. We start by outlining the set of signals the DACs are intended for, andillustrate the importance of high linearity in the intended applications. As appli-cation examples we use digital subscriber line (DSL) environments. The idealDAC is presented on a behavioral level, along with some important performancemeasures used to describe the degree of deviation from the ideal DAC.

2.1 The DSL Environment

Among the technologies that have emerged in recent years for broadband tele-communication are the different DSL technologies, e.g., asymmetric DSL(ADSL) and very high speed DSL (VDSL) [1, 2, 3, 4]. Common to these tech-nologies is their use of existing twisted-pair copper wires, originally intended forthe plain old telephone service (POTS), as a medium for transmission. One rea-son for this is that because the wires already exist, the cost for establishing theinfrastructure is considerably lower compared with, e.g., communication overoptical fibers where new lines have to be routed.

A typical DSL system is outlined in Fig. 2.1. The terminal on the user side, orcustomer premises equipment (CPE) side, is connected to the central office (CO)side with twisted-pair copper wires. The backbone network of the telecommuni-cation operator connecting the different CO stations is typically a high-speedoptical fiber link. DSL cannot be made available in every existing POTS node,

DACs in Telecommunication

8

since the attenuation of signals in copper wires is rather high for the frequencybands used. The maximum physical distance between the CPE and the CO sidefor ADSL is approximately 5.5 km. Over this limit the possible data rate is dra-matically reduced. This is due to the common use of so called loading coils onsuch long lines to improve the voice band properties of the line. As a side effectthese loading coils increase the attenuation for frequencies above the voice band[1].

In Fig. 2.2 we show the frequency bands used in ADSL, which is a standard thathas been well established and is widespread today. The range of frequenciesbelow 4 kHz is reserved for POTS. The frequency range between 30 and 138 kHzis used for upstream communication, i.e., data sent from the CPE side to the COside. Data is sent in the reverse direction, downstream, in the frequency rangebetween 138 kHz and 1.104 MHz. A guard band is present between the POTSband and the ADSL downstream band. The information in ADSL is transmittedusing a discrete multi-tone (DMT) signal. The ADSL version described here isknown as frequency division multiplexing (FDM) ADSL [1, 2, 3, 4], where theupstream and downstream bands are separated. There is also a version calledecho-canceled hybrid (ECH) ADSL, where the upstream and downstream bandsoverlap. ECH ADSL requires echo cancellation to separate transmitted data fromreceived data [1, 2, 3, 4].

The downstream capacity (up to 9 Mb/s) is larger than the upstream capacity (upto 1 Mb/s) since the desired rate for downloading data in some applications, e.g.,video-on-demand, is larger than the corresponding uploading rate [4], hence theterm asymmetric. In VDSL on the other hand, the communication is symmetric,i.e., the same data rate is available in both directions.

Figure 2.1 Overview of DSL system.

CPE

CPE

CPE

CO CO

CPE

CPE

Backbone

The DSL Environment

9

The maximum signal bandwidth in ADSL is about 1 MHz. In other types of tele-communication and data communication, e.g., VDSL and wireless local area net-work (WLAN), the corresponding bandwidths lie around 10 MHz, and in futurecommunication standards the bandwidths may be even higher.

2.1.1 Signals and modulation in ADSL

As mentioned earlier, ADSL uses a DMT signal for data transmission. For exam-ple, in the downstream band the data is sent on 224 carriers between 138 kHz and1.104 MHz. Generally, a DMT signal, , can be expressed (in the time-domain) as

. (2.1)

It should be noted that, with the notation used in (2.1), some of the tones musthave zero amplitude in ADSL, since their frequencies are in the POTS band orthe guard band (or in the wrong ADSL band for FDM ADSL).

To each carrier there is an associated quadrature amplitude modulation (QAM)constellation [3] given by the values of and . The bits that are to be transmit-ted are divided into different constellations. The number of bits modulated on

Figure 2.2 Frequency bands used in FDM ADSL.

0 4 30 138 1104Frequency [kHz]

Frequency bands in FDM ADSL

PO

TS

guar

d ba

nd

AD

SL

upst

ream

AD

SL

dow

nstr

eam

Y t( )

Y t( ) ai i ω0 t⋅ ⋅( )sin bi i ω0 t⋅ ⋅( )cos+i 1=

K

∑= =

r i i ω0 t⋅ ⋅ φi+( )sini 1=

K

∑=

ai bi


10

each carrier is not fixed, but is determined during training sequences and dependson the quality of the transmission link for the corresponding frequency band. InFig. 2.3(a) a 16-QAM constellation is shown, and the point of the constellation tobe transmitted determines the actual values of and .

Distorted signals

When the signal is sent from the transmitter to the receiver it will be distorted.Sources of signal distortion are, e.g., attenuation in the twisted-pair wire and non-linearities in the transmitting circuits. Here we examine the impact on the QAMconstellation for different types of distortion using simulations in Matlab. Thesimulations are performed using discrete time signals. Seven tones with angularfrequencies for have been used, and to each ofthese tones there is a 16-QAM constellation as illustrated in Fig. 2.3(a). As anexample we investigate how the constellation for the tone with is affectedby distortion. For the remaining tones we choose random values of andwith rectangular distribution, and for each such random combination we considerall possible combinations of and . The constellations plotted in Fig. 2.3 arethe results of 100 stochastic outcomes.

First we examine how the constellations are affected by a linear distortion. Lineardistortion affects each carrier by a signal independent phase shift and a signalindependent attenuation (or possibly amplification). Hence, the constellation ofthe linearly distorted carrier is a rotated and scaled copy of the original constella-tion, as illustrated in Fig. 2.3(b). The linear distorter is a simple finite impulseresponse (FIR) filter given by . Since there is aone-to-one mapping from the original constellation to the distorted constellation,the original constellation can be restored once the attenuation and the phase shiftis known.

The constellations for signals that are distorted by a simple nonlinearity,, are shown in Fig. 2.3(c). It can be seen that there is no

longer a one-to-one mapping between the original constellation and the distortedconstellation. The location of the received point is depending on the amplitudesand phases of the other tones as well. When the nonlinearity becomes moresevere, the clouds of points start to overlap and errors occur in determining theoriginal location of the transmitted point.

With these simple examples we have illustrated the importance of high linearityin all parts of the transmission link. Noise added to the signal will have similareffects on the constellations as a nonlinearity, so there are also requirements onthe noise margins.

ai bi

Ωn n π 8⁄⋅= n 1 2 … 7, , ,=

n 3=ai bi

a3 b3

y n( ) 0.5 x n( )⋅ 0.1 x n 1–( )⋅+=

y n( ) x n( ) 0.2 x3 n( )⋅+=

The DSL Environment

11

2.1.2 DAC requirements

Since the copper wires used in DSL were initially intended for POTS, which is anarrowband communication technology, strict requirements are imposed on thetransmitting and receiving circuits in order to achieve broadband communicationover these lines. General requirements on a DAC for DSL applications, which wewill use as a guideline throughout this thesis, can be found in Table 2.1.

(a)

(b) (c)

Figure 2.3 (a) 16-QAM constellation, (b) linearly distorted constellation, and (c) nonlin-early distorted constellation.

PropertyGeneral

requirement

Signal bandwidth 1-10 MHz

Effective number of bits 12-14

Table 2.1 General DAC requirements for DSL and similar applications.

−1.5 −0.5 0.5 1.5

−1.5

−0.5

0.5

1.5

Original constellation

a

b

−1.5 −0.5 0.5 1.5

−1.5

−0.5

0.5

1.5

Linearly distorted constellation

a

b

−1.5 −0.5 0.5 1.5

−1.5

−0.5

0.5

1.5

Nonlinearly distorted constellation

a

b


12

A comment on the requirements is that 12-bit DACs are commonly used in FDMADSL, whereas ECH ADSL often requires 14 bits of accuracy [1]. For someemerging communication standards the bandwidths are much higher than inTable 2.1 [5].

2.2 The ideal DAC

In this section we introduce the ideal DAC and the notation for digital signalsused throughout the thesis.

2.2.1 Representation of digital signals

The input to the DAC is a digital signal, that we denote . The parameterdenotes the sample (or update) instant. We will use the notation for both thevector form representation

(2.2)

and for the integer value

, (2.3)

since they easily can be distinguished by the context. The binary valued signalsare the individual bits of the digital word , and is the weight asso-

ciated with bit . The weights depend on what coding scheme is used. For exam-ple, in the binary-coded case we have that , whereas for all inthe thermometer-coded case. These two types of codes are common in data con-version, and are more thoroughly described in Sec. 5.3.1. We use the notationfor the inverse of , and denotes with all individual bits inverted.

Throughout this thesis we represent the weights, , as positive numbers. Thatis, we treat digital numbers and signals as positive. In the DSP blocks, digital sig-nals are generally expressed as signed numbers, using, e.g., two’s complementrepresentation [6]. However, all designs of DACs in this thesis operate by sum-ming positive analog weights, so from a DAC designer’s point of view it is moreconvenient to use positive weights also in the digital domain.

X n( ) nX n( )

X n( ) bN 1– n( ) bN 2– n( ) … b0 n( ), , ,[ ]=

X n( ) bk n( ) wk⋅k 0=

N 1–

∑=

bk n( ) X n( ) wkk

wk 2k= wk 1= k

bb X X

wk

The ideal DAC

13

2.2.2 Digital-to-analog conversion

The purpose of a DAC is to perform a mapping of the digital input to an analog.The analog signal can be represented by, e.g., an electrical current or voltage. Ifan analog signal, , that has a limited frequency bandwidth, , is uniformlysampled with a sample frequency to a discrete-time signal, , itcan be perfectly reconstructed by the function

, (2.4)

where for , , and is thereconstructed signal. The ideal DAC could be defined as a device performing themapping from the digital signal, , to the analog signal, , given by

, (2.5)

where is the gain of the DAC, is the update period, and .For practical reasons, e.g., the noncausal properties of the function, weinstead define the ideal DAC according to

, (2.6)

where is a unit square pulse with duration , i.e.,

. (2.7)

In other words, , is a piecewise constant signal with

for . (2.8)

When designing a DAC, the goal is to come as close as possible to the operationdescribed in (2.6) and (2.8). It is, however, not possible to achieve exactly theoperation of an ideal DAC, since given by (2.6) is discontinuous (unless

is constant). The sinc pulse and the unit square pulse are plotted together inFig. 2.4.

A t( ) f 0f s 2 f 0⋅> D n( )

A t( ) D n( ) sinc f s t nT–( )⋅( )⋅n ∞–=

∞

∑=

sinc x( ) sin π x⋅( ) π x⋅( )⁄= x ∞– ∞,[ ]∈ T 1 f s⁄= A t( )

X n( ) A t( )

A t( ) K X n( ) sinc f u t nT–( )⋅( )⋅n ∞–=

∞

∑⋅=

K T f u f s 1 T⁄= =sinc

A t( ) K X n( ) P t nT–( )⋅n ∞–=

∞

∑⋅=

P t( ) T

P t( )1 for 0 t T<≤0 otherwise

=

A t( )

A t( ) K X n( )⋅ K bi n( ) wi⋅i 0=

N 1–

∑⋅= = nT t≤ n 1+( )T<

A t( )X n( )


14

In the applications considered here, there is no information in the DC level of thesignal. In the general case, we add a constant to the right hand sides of (2.6) and(2.8).

2.2.3 Nyquist rate DACs vs. oversampled DACs

Assume that we want to output a signal with bandwidth Hz. By the samplingtheorem, the minimum required update frequency is [7]

(2.9)

as touched upon in the previous section. A DAC using this update frequency isreferred to as a Nyquist rate DAC.

In an ideal data converter, the only errors are those caused by the quantizationprocess, referred to as quantization noise. It is sometimes argued that there is noquantization noise in a DAC, since the input signal is already quantized [8]. How-ever, since the input is already quantized it contains quantization noise. We cantherefore talk about quantization noise in the output signal from a DAC, even ifthe quantization is a process in the circuits preceding the DAC.

For an -bit DAC with relatively large and with a varying input signal, thequantization noise, , can often be adequately described as a white noise sig-nal with rectangular distribution between 0 and 1 (assuming that the size of thequantization step is unity). The total power of the quantization noise is then [7, 9]

Figure 2.4 The sinc pulse (dashed) and the unit square pulse (solid) plotted together.

−5 −4 −3 −2 −1 0 1 2 3 4 5

0

1

Normalized time, t/T

Am

plitu

de le

vel

sinc(t/T) and P(t/T) plotted together

f 0

f u 2 f 0⋅=

N Nq n( )

The ideal DAC

15

. (2.10)

This power is evenly distributed over frequencies in the interval (sincethe noise is treated as white). If we use an update frequency larger than therequired , some of the noise will appear outside of the signal band, at fre-quencies in the interval . This part of the noise can be filtered out,since the signal does not have any spectral content for these frequencies, and theoverall signal-to-noise-and-distortion ratio (SNDR) (see Sec. 2.3.2) is improved.

A DAC with is known as an oversampled DAC, and the oversamplingratio (OSR) is defined as

. (2.11)

Compared with a Nyquist rate DAC, the signal-to-noise ratio (SNR) due to quan-tization noise is increased with dB [8]. To further decrease thepower of the quantization noise within the signal band, delta-sigma modulationtechniques are often used. These techniques utilize feedback loops to spectrallyshape the quantization noise to frequencies outside of the signal band, and arebriefly outlined in Sec. 4.2.2.

Another reason for using oversampling is that using square pulses instead of sincpulses for reconstruction affects the spectral properties of the output signal. Let

denote the power spectrum of the signal reconstructed with sinc pulses,and let denote the corresponding spectrum for the signal reconstructedusing square pulses. Then, the following equality holds [7, 8]

, (2.12)

i.e., the signal is attenuated for frequencies close to . For the Nyquist fre-quency, , this attenuation is . For a Nyquistrate DAC this attenuation may need to be compensated for with so called anti-sinc filters, depending on the requirements of the application. For oversampledDACs there is no spectral content of the signal close to the Nyquist frequency, ifhigh enough OSR is used. Therefore, the attenuation becomes neglectable.

Moreover, the images of the signal appearing around multiples of the update fre-quency need to be filtered out with image rejection filters before the signal entersthe communication channel to minimize the interference with other types ofcommunication utilizing other frequency bands. In an oversampled DAC the

Pq Var q n( )( ) 112------= =

0 f u 2⁄,( )

2 f 0⋅f 0 f u 2⁄,( )

f u 2 f 0⋅>

OSRf u

2 f 0⋅-------------=

10 log10 OSR( )⋅

Asinc ω( )Asquare ω( )

Asquare ω( ) Asinc ω( ) sinc ω2π f u------------( )⋅=

f uf u 2⁄ sinc 1 2⁄( )( ) 1– π 2⁄ 3.9 dB≈=


16

images are better separated from the signal, compared with Nyquist rate DACs,and the requirements on the transition band widths of the image rejection filtersare reduced.

2.3 DAC performance measures

Some performance measures are needed to describe the quality of a DAC. In thissection we define the performance measures that are commonly used for charac-terizing communication DACs [10, 11], used throughout this thesis.

2.3.1 Performance measures in the code domain

The static transfer characteristics, , of a nonideal 4-bit DAC is shown inFig. 2.5. We also plot the line , i.e., the transfer character-istics for the corresponding ideal DAC, for comparison. and are chosento yield a best-fit straight line (least mean square) with respect to the data pointsfor the nonideal DAC. If the DAC would be linear, all data points would be on thestraight line. In the following we define two common linearity measures in thecode domain.

Differential nonlinearity, DNL

The differential nonlinearity (DNL) for a code , , describes the devia-tion from an ideal step in the transition from to [9]. is definedas

Figure 2.5 Static transfer characteristics of a nonideal 4-bit DAC.

A X( )Y X( ) K X⋅ Y offset+=

K Y offset

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0123456789

101112131415

Input code

Out

put l

evel

Static transfer characteristics for a nonideal DAC

X DNL X( )X 1– X DNL X( )

DAC performance measures

17

(2.13)

The DNL for the DAC with the transfer characteristics in Fig. 2.5 is plotted inFig. 2.6.

Integral nonlinearity, INL

The integral nonlinearity (INL) describes the deviation from the line [10],i.e.,

. (2.14)

Combining (2.13) and (2.14) yields that

. (2.15)

Hence, DNL is a redundant measure (if the INL is known). The INL for the DACwith the transfer characteristics in Fig. 2.5 is plotted in Fig. 2.7.

2.3.2 Measures in the frequency domain

For communication DACs we are often more interested in the frequency domainbehavior than in the corresponding code-domain behavior [10]. In Fig. 2.8 weshow a typical power spectral density (PSD) plot of an output signal for a DACwith a single-tone (sinusoidal) input signal. Nonlinearities in the DAC cause har-

Figure 2.6 DNL of a nonideal 4-bit DAC.

DNL X( ) A X( ) A X 1–( )– K–K

-------------------------------------------------=

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

−2

−1

0

1

2

Input code

DN

L

DNL for a nonideal DAC

Y X( )

INL X( ) A X( ) Y X( )–K

-----------------------------=

DNL X( ) INL X( ) INL X 1–( )–=


18

monic distortion in the output signal. The second and third harmonics are indi-cated in Fig. 2.8. Hence, the different measures of distortion presented in thissection is also measures of the DAC linearity.

The signal impurities can be divided into noise and distortion. Noise is typicallysignal independent, due to, e.g., thermal activity in circuit elements, having asmooth spectral appearance. Distortion, on the other hand, is generally character-

Figure 2.7 INL of a nonideal 4-bit DAC.

Figure 2.8 PSD plot of the output signal from a nonideal DAC with a single-tone input sig-nal.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

−2

−1

0

1

2

Input code

INL

INL for a nonideal DAC

SFDR

PSD for distorted single−tone signal

Frequency

PS

D

fundamental

2:nd harmonic

3:rd harmonic


19

ized by clearly visible peaks in the output spectrum and is often signal dependent,e.g., due to circuit nonlinearities. Gray zones are present in the analysis, e.g.,quantization errors are clearly signal dependent, but are often treated as sourcesof noise. The total output power is

, (2.16)

where is the power of the wanted output signal, is the noise power,and is the total power due to distortion.

Signal-to-noise ratio, SNR

As a measure of how well the signal can be distinguished from the noise, we havethe signal-to-noise ratio (SNR)

. (2.17)

Signal-to-noise-and-distortion ratio, SNDR

The signal-to-noise-and-distortion ratio (SNDR, in some literature abbreviatedSINAD) is

. (2.18)

This is a more adequate measure of signal quality than SNR if a large amount ofdistortion is present. The SNDR due to quantization noise of the ideal -bit(Nyquist rate) DAC with a full-scale sinusoidal input signal can be expressed as[7, 8]

dB. (2.19)

Effective number of bits, ENOB

For a nonideal DAC we rearrange (2.19) to define the effective number of bits(ENOB) as

, (2.20)

which is only a different way of expressing the SNDR. It is a useful measure to,e.g., find a lower bound on the number of bits, , to achieve a given SNDR.

Pout Psignal Pnoise Pdist+ +=

Psignal PnoisePdist

SNRPsignal

Pnoise---------------=

SNDRPsignal

Pnoise Pdist+-------------------------------=

N

SNDR 6.02N 1.76+≈

ENOB SNDR 1.76–6.02

--------------------------------=

N


20

Spurious-free dynamic range, SFDR

The spurious-free dynamic range (SFDR) is defined as

, (2.21)

where is the power of the largest spurious (unwanted) tone. SFDR is indi-cated in Fig. 2.8. It should be mentioned that this definition of SFDR, which isoften used for data converters, is different from the one most often used foramplifiers, in which case SFDR is defined as the SNR for the maximum outputpower without having any spurious tones [8].

Total harmonic distortion, THD

The second and third harmonic tone is indicated in Fig. 2.8. If the power of the:th harmonic tone is denoted , the total harmonic distortion (THD) is

, (2.22)

i.e., THD is the power of all harmonics, normalized with respect to the signalpower.

Multi-tone power ratio, MTPR

Nonlinear systems, as opposed to linear systems, cannot be completely describedby single-tone properties [12]. In multi-carrier applications, e.g., ADSL, themulti-tone properties of the transmitting system are more adequate for describingthe performance. One multi-tone linearity measure often used is the multi-tonepower ratio. A number of tones with equal amplitude and frequency spacing areapplied to the input. One tone is left out, and the multi-tone power ratio (MTPR)is defined as the ratio between the rms amplitude of a carrier and the peak spuri-ous tone in the region of the left out tone [10], as indicated in Fig. 2.9. MTPR is ameasure on how much the other tones affect the amplitude of a specific tone,compare, e.g., with the nonlinearly distorted constellation discussed in Sec. 2.1.1.

SFDRPsignal

Pls---------------=

Pls

n Pn

THD

Pn

n 2=

∞

∑Psignal----------------=


21

Figure 2.9 PSD plot of a multi-tone signal with one tone left out.

MTPR

PSD for distorted multi−tone signal

Frequency

PS

D


22

23

3 Modeling of Current-Steering DACs

In this chapter we discuss modeling of current-steering DACs. Both static errors,such as component mismatch, and dynamic errors, e.g., due to parasitic capaci-tance are discussed. The study is focused on the dynamic errors.

Modeling of nonlinear behavior in analog circuits is often made using polyno-mial models, such as Taylor or Volterra series expansions [12, 13]. Some initialattempts of characterizing DACs using Volterra models were made in this work.These were, however, unsuccessful in capturing the nonlinear behavior of thecurrent-steering DAC, except for in very limited frequency bands. Hence, thepolynomial type models have been discarded in this work.

3.1 Classification of systems

Consider an arbitrary system (i.e., mapping from an input signal to an output sig-nal) with input and output . Some useful definitions for classificationof such a system are presented here.

• Suppose that we have two arbitrary input signals and , yieldingthe output signals and , respectively. Then the system is calledlinear if the input signal yields the output signal

, where and are arbitrary constants. Otherwise,the system is nonlinear.

X n( ) Y n( )

X1 n( ) X2 n( )Y 1 n( ) Y 2 n( )

X n( ) aX1 n( ) bX2 n( )+=Y n( ) aY 1 n( ) bY 2 n( )+= a b

Modeling of Current-Steering DACs

24

• Consider the special case for the signals above when ,where is an arbitrary integer. The system is time-invariant if

, otherwise the system is time-variant.

• The system is called causal if the value of the output signal, , at instant only is a function of the input signal for

(i.e., future values of have no influence on the output).

• The system is called static if the value of the output signal, , at instantonly is a function of the input signal for . Otherwise, the sys-

tem is called dynamic.

Some comments can be made regarding the application of the definitions toDACs. When implementing the DAC it is desired to come as close as possible (insome sense) to a linear, time-invariant (LTI) system. However, the linearity prop-erty is, as for most other physical systems, limited by the fact that the DAC has alimited input (and output) range determined by the number of bits in the inputsignal. Thus, the constants and in the definition of linearity cannot be arbi-trary, since overflow in the input signal causes a large amount of nonlinear distor-tion. Moreover, the time-invariance property does not hold because of aging ofthe chips and temperature variations. We do, however, regard the DAC as a time-invariant system over a limited range of time. In ADSL each DMT signal has aduration of less than 1 ms, and we consider the DAC to be a time-invariant sys-tem for this short period of time.

3.2 The ideal current-steering DAC

The ideal current-steering DAC is composed of a number of ideal currentsources, , and a number of ideal switches, , as shown inFigure 3.1. To each current source, , we associate a weight, , such that

, (3.1)

where is called the unit current. The DAC shown in Fig. 3.1 utilizes a differ-ential architecture. The switches are controlled by the digital input such that thecurrent from source is directed to the analog output terminal when the dig-ital input bit , otherwise the current is directed to terminal . The totalpositive output current is

. (3.2)

X2 n( ) X1 n k–( )=k

Y 2 n( ) Y 1 n k–( )=

Y n1( )n1 X n( ) n n1 n1 1– n1 2– …, , ,=

X n( )

Y n1( )n1 X n( ) n n1=

a b

I0 … IM 1–, , S0 … SM 1–, ,I i wi

I i wi Iunit⋅=

Iunit

I i A+bi 1= A–

I+ bi I i⋅i 0=

M 1–

∑ Iunit bi wi⋅i 0=

M 1–

∑⋅ Iunit X⋅= = =

The ideal current-steering DAC

25

Similarly for the negative output current

. (3.3)

If we let the weights, , be the same as for the digital bits, , and compareexpression (3.2) with expression (2.8) in Chapter 2, we find that the output cur-rent can be regarded as the output from an ideal DAC. Similarly, the outputcurrent can be regarded as the output from an ideal DAC with input

.

Differential architectures are often used to reject noise and distortion [8]. The dif-ferential output current, , is defined as

, (3.4)

where is the value of when all bits . From (3.4) we see that thedifferential output current can be regarded as the output from an ideal DAC. Wealso refer to the outputs in terms of voltages, i.e.,

, (3.5)

, (3.6)

and

Figure 3.1 The ideal current-steering DAC.

I0 Ij IN1

b0 bj bN1

RLRL

II+A+ A

I– Iunit bi wi⋅i 0=

M 1–

∑⋅ Iunit X⋅= =

wi bi

I+I–

X bN 1– … b0, ,[ ]=

Idiff

Idiff I+ I–– 2 Iunit bi wi⋅∑⋅ ⋅ Iunit wi

i 0=

M 1–

∑⋅–= = =

2 Iunit X⋅ ⋅ Iunit Xmax⋅–( )=

Xmax X bi 1=

V + RL I+⋅ RL Iunit X⋅ ⋅= =

V – RL I–⋅ RL Iunit X⋅ ⋅= =


26

, (3.7)

where is the load resistance.

We have now shown that the desired operation of an ideal DAC can be achievedby directing the currents from ideal current sources using ideal switches con-trolled by the digital input. When implementing current-steering DACs in, e.g.,CMOS technology, building blocks like the current sources and switches are non-ideal. In the rest of this chapter, behavioral-level modeling is used to discuss theimpact of nonideal components on the performance characteristics of the current-steering DAC.

3.3 Modeling of static errors

Static errors are defined as errors that are only depending on the present inputcode. This definition is similar to the definition of a static system given inSec. 3.1. In this section we discuss two different sources of static errors; compo-nent mismatch and finite output resistance of current sources.

3.3.1 Component mismatch

Assuming a long channel device and neglecting channel length modulation, thedrain current in an NMOS transistor in the saturation region can be approximatedby

. (3.8)

The parameter is the charge carrier (electron) mobility which is dependent on,e.g., doping concentration and temperature [14]. is the oxide capacitance perunit area, and depends on, e.g., the oxide thickness. and are the width andthe length of the transistor channel, is the gate-source voltage, and is thethreshold voltage, which is dependent on, e.g., the bulk-source voltage of thetransistor. A closer description of MOS transistors is given in Sec. 5.1.

If these transistors are to be used as current sources in a current-steering DAC itis important that the transistors are well matched to obtain the correct bit weights(within tolerable margins). Hence, it is desirable to manufacture transistors withthe same value of the parameters , , , etc. However, when manufacturingchips, variations in these parameters over the chip area occur, something we referto as component mismatch.

V diff V + V –– RL Idiff⋅ 2 Iunit RL X⋅ ⋅ ⋅ Iunit RL Xmax⋅ ⋅–= = =

RL

ID

µ Cox⋅2

---------------- WL----- V gs V T–( )2⋅ ⋅=

µCox

W LV gs V T

µ Cox V T

Modeling of static errors

27

On a higher level of abstraction mismatch leads to deviations from the desiredoutput currents in the current sources implemented with MOS transistors. Thecurrent from current source can be expressed as

, (3.9)

where the first term, , is the desired current, and the second term, , isthe deviation due to mismatch. This is equivalent to the model shown in Fig. 3.2,where an error current source, , is connected in parallel with the desired cur-rent source, .

For good matching it is important to have equivalent geometrical boundary con-ditions for the devices to be matched [8]. For this purpose it is a common designstrategy to divide the components, e.g., transistors and capacitors, into unit ele-ments which are connected in parallel. Following this strategy, a current sourcewith weight is constructed connecting unit current sources in parallel. Welet be a set of unit current sources. To each unit current source, ,there is a corresponding matching error, . Further we let be a set of indi-ces such that the current

, (3.10)

i.e., the current source is a parallel connection of the unit current sources with indices belonging to the set . We can rewrite (3.10) yielding

. (3.11)

The last term in (3.11) is identified as the matching error of , i.e.,

. (3.12)

If we consider two MOS transistors, and , on the same die, biased withthe same voltages and having (nominally) the same geometry, and compare thecorresponding drain currents and it has been shown that [15]

Figure 3.2 Model of current source with matching error.

I i

I i wi Iunit⋅ ∆i+=

wi Iunit⋅ ∆i

∆iwi Iunit⋅

Ii wi Iunit Di

wk wkIunit j, Iunit j,

δ j J i wi

I i Iunit j,j J i∈∑=

I iIunit j, j J i

I i Iunit j,j J i∈∑ wi Iunit⋅ δ j

j J i∈∑+= =

I i

∆i δ jj J i∈∑=

M1 M2

I1 I2


28

, (3.13)

where is the distance between the centers of the transistors, and and areprocess dependent constants. We see that for good matching properties (i.e.,small variance) we should use transistors with large area ( ) and keep themas close as possible (small ). Different yield estimation methods based on(3.13) have been proposed in the literature [16, 17]. The use of a current-steeringDAC for efficient estimation of the parameters in (3.13) was presented in [18].

Another useful guideline for good matching properties, which is not captured in(3.13), is to avoid covering the transistors with metal, since metal coverageincreases the variance [19].

Influence of graded element matching errors

In this section we analyze the influence of the second term in (3.13), which isoften referred to as graded matching errors. This analysis was originally pre-sented in [20].

On a larger scale, graded matching errors are caused by parameters with circulardistribution over the wafer [15], i.e., the value of a parameter is roughly deter-mined by the distance from the center of the wafer. As a first order approximationover a small area (e.g., a chip), we can make a Taylor expansion of the parameterwith respect to the geometrical coordinates, which is illustrated in Fig. 3.3.

The current from a current source can thus be approximately expressed as

, (3.14)

Figure 3.3 Illustration of a parameter (e.g., oxide thickness) with circular distribution overthe wafer. Over a small area (e.g., a chip) the parameter value can be approxi-mated with the first order Taylor expansion.

Var I1 I2–( )AI

2

W L⋅------------- SI

2 D2⋅+=

D AI SI

W L⋅D

Iunit j, Iunit kx x⋅ ky y⋅+ +=


29

where and are constants and and are the geometrical coordinates of thecurrent source with respect to a cartesian coordinate system. The matching error

is given by

. (3.15)

When implementing current-steering DACs, the unit current sources are oftenplaced in an array, as indicated in Fig. 3.4(a), where each square represents a unitcurrent source. A straightforward assignment of unit current sources to the differ-ent current sources of a 6-bit binary weighted DAC is shown in Fig. 3.4(b),where the upper half of the array is dedicated to the most significant bit (MSB),the upper half of the remaining part of the array to MSB-1, etc., until the remain-ing bits can be placed in the last row of the array.

The way of assigning unit current sources indicated in Fig. 3.4(b) is known tohave poor properties in terms of suppressing graded matching errors. Differentlayout techniques for suppressing the influence of graded matching errors havebeen proposed in the literature [21, 22, 23]. However, we use this approach toshow how matching errors can affect the DAC performance. First of all, we gen-eralize the concept illustrated in Fig. 3.4(b) for an -bit binary weighted DACwith the least significant bits (LSBs) contained within the bottom row. Forcomparison, the DAC in Fig. 3.4(b) has and . The array will thenhave elements in the -direction and elements in the -direction.

Computing the values of the different yields

(a) (b)

Figure 3.4 (a) Array of unit current sources and (b) unit current source assignment for a 6-bit binary weighted DAC.

kx ky x y

δ j

δ j x y,( ) kx x⋅ ky y⋅+=

I i

x

y

5 5 5 5 5 5 5 5

5 5 5 5 5 5 5 5

5 5 5 5 5 5 5 5

5 5 5 5 5 5 5 5

4 4 4 4 4 4 4 4

4 4 4 4 4 4 4 4

3 3 3 3 3 3 3 3

2 2 2 2 1 1 0

x

y(b)

NM

N 6= M 3=2M x 2N M– y

∆i


30

, (3.16)

where and are the coordinates of unit current source , and andare the average coordinates for the unit current sources assigned to bit . We nor-malize the coordinate axis such that the distance between adjacent unit currentsources are unity in both the - and the -direction, and we also normalize thecurrents so that . We have that

for , (3.17)

for , (3.18)

for , (3.19)

and

for . (3.20)

The parameter only affects the errors for the LSBs. These errors are typi-cally much less than the errors for the more significant bits (assuming that isnot very large compared with ) due to the factor in (3.16). With this as anargument we set to simplify the calculations. This results in

for (3.21)

and

for . (3.22)

We define the error signal, , as

∆i δ jj J i∈∑ kx x j⋅ ky y j⋅+

j J i∈∑= = =

wi kx

x j

wi-----

j J i∈∑⋅ ky

y j

wi-----

j J i∈∑⋅+

⋅ wi kx xi⋅ ky yi⋅+( )⋅==

x j y j Iunit j, xi yii

x yIunit 1=

xi 2M 1– 32--- 2i⋅+= i 0 … M 1–, ,=

xi 0= i M … N 1–, ,=

yi 2N M– 1–– 2 1–+= i 0 … M 1–, ,=

yi 2N M– 1––32--- 2i M–⋅+= i M … N 1–, ,=

kx Mkx

ky wikx 0=

∆i wi ky 2 1– 2N M– 1––( )⋅ ⋅= =

ky 2i 1– 2i N M– 1–+–( )⋅( )= i 0 … M 1–, ,=

∆i wi ky32--- 2i M–⋅ 2N M– 1––

⋅ ⋅= =

ky32--- 22 i⋅ M–⋅ 2i N M– 1–+–

⋅= i M … N 1–, ,=

e n( )


31

, (3.23)

i.e., the actual output signal minus the wanted output signal. Clearly,

, (3.24)

where . The power of this error signal, , can be expressed as

. (3.25)

If we assume that the probability that and are equal, i.e.,

(3.26)

we obtain

, (3.27)

which yields

. (3.28)

The covariance terms in (3.25) are signal dependent, since

(3.29)

and can therefore not be expressed explicitly for an arbitrary signal. We shall inthe following assume that the covariance sum in (3.25) is zero (or small), whichis true if, e.g., the bits are mutually uncorrelated. With this assumption,becomes

. (3.30)

Combining (3.21), (3.22), (3.28), and (3.30) yields

e n( ) bi n( ) I i⋅i 0=

N 1–

∑ bi n( ) wi Iunit⋅ ⋅i 0=

N 1–

∑–=

e n( ) bi n( ) ∆i⋅i 0=

N 1–

∑ ei n( )i 0=

N 1–

∑= =

ei n( ) bi n( ) ∆i⋅= Pe

Pe Var e n( )( ) Var ei n( )( )i 0=

N 1–

∑ Cov ei n( ) e j n( ),( )i j≠∑+= =

bi n( ) 1= bi n( ) 0=

P bi n( ) 1=( ) P bi n( ) 0=( ) 12---= =

Var bi n( )( ) E bi2 n( )( ) E2 bi n( )( )– 1

2---

12---

2– 1

4---= = =

Var ei n( )( ) Var ∆i bi n( )⋅( ) ∆i2 Var bi n( )( )⋅

∆i2

4------= = =

Cov ei n( ) e j n( ),( ) ∆i ∆ j Cov bi b j,( )⋅ ⋅=

Pe

Pe Var ei n( )( )i 0=

N 1–

∑=


32

, (3.31)

where is a number calculated according to

.(3.32)

If we assume that the term is dominating (which is true for rea-sonable values of and , e.g., and ), we can approximatewith

. (3.33)

For a full-scale sinusoid, with , the signal power is given by

(3.34)

and the power of the quantization noise is [7, 9]

. (3.35)

Assuming that the quantization noise is uncorrelated with yields the follow-ing expression for the SNDR

. (3.36)

For larger (3.36) can be approximated with

. (3.37)

In [20] there is an analysis of SFDR due to graded matching errors utilizing aFourier series expansion of an approximated error signal to estimate the power ofthe spurious tones. The resulting expression was given as

. (3.38)

To check the validity of (3.37) and (3.38) we have performed some simulations inMatlab. A 14-bit DAC architecture has been used in the simulation and hasbeen chosen to 7. A full-scale sinusoidal input was used, and matching errors

Pe

4 M 2+( )– T ky2⋅⋅

105-------------------------------------=

T

T 70 2M N+⋅ 20 23M N+⋅ 23 4N+ 35 4M⋅– 28 42M⋅– 35 4N⋅–+ +=

23 4N+ 8 24N⋅=N M N 14= M 6= Pe

Pe8 24N⋅

16 105 22M⋅⋅--------------------------------- ky⋅≈ 24N

210 22M⋅----------------------- ky

2⋅=

a ωt( )sin⋅ a 2N 1–≈

Psa2

2----- 22N 2–

2--------------- 22N

8--------= = =

PQ112------=

e n( )

SNDRPs

Pe PQ+------------------- 105 2⋅ 2 N M+( )

4 24N ky2⋅⋅ 70 22M⋅+

----------------------------------------------------= =

ky

SNDR 14 6M 6N– 20 kylog–+≈ dB

SFDR 21.6 6 M N–( )⋅ 20 kylog dB–+=

M


33

were added to the bit weights according to (3.21) and (3.22). Simulated signalspectra for and are plotted in Fig. 3.16(a) and (b), respec-tively. In Fig. 3.16(c) we show simulated and calculated (using (3.36)) values ofSNDR vs. . The corresponding plots for SFDR, with the calculated valuesgiven by (3.1), are shown in Fig. 3.5(d). In this example we conclude that simu-lated and calculated values agree well, e.g., the simulated and calculated SNDRhas a maximum deviation of less than 2.5 dB even if rough approximations aremade. In [20] there was an extended analysis taking into account the correlationbetween the input bits and , reducing the maximum deviationbetween the curves to approximately 0.1 dB.

(a) (b)

(c) (d)

Figure 3.5 Simulated signal spectra of 14-bit DAC with for (a) and (b). The plots in (c) and (d) show simulated (dashed) and calculated

(solid) values of SNDR and SFDR vs. .

ky 10 4–= ky 10 3–=

ky

bN 1– bN 2–

0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

Normalized frequency

PS

D [d

B]

Output signal spectrum, ky=10−5

0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0


PS

D [d

B]

Output signal spectrum, ky=10−4

10−7

10−6

10−5

10−4

10−3

10−2

10

20

30

40

50

60

70

80

90

ky

SN

DR

[dB

]

SNDR vs. ky

simulatedcalculated

10−7

10−6

10−5

10−4

10−3

10−2

10

20

30

40

50

60

70

80

90

100

110

120

ky

SF

DR

[dB

]

SFDR vs. ky

simulatedcalculated

M 7= ky 10 4–=ky 10 3–=

ky


34

Modeling of random matching errors

Special layout techniques are often used to reduce or eliminate the influence ofgraded element matching errors, e.g., distributed biasing discussed in Sec. 4.1.2.However, if this is done, random parameter variations, which can be modeled asspatial white noise [15] and correspond to the first term in (3.13) still remain.Unit current sources with random matching errors are often modeled as

, (3.39)

where is an observation of a stochastic variable with zero mean and Gaus-sian distribution [15, 24]

, (3.40)

where the different are mutually uncorrelated. This way of modeling match-ing errors will be used in Chapter 4 to analyze some methods for error compensa-tion.

3.3.2 Finite output resistance

The ideal current source has infinite output resistance, i.e., the output current isindependent on the voltage across the current source. When implementing cur-rent sources in, e.g., MOS or bipolar technologies, the output resistance is finite.We now examine what influence the finite output resistance will have on thetransfer characteristics of the DAC. The results presented here have previouslybeen presented by Wikner in [25], and are not original parts of this work. It isincluded here because it provides a good starting point for the modeling of finiteoutput impedance, including capacitive parts, in Sec. 3.4.

Assume that we have unit current sources with finite output resistance, . Forinput code there are unit current sources connected in parallel to the outputnode. The equivalent circuit model for the DAC is shown in Fig. 3.6.

Figure 3.6 Equivalent model of current-steering DAC with current sources having finiteoutput resistance.

Iunit j, Iunit δ j+=

δ j ∆ j

∆ j N 0 σ,( )∈

∆ j

RunitX X

IunitX

RL

Runit/X

Vout(X)

VDD

Modeling of dynamic errors

35

The output voltage of the circuit in Fig. 3.6 is

, (3.41)

which clearly is a nonlinear function of . Thus, the finite output resistance inthe current sources introduces nonlinear behavior, and we can conclude that isimportant to have high output resistance compared with the load resistance to gethigh linearity. Equation (3.41) can be used to find design criteria for the outputresistance of the current sources [26].

3.4 Modeling of dynamic errors

Modeling of different sources of dynamic errors is discussed in this section. Theerror focused on in this work is the error caused by the nonzero output capaci-tance of current sources. Nonlinear behavior due to parasitic capacitance is aknown phenomenon [27]. The work presented in this section contributes withtwo different behavioral-level models that have been developed by the author,one of which is closer to a circuit-level model.

3.4.1 State-space model of a current-steering DAC

The finite output resistance of the current sources was mentioned as a limitationof the DAC performance in Sec. 3.3.2. In this section we present a model of theDAC which also includes parasitic capacitance in the current sources and thewires. The system of differential equations describing the DAC during an updateperiod is expressed on a state-space form. A numerical computation program,e.g., Matlab, can then be used to calculate the final values of the different volt-ages in the circuit, i.e., the values of the voltages at the end of the update period.The model presented in this section was first introduced in [28].

Modeling of nonideal DAC components

The ideal current source shown in Fig. 3.7(a) has infinite output impedance. Asingle transistor and a single cascode version of a PMOS current source areshown in Fig. 3.7(b) and (c), respectively. The cascode transistor increases theoutput resistance (see Sec. 5.2.1), but the source still has finite output impedance,as indicated in the linearized model of a current source in Fig. 3.7(d).

Results from simulations of the output impedance of a single transistor currentsource and a single cascode current source [7] are shown in Fig. 3.8. The simula-tion used PMOS transistor parameters for a CMOS process.

V out X( ) Iunit

V DD

Runit-----------+

X

1RL

Runit----------- X⋅+

-----------------------------⋅ RL⋅=

X

0.35 µm


36

for the source transistor and the corresponding ratiofor the cascode transistor is . The current is .We can see that the output resistance (i.e., output impedance at low frequencies)of the cascode current source is higher than for the single transistor currentsource. For higher frequencies the capacitive part of the output impedancebecomes dominating, and for the frequencies where the output impedance forboth types of current sources is essentially capacitive, they both have the sameoutput impedance. This is true provided that all transistors are equally wide,since the output capacitance is more or less the parallel connection of an overlapcapacitance and a junction capacitance, which are both depending on the transis-tor widths [14]. For the cascode current source it is the parasitic capacitance inthe cascode transistor that dominate. More information on the implementation ofcurrent sources is given in Chapter 5.

Use of differential signal paths is an efficient way of rejecting noise and distor-tion, e.g., substrate noise or channel charge injection, provided that the two pathsare symmetrically designed [8]. Therefore, differential current switches are com-monly used and they are implemented with two or more MOS transistors in par-allel, as shown in Fig. 3.9(a). In this work the switch is represented by the MOS

(a) (b)

(c) (d)

Figure 3.7 (a) Ideal current source, (b) single transistor PMOS implementation of a currentsource, (c) single cascode PMOS implementation of a current source, and (d)linearized model of the nonideal current source.

IoutIout

Vbias

Iout

source transistor

cascode transistor

Vbias

Vcasc Iout

Rout Cout

I

Vout

W L⁄ 2 µm( ) 10 µm( )⁄=W L⁄ 2 µm( ) 1 µm( )⁄= 1.22 µA


37

switch-on resistance, as shown in Fig. 3.9(b), assuming that the switch transistoroperates in the linear region. This is a simplification, because the voltage over theswitch is varying with the output voltage of the DAC, and for some configura-tions the switch transistor may even enter the saturated region. Thus, the linear-ized model of the switch is a coarse approximation. However, it is good enoughto illustrate the effect of finite output impedance in the current sources. There isalso parasitic capacitance in the switch, but it is lumped into the parasitics of thecurrent source and output wire.

Figure 3.8 Output impedance vs. frequency for (a) a single transistor current source, and(b) a single cascode current source.

(a) (b)

Figure 3.9 (a) Example of a differential PMOS switch and (b) linearized model of the dif-ferential switch.

102

103

104

105

106

107

108

106

107

108

109

1010

|Zout

(f)| for single transistor (solid) and single cascode (dashed)

Frequency [Hz]

Out

put i

mpe

danc

e [Ω

]

Iin

Iout+ Iout–

Q–Q+

Iin

Iout+ Iout–

Rswitch


38

The output wires of the DAC should have zero impedance to reduce the internalvoltage drop. In reality, the wires contain resistive as well as capacitive andinductive parts [29]. For high accuracy, a transmission line model or an RC-lad-der network should be used as a model for the wire. However, we want to achieveshort simulation times, so a small number of circuit nodes is desired. Therefore,we trade accuracy for a lower degree of complexity in the model. As an approxi-mation we use a resistor and capacitor in parallel, i.e., a simple RC-ladder, asshown in Fig. 3.10. The impedance includes the internal wire impedance as wellas the off-chip load.

Circuit-level model of the DAC

The model of the complete current steering DAC is found by replacing the com-ponents of the ideal DAC in Fig. 3.1 with their nonideal counterparts presented inthe previous section. This yields the schematic in Fig. 3.11.

To simplify further analysis, we first examine the current-voltage relationship forthe model of the current source in Fig. 3.7(d). We have

(3.42)

where

. (3.43)

Figure 3.10 Model of the output wire load.

Iout t( ) IV DD V out t( )–( )

Rout------------------------------------- Cout t∂

∂V out t( )⋅–+= =

IV out t( )

Rout----------------– Cout t∂

∂V out t( )⋅–=

I IV DD

Rout----------+=


39

Hence, the linearized model of a unit current source is equivalent to the circuit inFig. 3.12, where the current is replaced with the slightly larger currentand the output impedance connected to ground instead of . This is the modelwe will use from now on to eliminate terms including from the calculations.

Assume that we during an update period have a value of the digital input, , suchthat of the current sources are connected to one of the analog outputs. For sim-ple notation we let these current sources, , have indices . Thecircuit schematic for this specific configuration shown in Fig. 3.13.

The following relations between voltages and currents hold for this circuit

Figure 3.11 Circuit schematic of the model of the nonideal differential current-steeringDAC.

Figure 3.12 Equivalent circuit of current source.

I0 R0 C0

Rs0

Ij Rj Cj

Rsj

IN1RN1

CN1

RSN1

VDD

Iunit Iunit

V DDV DD

Iunit

output impedance

XK

I j j 1 2 … K, , ,=


40

for , (3.44)

for , (3.45)

, (3.46)

and

. (3.47)

Combining (3.44) and (3.45) yields

. (3.48)

In a similar way, combining (3.45), (3.46), and (3.47) yields

. (3.49)

Figure 3.13 Circuit schematic of one output during an update period for a certain value ofthe input .

I1

R1 C1Rs1

Iout1

V1

IK

RK CKRsK

IoutK

VK

I

R C

V

X

Ioutj t( ) I j

V j t( )

R j-----------– C j t∂

∂V i t( )⋅–= j 1 2 … K, , ,=

Ioutj t( )V j t( ) V t( )–

Rsj---------------------------= j 1 2 … K, , ,=

I t( ) V t( )R

---------=

I t( ) Ioutj t( )j 1=

K

∑ Ct∂

∂V t( )⋅–=

t∂∂

V i t( )1

C j------ I j V j t( ) 1

R j----- 1

Rsj-------+

⋅– V t( )1

Rsj-------⋅+⋅=

t∂∂

V t( )1C----

V j t( )

Rsj-----------

j 1=

K

∑ V t( ) 1R--- 1

Rsj-------

j 1=

K

∑+

⋅–⋅=


41

We let denote the update period of the DAC. We are interested in finding thevalues of the different nodal voltages at the end of the update period. For this pur-pose we define the voltage vector

. (3.50)

For simplicity we let the update period start at time . We further define thestate vector

, (3.51)

where contains the initial voltages, i.e., the voltages just before the switch-ing occurs. The state vector should not be confused with the input . Using(3.48)-(3.51) we can now express the system of differential equations for theDAC as

, (3.52)

where

(3.53)

and

T

V t( ) V 1 t( ) V 2 t( ) … V K t( ) V t( ), , , ,[ ]T=

t 0=

X t( ) V t( ) V 0–( )–=

V 0–( )X X

t∂∂ V t( )

t∂∂ X t( ) A X t( )⋅ B u t( )⋅+= =

A

1R1------ 1

Rs1--------+

1C1------ 0 … 0

1Rs1-------- 1

C1------

0 1R2------ 1

Rs2--------+

1C2------ … 0

1Rs2-------- 1

C2------

… … … … …

0 0 … 1RK------- 1

RsK--------+

1CK------- 1

RsK-------- 1

CK-------

1Rs1-------- 1

C---- 1

Rs2-------- 1

C---- … 1

RsK-------- 1

C---- 1

R--- 1

Rsj-------

j 1=

K

∑+ 1

C----–

=


42

. (3.54)

is a unit step used to apply the initial conditions given in at time . Asimple manipulation of (3.51) yields

. (3.55)

Equations (3.52)-(3.55) form a state-space representation of a linear system withinput and output [30, 31]. Hence, the nodal voltages in the DAC circuitare given as the step response of a linear system on a state-space form. This kindof system can easily be simulated with, e.g., Matlab or another numerical compu-tation tool.

The following algorithm is used for simulation of the model.

1. For a given value of the input, , find the appropriate matrix representingone of the output terminals.

2. Use the final voltages from the last update period as initial values to calculatethe vector . (Reasonable initial voltages are assigned for the first updateperiod.)

3. Calculate/simulate the final value of , e.g., with a numerical computationtool like Matlab.

4. Repeat steps 1 through 3 for the other output terminal.

In this way we calculate the final values of all the nodal voltages in the circuit,which reenter as initial values for one or the other output terminal in the nextupdate period. The outputs from the DAC, and , are given as the out-put node voltage at the end of each update period, i.e., . If current is pre-ferred as output, each output voltage is divided by the corresponding loadresistance.

Simulations

In this section we present simulation results to illustrate the effect of the nonidealcomponents introduced in the model. We consider a 14-bit binary weightedarchitecture. The parameters used in the simulations are given in Table 3.1.

Fig. 3.14(a) and (b) show simulated PSD plots for single-ended and differentialoutputs, respectively. The input is a full-scale, single-tone signal with signal fre-quency and update frequency .

Fig. 3.15 show the simulated PSD plots when the signal frequency is reduced to, i.e., one tenth of the signal frequency used in Fig. 3.14. Com-

paring the two figures we find that the harmonic distortion is largely reduced

B A V 0–( )⋅I1

C1------

I2

C2------ …

IK

CK------- 0, , , ,

T

+=

u t( ) B t 0=

Y t( ) V t( ) X t( ) V 0–( )+= =

u t( ) Y t( )

X A

B

V t( )

V + n( ) V – n( )V nT( )

f sig 1.104 MHz= f u 10 MHz=

f 110.4 kHz=


43

when the signal frequency is lowered. For the differential case the SFDR (deter-mined by the third harmonic) is increased from 70 to 87 dB. We can also see thatthe even order harmonics that appear in the single-ended spectra (the (b) figures)are efficiently cancelled in the differential case.

In Fig. 3.16 we show how SFDR varies with signal frequency for a half-scale sin-gle-tone signal with update frequency . This behavior is typicalfor current-steering DACs [10, 32, 33], compare, e.g., with the measurementresults presented in Chapter 5.

Parameter Value

Unit current

Output resistance, unit current source

Output capacitance, unit current source

Switch resistance,

,

Load resistance

Load capacitance

Table 3.1 Model parameter values used in the simulations.

(a) (b)

Figure 3.14 Simulated (a) single-ended and (b) differential outputs for a full-scale single-tone input with 10 MHz update frequency and 1.104 MHz signal frequency.

1.22 µA

1 GΩ

5 fF

100 Ω j 0 … 7, ,=

100 27 j– Ω⋅ j 8 … 13, ,=

70 Ω

200 pF

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for single−ended output signal

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for differential output signal

Frequency [Hz]

PS

D [d

B/H

z]

f s 10 MHz=


44

3.4.2 A low-complexity model

In this section we present a model with much lower computational complexitythan the state-space model in the previous section. One use of a model with lowcomputational complexity is that it can be implemented on-chip, to a relativelylow hardware cost, and used for error estimation in error compensation tech-niques. Examples on such techniques are presented in Chapter 4.

(a) (b)

Figure 3.15 Simulated (a) single-ended and (b) differential outputs for a full-scale single-tone input with 10 MHz update frequency and 110.4 kHz signal frequency.

(a) (b)

Figure 3.16 Simulated SFDR as a function of signal frequency for (a) single-ended outputand (b) differential output. The update frequency is 10 MHz, and the signal is afull-scale single-tone signal.

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for single−ended output signal

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for differential output signal

Frequency [Hz]

PS

D [d

B/H

z]

105

106

55

60

65

70

SFDR vs fsig

, single−ended output

Frequency [Hz]

SF

DR

[dB

]

105

106

70

75

80

85

90

SFDR vs fsig

, differential output

Frequency [Hz]

SF

DR

[dB

]


45

A simple DAC model

The nonlinear behavior in the models presented in Sec. 3.3.2 and Sec. 3.4.1, iscaused by a signal dependent parasitic network connected to the internal nodes ofthe DAC. Consider the simplified case when this parasitic network is reduced to asingle signal dependent capacitor connected to the output node, as illustrated inFig. 3.17.

This is a single pole system with the output voltage, , given by

, (3.56)

where is the output current for the input code , nominally , andis the signal dependent parasitic load. In discrete time we are interested in thevalue of the output at multiples of the update period , i.e.,

, (3.57)

where has been chosen as . From (3.57) it can be seen that isdepending on , which in turn is dependent on , etc. Thus, thenonlinearity is dynamic and has infinite memory. We can however define a staticparameter describing the error, namely the relative step error

(3.58)

where is the settled output value for input code , for the sim-ple model in Fig. 3.17. Combining (3.57) and (3.58) yields

Figure 3.17 DAC model with signal dependent capacitive load.

R CX

IX

V(t)

V t( )

V t( ) V t0( ) I X R⋅ V t0( )–( ) 1 e

t t0–

RCX------------–

–

⋅+=

I X X Iunit X⋅ CX

T

Y n( ) V nT( ) Y n 1–( ) I X R⋅ Y n 1–( )–( ) 1 eT

RCX-----------–

–

+= =

t0 n 1–( )T Y n( )Y n 1–( ) Y n 2–( )

erel X( ) 1 Y n( ) Y n 1–( )–Y X Y n 1–( )–

------------------------------------–=

Y X X Y X I X R⋅=


46

(3.59)

for the simple model in Fig. 3.17. This expression can be interpreted as that theDAC has a signal dependent settling time constant .

Model structure

Based on the simple model in the previous section, we propose a low-complexitymodel to be used for estimation of the output in a current-steering DAC with non-zero output capacitance in the current sources, as discussed in Sec. 3.4.1. We startby normalizing the output such that

, (3.60)

i.e., we let the static gain of the DAC be unity. We rewrite (3.57)-(3.59) yielding

, (3.61)

which is the first approach to the low-complexity model. A block diagram of acircuit that calculates (3.61) is shown in Fig. 3.18. The relative step error is storedin a lookup table. If can be well approximated with a piece wise constantfunction, the lookup table can be addressed by a few MSBs of (instead of allbits), and the size of the lookup table can be reduced.

The state-space model presented in Sec. 3.4.1 is used as a reference to investigateif the model given by (3.61) is reasonable. The model parameters given inTable 3.1 on page 43 is used in a simulation, and the input is a white noise signalwith rectangular distribution where all input codes are equally probable. Thelength of the signal is samples. In Fig. 3.19(a) we plot observations of

(3.62)

Figure 3.18 Proposed model.

erel X( ) eT

RCX-----------–

=

τX RCX=

Y X X=

Y n( ) Y n 1–( ) Y X n( ) Y n 1–( )–[ ] 1 erel X n( )( )–[ ]⋅+= =

Y n 1–( ) X n( ) Y n 1–( )–[ ] 1 erel X n( )( )–[ ]⋅+=

erel X( )X

lookuptable

z1

X(n) erel(n) Y(n)

216

erel X n( )( ) 1 Y n( ) Y n 1–( )–Y X n( ) Y n 1–( )–-------------------------------------–=


47

as a function of . In (3.62) we use instead of in the denominator,because the finite output resistance yields a nonlinear static transfer function ofthe model, and by (3.58), is a measure of the deviation from this static trans-fer curve. However, for estimation of errors at frequencies, where the dynamicerrors dominate, it is sufficient to assume that the static transfer characteristic islinear. A large spread in can be observed in Fig. 3.19(a). This is because it isnot only the value of the capacitive load that determines the step error, but alsothe initial values of the voltages across the capacitances. These initial values areroughly determined by , so a natural modification of the model is toassume that is a function of and . In Fig. 3.19(b) we plot theobserved values of together with estimated values. The estimations havebeen made using 5 MSBs of and 3 MSBs of . The estimated valueshave been taken as the mean value of all observations having the same value ofthe 5 MSBs of and the 3 MSBs of . Each of the lines inFig. 3.19(b) represents a specific value of quantized to 3 bits. From theplot in Fig. 3.19(b) we conclude that it is reasonable that a better estimation of

is found if is used together with than if is used alone.

The modified approach is given by

. (3.63)

A block diagram of a circuit that calculates (3.63) is shown in Fig. 3.20. Againwe have set the static gain of the DAC to unity, replacing with in (3.63).The lookup table may be addressed by only a few MSBs of and tokeep the size of the lookup table small, as discussed above.

(a) (b)

Figure 3.19 The relative step error, , plotted as a function of the input code (a) with-out and (b) with the estimated values using the low-complexity model.

X n( ) Y X n( ) X n( )

erel

erel

X n 1–( )erel X n( ) X n 1–( )

erelX n( ) X n 1–( )

X n( ) X n 1–( )X n 1–( )

erel X n 1–( ) X n( ) X n( )

0 2000 4000 6000 8000 10000 12000 14000 16000−5

0

5

10x 10

−3 erel

vs X

Input code

Rel

ativ

e er

ror

0 2000 4000 6000 8000 10000 12000 14000 16000−5

0

5

10x 10

−3 erel

vs X

Input code

Rel

ativ

e er

ror

erel X

Y n( ) Y n 1–( ) Y X n( ) Y n 1–( )–[ ] 1 erel X n( ) X n 1–( ),( )–[ ]⋅+=

Y X XX n( ) X n 1–( )


48

Simulation of the low-complexity model

Simulation plots from the model type in Fig. 3.20 are shown in Fig. 3.21. Theparameters in the lookup table have been extracted from the model presented inSec. 3.4.1 using the parameters given in Table 3.1 on page 43. 5 MSBs from

and 5 MSBs from have been used for estimation of . Thespectra in Fig. 3.21 correspond to the spectra in Fig. 3.14, and there is a goodagreement between the simulation results from the two different models. Animportant difference is that the simulation time is reduced to approximately atenth using the low-complexity model. Moreover, solving the state-space equa-tions is a complex task and is not suitable for simple on-chip estimation of errors,whereas the solutions in Fig. 3.18 and Fig. 3.20 require relatively little hardwareprovided that the lookup tables are reasonably small.

The agreement between simulation results from the state-space model and thelow-complexity model is further illustrated in Fig. 3.22. Simulated SFDR as afunction of the signal frequency for the differential output of the low-complexitymodel using a 10 MHz update frequency is shown Fig. 3.22(a). The correspond-ing plot for the state-space model is shown in Fig. 3.22(b), and a good agreementbetween the two plots can be observed.

3.5 Combined models

In previous sections of this chapter we have isolated a nonideal property of a cur-rent-steering DAC, and discussed the impact of that property on the performanceof the DAC. In reality, all these nonideal properties are present at the same time.To get more realistic simulation results, the models should be combined and sim-ulated together. Such combined modeling was used to simulate the behavior of acurrent-steering dynamic element matching (DEM) DAC [34, 35]. The resultsfrom this work is presented in Sec. 5.6.2. The comparisons between simulationsand measurements presented there provide a validation of the state-space modelin Sec. 3.4.1.

Figure 3.20 Block diagram for the modified approach.

lookuptable

z1

X(n)erel(n) Y(n)z1

X n( ) X n 1–( ) erel

Combined models

49

(a) (b)

Figure 3.21 (a) Single-ended and (b) differential outputs for a full-scale single-tone inputwith 10 MHz update frequency and 110.4 kHz signal frequency simulated withthe low-complexity model.

(a) (b)

Figure 3.22 Simulated SFDR as a function of signal frequency for differential output signalswith full-scale amplitude. The plot in (a) shows the results for the low-complex-ity model, whereas (b) shows the results for the state-space model for compari-son.

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

Single−ended PSD for low−complexity model

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

Differential PSD for low−complexity model

Frequency [Hz]

PS

D [d

B/H

z]

105

106

70

75

80

85

90

SFDR vs fsig


Frequency [Hz]

SF

DR

[dB

]

105

106

70

75

80

85

90

SFDR vs fsig


Frequency [Hz]

SF

DR

[dB

]


50

51

4 Compensation andCorrection of Errors

It can be hard to meet a DAC design specification using a straightforward imple-mentation. In this chapter we present some ideas on how to compensate for theerrors, in order to improve the linearity of the circuits. So called predistortion is afamily of techniques widely used in telecommunication circuits, mostly RFpower amplifiers, to enhance the linearity and, thereby, improve the quality of thecommunication link. The idea is to use models of the nonlinearity and modify theinput signal in order to get the desired output signal. Other techniques, e.g.,dynamic element matching (DEM), rely on randomization in order to change thespectral properties of the nonlinearities from spurious tones to (white or shaped)noise.

The presentation of the different techniques given in this chapter has beendivided into two main groups, compensation and correction of static errors,which is presented in Sec. 4.1, and compensation and correction of dynamicerrors, which is presented in Sec. 4.2.

4.1 Compensation and correction of static errors

In this section we discuss compensation of static errors in DACs caused bymatching errors in the current sources. In Sec. 4.1.1 and Sec. 4.1.2 we discussmethods aiming for reduction of the matching errors between the different cur-rent sources using calibration and careful design styles. In the DEM methods pre-sented in Sec. 4.1.3, special randomization techniques make it possible to alterthe spectral properties of the errors in a favorable way.

Compensation and Correction of Errors

52

4.1.1 Calibration of the MSBs

One way of reducing the distortion caused by inadequate matching is to calibratethe current sources, in order to get output currents closer to the nominal currentsthan would be the case without calibration. A method for calibrating the mostsignificant current sources in a binary weighted DAC is proposed in this section.

Basic idea

The idea behind the proposed calibration method is to remove the DNL error inthe transition from to . This error isoften the dominating one in binary coded DACs due to the large amount ofswitches turning on and off. To achieve this, the MSB current, , is substi-tuted with a current

, (4.1)

with the intention of using the currents from the less significant bits and one addi-tional unit current source as reference for the calibration. The DNL and INL for a12-bit binary coded DAC with random matching errors having a standard devia-tion of 1% are shown in Fig. 4.1 and Fig. 4.2, respectively. Values without cali-bration are given in the (a) figures, whereas values with calibration are given inthe (b) figures. In Fig. 4.2(a) we can observe a problem with the binary weightedarchitecture in that its transfer characteristics is not always monotone. In thiscase,

. (4.2)

It is therefore common to use thermometer coded or segmented architecturesinstead, which is further discussed in Sec. 5.3.1.

PSD plots of full-scale single-tone signals without and with calibration are shownin Fig. 4.3(a) and (b), respectively. For this particular stochastic outcome, theSFDR is improved from 66 dB to 80 dB when calibration is applied. It can beconcluded that the proposed calibration method improves the static linearity ofthe binary weighted DAC for this particular case. The proposed method can eas-ily be extended to calibrating more bits than one [36], starting with the least sig-nificant of the bits to be calibrated, proceeding with the next bit until the mostsignificant bit has been calibrated.

X 0 1 1 … 1, , , ,[ ]= X 1 0 0 … 0, , , ,[ ]=

IN 1–

IN 1– Iunit I j

j 0=

N 2–

∑+=

IN 1– I j

j 0=

N 2–

∑<

Compensation and correction of static errors

53

(a) (b)

Figure 4.1 DNL for binary weighted DAC (a) without and (b) with calibration of the MSB.

(a) (b)

Figure 4.2 INL for binary weighted DAC (a) without and (b) with calibration of the MSB.

(a) (b)

Figure 4.3 PSD plot for full-scale single-tone signals (a) without and (b) with calibration ofthe MSBs.

0 500 1000 1500 2000 2500 3000 3500 4000−4

−3.5

−3

−2.5

−2

−1.5

−1

−0.5

0

0.5

1DNL curve, uncalibrated DAC

Input code

DN

L

0 500 1000 1500 2000 2500 3000 3500 4000−4

−3.5

−3

−2.5

−2

−1.5

−1

−0.5

0

0.5

1DNL curve, calibrated DAC

Input code

DN

L

0 500 1000 1500 2000 2500 3000 3500 4000−3

−2

−1

0

1

2

3INL curve, uncalibrated DAC

Input code

INL

0 500 1000 1500 2000 2500 3000 3500 4000−3

−2

−1

0

1

2

3INL curve, calibrated DAC

Input code

INL

0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

Output spectrum, uncalibrated DAC


PS

D [d

B]

0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

Output spectrum, uncalibrated DAC


PS

D [d

B]


54

Proposed implementation

A proposed circuit for the calibration technique is shown in Fig. 4.4. The calibra-tion phase is shown in Fig. 4.4(a). A current mirror is utilized to construct the dif-ference , and a current memory is set to hold the current

. During the operation phase, shown in Fig. 4.4(b), the current memory isutilized to subtract the current from , yielding the total output cur-rent .

(a)

(b)

Figure 4.4 Proposed circuit solution for the calibration technique during (a) the calibrationphase and (b) the operation phase.

∆IN 1– IN 1– IN 1––=∆IN 1–

∆IN 1– IN 1–IN 1–

IN1 IN2 I0 Iunit

DIN1

current memorycurrentmirror

DIN1

IN1 IN2 I0


55

Qualitative comparison with other calibration techniques

In other calibration techniques [32], a capacitor is used to hold the proper gatepotential for the current source. Charge leakage in that capacitor causes adecrease in the output current over time, so periodical recalibration of the currentsources are required.

Charge leakage also causes the current in the current memory, used in the pro-posed technique, to decrease. However, if the current sources are carefullydesigned, so the matching errors are small, the current will also be small.Hence, even if charge leakage resets the current memory, yielding the total outputcurrent instead of , the performance of the DAC is not as severelydeteriorated as is the case when the complete output current is stored in a currentmemory. A similar idea is used in [37], where a static DC current source is set todeliver approximately 90% of the nominal current, and a current memory is usedfor fine tuning the remaining part.

4.1.2 Distributed biasing

The impact of graded element matching errors was discussed in Sec. 3.3.1. Onetechnique that can be used to reduce the effect of graded errors is distributed bias-ing [21, 38]. This design technique is used in the DAC presented in Sec. 5.7 toobtain good matching properties.

A multiple-output PMOS current mirror is shown in Fig. 4.5. If we neglect theinfluence of channel-length modulation (i.e., let the output transistors have infi-nite output resistance), we have that

(4.3)

provided that the output transistors are operating in the saturated region and thatthe transistors are perfectly matched. The transistors have the same length.denotes the width of the output transistors and is the width of the input tran-sistor. In the following we discuss how current mirrors can be utilized for biasingcurrent sources and how the matching properties are affected.

In Fig. 4.6(a) we show an example where the current-source array is made up ofthe output transistors of a single multiple-output current mirror. Graded parame-ter variations, discussed in Sec. 3.3.1, cause the output currents from the differentcurrent sources to vary over the array. The matching of output currents can beimproved by partitioning the array of current sources into smaller parts, lettingeach such part be an individual multiple-output current mirror, as indicated inFig. 4.6(b). This is because the bias voltage ( in Fig. 4.5) is set individually for

∆i

IN 1– IN 1–

Iout j,W out

W in----------- I in⋅=

W outW in

V b


56

each current mirror. If the input transistors are located close to the output transis-tors, the bias voltage is set to give the proper output current for the values of tran-sistor parameters in the proximity of the input transistors, reducing the currentvariations over the array due to graded parameter mismatch, compared with theapproach in Fig. 4.6(a). The biasing strategy has no effect on the influence of ran-dom matching errors, so this problem remains.

4.1.3 Dynamic element matching

This section is an overview of dynamic element matching (DEM) techniques.The purpose is to provide a background to DEM, in order to simplify the under-standing of the description of the DEM DAC presented in Sec. 5.6, were mea-surement and simulation results can be found as well.

If the error in the output level, , is determined by the input code, , i.e.,, the same error will occur each time a certain input code, , is

applied. Hence, if the input signal is periodic (which is the case for, e.g., asinusoidal input signal), will also be periodic with the same fundamentalfrequency as the input signal. This results in harmonic distortion, unless the erroris a linear gain error, where is a constant. DEM techniquesutilize randomization to make sure that the input code do not cause the sameerror each time it is applied. Generally, one can say that ,where is a control signal. The control signal may, e.g., be random or a deter-ministic function of the input. In this way, the error signal is changed from yield-ing harmonic distortion to having more noise-like properties.

Some DEM algorithms transform distortion into white noise, whereas the noise-shaping DEM techniques moves a large amount of the noise out of the signalband. These two types of DEM are discussed in this section. There are also DEMtechniques that minimize the number of switching events [39, 40], and hence theglitches. These techniques will not be further discussed here. DEM is especially

Figure 4.5 Multiple output PMOS current mirror.

Iin Iout,1Iout,K

Vb

e Xe n( ) f X n( )( )= X

X n( )e n( )

e n( ) K X n( )⋅= KX

e n( ) f X n( ) r n( ),( )=r n( )


57

suitable in audio applications where the signal bandwidths are low (comparedwith, e.g., DSL applications) and a large amount of oversampling can beafforded.

Generalized DEM

A general DEM DAC is shown in Fig. 4.7. The input, , is converted into athermometer coded signal

. (4.4)

The bits of are scrambled yielding a third code

, (4.5)

such that

(a) (b)

Figure 4.6 Current-source arrays with (a) global and (b) distributed bias.

Ibias

current source array

Ibias,1


Ibias,2

Ibias,K

X1 n( )

X2 n( ) tK n( ) tK 1– n( ) … t2 n( ) t1 n( ), , , ,[ ]=

X2 n( )

X3 n( ) uK n( ) uK 1– n( ) … u2 n( ) u1 n( ), , , ,[ ]=


58

, (4.6)

and for each there is exactly one such that (4.6) holds. Which is mappedon what is determined for each update instant by the control signal .Each is an input to a one bit DAC with nominal gain and an associatedmatching error . The outputs from all one bit DACs are summed, yielding thetotal output

, (4.7)

where the first term in is the desired output, and the second term is the error dueto mismatch. Without scrambling, the error becomes

(4.8)

and harmonic distortion occurs because the resulting error is periodic. This is nottrue in DEM DACs, provided that the control signal is properly chosen. Thescrambling ensures that different errors occurs for the same input code at differ-ent update instants, a property which is used to transform harmonic distortioninto noise. The overall SNDR is improved if oversampling is used, because theout-of-band noise can be filtered out.

A straightforward implementation of the digital circuits required in DEM mayresult in high hardware complexity. There is a large amount of research on DEMcircuit techniques with reduced hardware complexity presented in the literature[41, 42]. Some of these techniques are overviewed in the following sections. Forcomparisons of different networks used for DEM realizations, see, e.g., [43, 44].

DEM utilizing switching trees

One approach to implement DEM uses a tree of switches according to Fig. 4.8.The input to the tree, denoted in Fig. 4.8, is binary coded, so the tree per-forms both the binary-to-thermometer encoding and the scrambling. Each switchlayer, , is controlled by a pseudo random control signal, . Aswitch has one -bit input and two ( )-bit outputs, which we denoteand , that are inputs to the switches in the following layer. If , thenthe bits of the ( )-bit output are given the values of the LSBs of

ui n( ) t j n( )=

j i t j n( )u j n( ) n r n( )

ui n( ) w∆i

Y n( ) w ∆i+( ) ui n( )⋅i 1=

K

∑ w ui n( )i 1=

K

∑⋅ ∆i ui n( )⋅i 1=

K

∑+= = =

w X1 n( )⋅ ∆i ui n( )⋅i 1=

K

∑+=

∆i ti n( )⋅i 1=

K

∑

r n( )

X n( )

i r i n( ) 0 1, ∈M M 1– out1

out2 r i 1=M 1– out1 M 1–


59

the input, whereas the value of the MSB of the input is assigned to all individualbits of . When the MSB of the input is instead mapped on the bits of

, and the LSBs of the input are mapped on . The number of out-put bits for each switch is linearly decreasing with decreasing layer index, andthe tree is terminated with the switching layer having 1-bit outputs. These 1-bitsignals constitute a scrambled, thermometer coded word that is used to control 1-bit DACs, whose outputs are summed yielding the total output for the DEMDAC.

An additional bit with the same weight as the LSB, and fixed value ‘0’, is addedto the binary weighted input to give the LSBs the same total weight as the MSB.This is required because there is an even number of output bits from the switch-ing tree, whereas a thermometer coded word has an odd number of bits. Thisresults in that at least one of the output bits from the tree will have the value ‘0’.

Partial randomization DEM

The tree approach described above is known as full randomization DEM(FRDEM). For DACs with a large number of input bits, the hardware complexityof the FRDEM switching tree becomes large, since the number of outputs fromthe tree grows exponentially with the number of input bits. An approach that hasbeen proposed to trade the hardware complexity for a lower degree of randomiza-tion is the partial randomization DEM (PRDEM) technique. In PRDEM, theswitching tree is terminated before 1-bit outputs are achieved, thus resulting in alower hardware complexity. The outputs from the switches in the last layer areused as inputs to DAC banks consisting of one 1-bit DAC and one multi-bit DAC(the 1-bit DAC in the DAC bank is a required because of the added LSB in the

Figure 4.7 Generalized block diagram of a DEM DAC.

bina

ry-t

o-th

erm

omet

er e

ncod

er

scra

mbl

er1-bit

DACs

X1(

n)

X2(

n)

X3(

n) combinedoutputr(

n)

out2 r i 0=out1 M 1– out2


60

input to the tree). Design, modeling, and measurements of a current-steeringPRDEM DAC is discussed in Sec. 5.6. From the simulations and measurementspresented there we find that randomization in a few layers only is enough formaking the distortion due to mismatch neglectable compared with the dynamicerrors. Hence, terminating the switching tree after a few layers is acceptable.

Mismatch shaping DEM

Using random scrambling has the effect of transforming harmonic distortioncaused by mismatch into (approximate) white noise. Hence, the power of the dis-tortion is evenly distributed over the whole frequency range. To gain even morein SNDR it is desirable to shape the noise, so that a larger portion of the noiseappears outside of the signal band, where it can be filtered out. This is the goalwith so called mismatch shaping DEM [24, 45, 46]. In mismatch shaping DEM,the one bit signals are chosen according to [45]

, (4.9)

where is the number of 1-bit signals and is a signal with very little powerwithin the signal band. The total output is

. (4.10)

Figure 4.8 DEM circuit utilizing switching tree.

switch2

r1(n)

switchN+1

rN(n)switch

N

rN1(n)

switchN

rN1(n)

switch2

r1(n)

NX(n)

0 to 1

-bit

DA

Cs

layer 1

layer N1

layer N

ui n( )

ui n( )1K---- X1 n( )⋅ zi n( )+=

K zi n( )

Y n( )1K---- w ∆i+( ) X1 n( )⋅ ⋅

i 1=

K

∑ 1K---- w ∆i+( ) zi n( )⋅ ⋅

i 1=

K

∑+= =

X1 n( ) w 1 ∆i

i 1=

K

∑+

⋅ w ∆i+( ) zi⋅i 1=

K

∑+⋅=

Compensation and correction of dynamic errors

61

The first term in (4.10) is the desired output (with a slightly different gain com-pared with (4.7)). The second term is the error, , due to mismatch. Moreover

, (4.11)

yielding

. (4.12)

Combining (4.10) and (4.12) yields

. (4.13)

Since every has very little power within the signal band, so does . Theconstruction of the different is similar to delta-sigma modulation (which isoutlined in Sec. 4.2.2) and is nontrivial. Several circuit solutions have been pro-posed (see, e.g., [24, 45, 47, 48]), and there are also solutions where the different

are multi-bit words.

4.2 Compensation and correction of dynamic errors

Techniques on compensation and correction of dynamic errors are presented inthis section. For behavioral-level simulations of the different techniques we useMatlab in combination with the state-space model presented in Sec. 3.4.1. Anarchitecture that utilizes redundant coding of differential signals to increase theflexibility and hence give the possibility for improved linearity is presented inSec. 4.2.1. The techniques described in Sec. 4.2.2 and Sec. 4.2.3 are dependenton models to compute the expected error and the predistorted input, respectively.For this purpose we base our techniques on the low-complexity model describedin Sec. 3.4.2. Here we only consider improvement on the linearity of the single-ended signals. The models need modifications to reduce distortion in the differ-ential signals. The update frequency is 10 MHz In all simulations and measure-ments.

Methods that have been claimed to improve the dynamic behavior, are the use oftrack and hold circuits or deglitcher circuits connected to the DAC outputs[49, 50]. These techniques are not considered in this thesis.

e n( )

X1 n( ) ui n( )i 1=

K

∑ X1 n( ) zi n( )i 1=

K

∑+= =

zi n( )i 1=

K

∑ 0=

e n( ) ∆i zi n( )⋅i 1=

K

∑=

zi e n( )ui n( )

ui n( )


62

4.2.1 Differential DACs with variable common mode

In this section we propose a redundant differential DAC architecture whichallows the common mode level to be varied. This can be used, e.g., to reduce theoverall load at the outputs or to apply a dithering signal [51, 52] to reduce thenonlinear behavior. The ideas presented in this section were introduced in[53, 54, 55].

Proposed redundant architecture

The proposed redundant DAC architecture is shown in Fig. 4.9. It combines twocurrent-steering DACs (DAC1 and DAC2), which may be single-ended or differ-ential. In the latter case we only use output , and connect to a constant DCvoltage, , which in practice is the same as having a single-ended current-steering DAC.

The input, , to DAC1 is

, (4.14)

where is the input to the whole system and is a control signal. Theinput, , to DAC2 is similarly given by

, (4.15)

Figure 4.9 Proposed redundant DAC architecture.

A+ A–V dump

DAC1

A+

A

DAC2

A+

A

r(n)X(n)

X1(n)

X2(n)

Vdump

RL RL

I2 I1

X1 n( )

X1 n( ) X n( ) r n( )+=

X n( ) r n( )X2 n( )

X2 n( ) Xmax X n( )– r n( )+=


63

where is the maximum value of for the given code, i.e., with all individ-ual bits . If the input code is binary weighted, then corre-sponds to with all individual bits inverted, represented by the invertersymbol in Fig. 4.9. The control signal must not cause any of the signals and

to overflow, since this causes distortion. Thus, the DAC inputs need to fulfill

, (4.16)

yielding

. (4.17)

With ideal DACs (DAC1 and DAC2) we obtain the following expressions for theoutput currents

and

. (4.18)

For the combined differential output current, , we obtain

. (4.19)

Hence, ideally we have the same differential output current as for a single idealdifferential current-steering DAC, because the control signals cancel. Of course,in reality the control signal will affect the two outputs differently due to any non-linearity in the transfer functions of the DACs, and the cancellation will not beperfect.

We also consider the common-mode signal

. (4.20)

Hence, the control signal is added to the common-mode signal. One factor thatlimits the possibly useful control signals is, therefore, the common-mode rejec-tion of the following circuitry. Another factor is, as mentioned earlier, how thecontrol signal is distorted between the two DAC outputs.

Xmax Xbi 1= Xmax X n( )–

X n( )X1

X2

0 X i Xmax≤ ≤

r min X Xmax X–,( )–≥

I1 Iu wi bi n( )⋅i 0=

N 1–

∑ Iu r n( )⋅+=

I2 Iu wi bi n( )⋅i 0=

N 1–

∑ Iu r n( )⋅+=

Idiff I1 I2–=

Idiff I1 I2– 2Iu bi wi⋅i 0=

N 1–

∑ Iu wi

i 0=

N 1–

∑–= =

Icm

I1 I2+

2--------------- Iu wi

i 0=

N 1–

∑ Iu r n( )⋅+= =


64

In an implementation, the two DACs have to be mutually well-matched, prefera-bly manufactured on the same die, sharing same master bias, etc. It is also impor-tant to avoid clock skew between the two DACs, and therefore it is desirable thatthey share the same clock net. Obvious penalties, compared with conventionalDACs, are increased area requirements and power consumption. A test chip thatcan be used for evaluation of the ideas discussed here is presented in Sec. 5.7. Atthis point, however, the DACs on this chip have only been measured one at atime, not combined.

Dithering of the common-mode level

A first method of utilizing the redundancy is to apply dithering of the common-mode level to reduce the nonlinear distortion caused by random matching errorsin the current sources. This technique is similar to DEM techniques presentedearlier, and is actually a technique for compensation of static errors. It appears inthis section because the other methods of utilizing the redundant architectureaims at reducing dynamic errors. For simulation purposes, we add a randommatching error with Gaussian distribution, standard deviation ofand expectation value 0 to each unit current source. The simulated DAC architec-ture utilizes segmentation where the 6 MSBs are encoded into thermometer code.The matching errors have not been altered between the runs, i.e., the same DACshave been used in all simulations.

The control signal was chosen to be quantized values of

, (4.21)

where is a scaling constant and is white noise with a rectangular distribu-tion

. (4.22)

The PSD plots of for and are shown in Fig. 4.10(a) and (b),respectively. The input is a single-tone signal with half-scale amplitude. It is seenthat the added dithering signal reduces the spurious tones to a large extent. InFig. 4.11 the SFDR is plotted vs. . We see that the SFDR increases withincreasing . The quantitative results are, obviously, specific for this particularoutcome of the stochastic matching errors.

DC level minimization

We propose a second method based on the proposed redundant architecture inFig. 4.9 that aims at reducing the parasitic load associated with an output termi-nal. Looking at the circuit models presented in Sec. 3.4 we see that each current

σ 0.02 Iu⋅=

r n( )

a ψ n( )⋅

a ψ n( )

ψ n( ) Re 0.5– 0.5,( )∈

Idiff a 0= a 213=

a2loga


65

source connected to a terminal provides an additional load through its outputimpedance. For the best possible dynamic behavior (i.e., short settling times) it isdesired to minimize the load at the output terminal, i.e., minimize the number ofunit current sources connected to the terminal. If the input does not make use ofthe whole range, e.g., a half-scale single-tone signal, this can be achieved by let-ting be a (negative) constant. This is equivalent to reducing the DClevel of each single-ended output.

(a) (b)

Figure 4.10 PSD plots for simulated outputs from redundant DAC with matching errors (a)without dither signal and (b) with dither signal having amplitude .

Figure 4.11 SFDR as a function of .

0 1 2 3 4 5−120

−100

−80

−60

−40

−20

0

PSD plot of DAC output, a = 0

Frequency [MHz]

PS

D [d

B/H

z]

0 1 2 3 4 5−120

−100

−80

−60

−40

−20

0

PSD plot of DAC output, a = 8192

Frequency [MHz]

PS

D [d

B/H

z]

a 213=

4 6 8 10 12 1480

82

84

86

88

90

92

94

96

98

100

SFDR vs. log2(a)

log2(a)

SF

DR

[dB

]

log2 a( )

r n( ) r=


66

Here we present some simulation results using the model presented in Sec. 3.4.1.The simulated DAC is 14-bit binary-weighted, and the model parameters are thesame as in Table 3.1 on page 43. The current sources are assumed to be perfectlymatched, but matching errors can also be added in the model, as discussed inSec. 3.5. PSD plots of the simulated DAC outputs using half-scale sinusoidalinputs are shown in Fig. 4.12. The PSD for a single differential DAC is shown inFig. 4.12(a). PSDs for the proposed redundant architecture, with the dump termi-nal connected to a DC voltage source of 0.5 V, are shown in Fig. 4.12(b) and (c).The PSD for is shown in Fig. 4.12(b) and the PSD for (yieldingthe lowest possible DC level without overflow) is shown in Fig. 4.12(c). A Com-parison of Fig. 4.12(a) and (b) indicates that switching a current source betweenan output node and a silent node has favorable effects on the distortion, comparedwith switching between two output nodes, since the distortion is 5 dB lower inFig. 4.12(b). This also agrees with some single-ended measurements performed.The spurious tones are reduced even more, resulting in an improvement in theSFDR by approximately 7 dB when the DC level is reduced, as is the case inFig. 4.12(c). Further measurements have to be performed before any conclusionscan be made regarding the application to real DAC circuits.

Common-mode level reduction with boundary conditions

Using the approach with a constant is only applicable to a limited class ofsignals, i.e., the ones that do not utilize the possible input range. Moreover, it isrequired that the maximum and minimum value of all future samples of the inputare known. Even if the signal has finitely many samples, the number of samplesis often so large that this is not possible to obtain to a reasonable hardware cost oracceptable delay. Instead we modify the approach and choose as the small-est integer fulfilling the boundary conditions

(4.23)

and

. (4.24)

Boundary condition (4.23) ensures that overflow is avoided, and is chosensuch that the common mode variations can be sufficiently rejected in the follow-ing circuitry. The previous approach with a constant corresponds to

. The boundary conditions should hold for all , so we need to keeptrack of some future samples of , otherwise we risk choosing too small tofulfil both (4.23) and (4.24) for some future sample. However, since we do notneed to keep track of all future samples, which is the case when using a constant

, this approach is more suitable for implementation.

r 0= r 212–=

r n( )

r n( )

r n( ) min X n( ) Xmax X n( )–,( )–≥ rmin n( )=

r n( ) r n 1–( )– ∆rmax≤

∆rmax

r∆rmax 0= n

X r n( )

r


67

In Fig. 4.13(a) and (b) we show simulated 3-tone PSD plots for a single DAC andfor the proposed redundant DAC with chosen as above, respectively. Thesimulation model is a 14-bit binary weighted version of the one presented inSec. 3.4.1. Parameter values are given in Table 3.1 on page 43, and .The peak-to-peak value for this particular input is approximately 10600. Thelargest distortion peak is reduced from –72 to –82 dB.

4.2.2 Modulation of expected errors

Delta-sigma modulation is a technique used in data conversion to achieve high-resolution with quantizers having few quantization levels. This is performedusing the quantization error in a feedback loop, spectrally moving a large amountof the quantization noise power to a frequency range above the signal band. How-

(a)

(b) (c)

Figure 4.12 PSD plots of simulated DAC outputs from (a) a conventional DAC, and the pro-posed redundant DAC with (b) and (c) . The input is a half-scale sinusoid with signal frequency 2.208 MHz and update frequency 10 MHz.

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for output from conventional DAC

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for output signal, r=0

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for output signal, r=−4096

Frequency [Hz]

PS

D [d

B/H

z]

r 0= r 212–=

r n( )

∆rmax 20=


68

ever, an ideal quantizer is a poor model of a real data converter. Reference levelswill not be evenly spaced due to, e.g., component mismatch. Other dynamic andstatic errors also occur, as was discussed in Chapter 3.

In this section we propose a linearization technique based on delta-sigma modu-lation, primarily intended for DACs, which also spectrally shapes nonlinearitiesarising from other sources than the quantization process. The application, how-ever, is not limited to DACs, but can be applied to any kind of oversampled sys-tem. The technique presented here was first proposed in [56].

Delta-sigma modulator basics

The aim for a delta-sigma modulator is to spectrally shape the quantization noise,so that it is moved out of the signal band. This technique implies that oversamp-ling has to be used. A general delta-sigma modulator is shown in Fig. 4.14(a).The feedback filter is assumed to be a linear filter. The quantizer is often modeledwith an error, , added to the quantizer input, as shown in Fig. 4.14(b).

In the frequency domain, the output can be written as

(a) (b)

Figure 4.13 PSD for 3-tone signal (a) without and (b) with common-mode level reduction.

(a) (b)

Figure 4.14 (a) General delta-sigma modulator and (b) delta-sigma modulator with quanti-zer modeled as an added error signal.

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for simulated output signal, r=0

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for simulated output signal, ∆rmax

=10

Frequency [Hz]

PS

D [d

B/H

z]

e n( )

Qfeedback

filter

X(n) Y(n)

feedbackfilter

X(n) Y(n)e(n)


69

(4.25)

where is the signal transfer function, is the noise transfer func-tion, and , , and are the z-transforms of , , and ,respectively.

The modulator structure we use in the following is shown in Fig. 4.15. It isreferred to as an error feedback modulator [8, 57], since the quantization error isused as an input to the filter .

It is easily derived from Fig. 4.15 that

(4.26)

and

. (4.27)

We let be an FIR transfer function, making an FIR filter. We cannow specify , and is implicitly given by (4.27). An orderis chosen by placing poles in the origin and zeros strategically on the unitcircle. This structure is sensitive to coefficient errors [8], and may be difficult toimplement. It is, however, an easy way to design an example for simulations inMatlab, where we can have virtually infinite precision in the coefficients.

Simulation results for a 5th order modulator of this type, using , with asingle-tone input is shown in Fig. 4.16. The input and output spectra are shown inFig. 4.16(a) and (b), respectively. The input has 14 bits of resolution, and a 6-bitquantizer is used. The zeros of the noise transfer function are located on the unitcircle at , , and . The spectrum for theinput signal quantized to 6 bits without the feedback is plotted in Fig. 4.16(c) forcomparison. As for all types of delta-sigma modulators, stability is an importantissue. The stability of delta-sigma modulators with FIR noise transfer functions isdiscussed in [58].

Figure 4.15 Error feedback modulator.

Y z( ) X z( ) STF z( )⋅ E z( ) NTF z( )⋅+=

STF z( ) NTF z( )Y z( ) X z( ) E z( ) Y n( ) X n( ) e n( )

H z( )

Q

H(z)

X(n) Y(n)

e(n)

STF z( ) 1=

NTF z( ) 1 H z( )–=

NTF z( ) H z( )NTF z( ) H z( ) Lth NTF

L L

OSR 4=

z 1= z e j π OSR⁄( )±= z e j π 2 OSR⋅( )⁄( )±=


70

Spectral shaping of nonlinearities

As mentioned earlier, an ideal quantizer is a poor model of a real DAC. In thissection we propose a technique for compensating nonidealities due to physicalimperfections utilizing the basic ideas of delta-sigma modulation. The modulatorspectrally shapes the quantization noise through feedback of the quantizationerror. We want to do the same thing with distortion arising from nonlinearities inthe DAC. Therefore, the quantizer in Fig. 4.15 is substituted with a quantizer cas-caded with an accurate model of the DAC, yielding the block diagram shown inFig. 4.17. We refer to this circuit as the distortion shaper. The output from thequantizer, , is passed on as the input to the real DAC.

This structure can be modeled similarly as the delta-sigma modulator was inFig. 4.14(b), replacing the quantizer and the DAC model with an addition of anerror signal. However, the error signal, , might be considerably larger thanthe quantization error, which is bounded within one LSB of the quantizer. There-

(a)

(b) (c)

Figure 4.16 Spectra for (a) 14-bit single-tone signal, (b) delta-sigma modulated signal using5th order modulator with a 6-bit quantizer, and (c) 6-bit single-tone signal.

0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

14−bit input signal to modulator


PS

D [d

B]

0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

6−bit output signal from modulator


PS

D [d

B]

0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

6−bit single−tone signal


PS

D [d

B]

Y n( )

e n( )


71

fore, a feedback configuration which is guaranteed to be stable according to somecriterion in the delta-sigma modulator case, need not necessarily be stable in thiscase. The stability issue has to be carefully considered for each special case, e.g.,through extensive simulation of the system.

For an implementation of the distortion shaper it is important to have an accuratemodel of the DAC. The best model is of course the DAC itself, meaning that weaccurately measure the error for each update instant, i.e., a fast and accurate ADCis required in the feedback loop. This is not easily achieved, so a better solutionwould be to use an adaptive model of the DAC, which is updated, e.g., during atraining period.

Simulations

A suitable candidate for the model in the feedback loop to compensate for errorsdue to finite output impedance is the low-complexity model presented inSec. 3.4.2. Here some simulation results for linearization of the DAC model inSec. 3.4.1 are presented. The simulation parameters are the same as in Table 3.1on page 43, except that the output resistance in the unit current sources has beenincreased a factor 10 to reduce the static nonlinearity, which is not included in thelow-complexity model. The parameters for the low-complexity model are thesame as those used in the simulations in Sec. 3.4.2. The filter is the same asin the delta-sigma simulation in Fig. 4.16. The method is illustrated in by thesimulation plot in Fig. 4.18 where the dominating second harmonic is suppressedwith 20 dB, to the cost of increased high frequency distortion. There is one spuri-ous tone within the signal band that increases, so the SFDR improvement is only11 dB.

Figure 4.17 Block diagram of the proposed distortion shaping device.

Q

H(z)

X(n)

Y(n) (to DAC)

e(n)

DACmodel

H z( )


72

Measurements

Measured PSD plots for single-ended outputs from the DAC presented inSec. 5.5 are shown in Fig. 4.19. Fig. 4.19(a) shows the spectrum using an uncom-pensated input, whereas the input used in Fig. 4.19(b) has been processed withthe distortion shaping technique presented in this section. The model used forestimation of the error is a simple version of the low-complexity model presentedin Sec. 3.4.2, namely

. (4.28)

Referring to the block diagram of the model shown in Fig. 3.18, the lookup tableonly contains two values, and 0, and is addressed by the MSB of the input tothe DAC. The resulting SFDR improvement is approximately 12 dB, which givesa strong indication that the model structure presented in Sec. 3.4.2 is suitable forits purpose, i.e., to estimate dynamic errors in order to compensate for them.

4.2.3 Predistortion of dynamic errors

The method described in Sec. 4.2.2 reduces the distortion within the signal bandto the cost of increased out-of-band distortion, which requires filtering to removethe out-of-band distortion. The technique is particularly suited to use in a delta-sigma DAC, where filters are required in any case to remove the shaped quantiza-tion noise. For other cases it is better to compute an input that yields an output asclose as possible to the desired output, removing the distortion rather than spec-trally shaping it. By doing so, we also increase the possible signal bandwidth fora given update frequency, compared with if the distortion is shaped. Filters arestill required to remove images of the signal, but the filter requirements are not ashard as if the filters also have to remove the shaped distortion. This technique is

(a) (b)

Figure 4.18 PSD plots for simulated outputs (a) without and (b) with distortion shaping.

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

Output signal wihtout distortion shaped

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

Output signal with distortion shaped

Frequency [Hz]

PS

D [d

B/H

z]

erel X n( )( ) a bN 1– n( )⋅=

a


73

known as predistortion [12]. Methods based on predistortion are often proposedfor improving the linearity in power amplifiers for radio frequency (RF) applica-tions [59, 60, 61]. Very little work has been done in the field of predistortion forDACs. In [62] a method was reported utilizing a black-box model of the DAC.No consideration was, however, taken to the computational complexity of thepredistortion block.

In this section we present a predistortion method for DACs aimed at reducing thenonlinear behavior caused by parasitic capacitance, as discussed in Sec. 3.4. Themethod utilizes the low-complexity model presented in Sec. 3.4.2 to calculate thepredistorted input to the DAC. The method first appeared in [63].

Predistortion block

The purpose of the predistortion block is to, for a given input , find a modi-fied input, , such that . To accomplish this we use the low-com-plexity DAC model presented in Sec. 3.4.2. In accordance with Sec. 3.4.2 we use

(4.29)

as an estimate of the output from the current-steering DAC and normalize theoutput such that the static gain of the DAC is unity. To find the appropriate pre-distorted signal we replace with in (4.29), yielding

.

(4.30)

Further, we set and assume that , i.e., that thepredistortion for the previous sample was successful. This yields

(a) (b)

Figure 4.19 PSD plots for measured outputs from a DAC (a) with and (b) without the distor-tion shaped.

X n( )X p n( ) Y n( ) X n( )≈

Y n( ) Y n 1–( ) X n( ) Y n 1–( )–[ ] 1 erel X n( ) X n 1–( ),( )–[ ]⋅+=

X X p

Y n( ) Y n 1–( ) X p n( ) Y n 1–( )–[ ] 1 erel X p n( ) X p n 1–( ),( )–[ ]⋅+=

Y n( ) X n( )= Y n 1–( ) X n 1–( )=


74

.

(4.31)

Solving for yields

. (4.32)

In Sec. 3.4.2 only a few MSBs of are used to estimate . Thus, if we assumethat the correction introduced by the predistortion is small, i.e., issmall, it is reasonable to approximate with

. We can then make a nonrecursive definition of

, (4.33)

where

. (4.34)

Similarly to the error estimation presented in Sec. 3.4.2, can be stored in alookup table. Further, the lookup table may be addressed with only a few MSBsof and to keep the size of the lookup table small. We propose apredistorter circuit according to Fig. 4.20.

Simulation results

In this section we present results from simulations where the predistortion tech-nique is used to linearize the state-space model of the current-steering DAC pre-sented in Sec. 3.4.1. The simulation parameters are given in Table 3.1 on page43, and the parameters for the predistortion block are the same as in the simula-tions in Sec. 3.4.2.

Figure 4.20 Proposed predistorter circuit.

X n( ) X n 1–( ) X p n( ) X n 1–( )–[ ] 1 erel X p n( ) X p n 1–( ),( )–[ ]⋅+=

X p n( )

X p n( ) X n 1–( ) X n( ) X n 1–( )–1 erel X p n( ) X p n 1–( ),( )–------------------------------------------------------------+=

X erelX p n( ) X n( )–

erel X p n( ) X p n 1–( ),( )erel X n( ) X n 1–( ),( ) X p n( )

X p n( ) X n 1–( ) X n( ) X n 1–( )–1 erel X n( ) X n 1–( ),( )–-------------------------------------------------------+= =

X n 1–( ) prel X n( ) X n 1–( ),( ) X n( ) X n 1–( )–( )⋅+=

prel X n( ) X n 1–( ),( ) 11 erel X n( ) X n 1–( ),( )–-------------------------------------------------------=

prel

X n( ) X n 1–( )

lookuptableX(n)

prel(n) Xp(n)z1


75

The PSD plots for outputs without and with predistorted inputs are shown inFig. 4.21(a) and (b), respectively. The input is a half-scale sinusoid with signalfrequency 1.104 MHz and the update frequency is 10 MHz. Full-scale inputscannot be used since the predistorted inputs are likely to overflow in that case. InFig. 4.22 we have increased the signal frequency to 2.208 MHz. For both fre-quencies it can be concluded that the predistortion reduces the second harmonicto a large extent and suppresses the other harmonics below the noise floor. SFDRis plotted as a function of signal frequency in Fig. 4.23. For this example theSFDR at low frequencies is preserved over the whole frequency range when thepredistortion technique is used.

(a) (b)

Figure 4.21 PSD plots for outputs (a) without and (b) with predistortion. The input is a half-scale sinusoid with signal frequency 1.104 MHz, and the update frequency is10 MHz.

(a) (b)

Figure 4.22 PSD plots for outputs (a) without and (b) with predistortion. The input is a half-scale sinusoid with signal frequency 2.208 MHz, and the update frequency is10 MHz.

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for nonpredistorted input signal

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for predistorted input signal

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for nonpredistorted input signal

Frequency [Hz]

PS

D [d

B/H

z]

0 1 2 3 4 5

x 106

−120

−100

−80

−60

−40

−20

0

PSD for predistorted input signal

Frequency [Hz]

PS

D [d

B/H

z]


76

4.2.4 Implementation issues

Methods for compensating dynamic errors utilizing models of the errors werepresented in Sec. 4.2.2 and Sec. 4.2.3. The hardware complexity for an imple-mentation of the compensation blocks used in the simulations is low, a fewadders and multipliers, and a small lookup table. A problem that needs to besolved, however, is the estimation of model parameters. In simulations this is nota problem, since both the input and the output are accessible (without approxima-tion), and model parameters can be estimated with high precision. To do the samething for an actual circuit, a fast and accurate ADC is required to measure theerror in a wide-band DAC aiming for high resolution. In [62] this problem wasapproached by using a state-of-the-art commercial ADC operating at a limitedpart of the signal band. This solution failed to compensate for any distortion thatappeared outside of this band.

Figure 4.23 Simulated SFDR as a function of signal frequency with and without predistor-tion.

105

106

50

55

60

65

70

75

80

85

90

Simulated SFDR vs. fsig

fsig

[Hz]

SF

DR

[dB

]

without predistortionwith predistortion

77

5 Current-Steering DACImplementations

The most common type of DAC for high-speed applications, e.g., broadbandcommunication, is the current-steering. The implementation of three different 14-bit current-steering DACs in standard digital CMOS processes is discussed in thischapter, together with the measurement results.

5.1 CMOS processes

Complementary metal oxide semiconductor (CMOS) processes are very popularfor implementing integrated circuits, mainly due to low cost, but also becausethey provide good possibilities for designing digital low-power circuits. Thewords “metal oxide semiconductor” refers to the physical structure of the transis-tors, whereas the word “complementary” means that the designer have access toboth NMOS and PMOS transistors. All DACs presented in this chapter have beenimplemented in standard digital CMOS processes. In this section we give anoverview of the CMOS transistor.

5.1.1 Large signal models

The large signal behavior of the CMOS transistor in different operation regions isbriefly discussed in this section. Well known equations for the current-voltagerelationships, assuming long channel devices, are also presented.

Current-Steering DAC Implementations

78

NMOS transistors

A commonly used symbol for an NMOS transistor is shown in Fig. 5.1(a). Thelabels G, S, D, and B denote the gate, source, drain, and bulk terminal, respec-tively. We have also indicated the gate-source voltage, , the drain-sourcevoltage, , and the bulk-source voltage, . The drain current, is alsoindicated in the figure. In most processes, the bulk terminals of all NMOS tran-sistors are connected to ground, and the simplified symbol in Fig. 5.1(b), withoutthe bulk terminal explicitly shown, can be used instead.

Equations (5.1), (5.2), and (5.3) model the relationships between the drain cur-rent and the different voltages for a long channel NMOS transistor in the cut-off,linear, and saturated region, respectively.

, (5.1)

,

, (5.2)

and

,

. (5.3)

(a) (b)

Figure 5.1 (a) Symbol for an NMOS transistor, and (b) simplified symbol for an NMOStransistor with the bulk terminal connected to ground.

V GSV DS V BS ID

D

S

G B

VBS

VDS

VGS

ID

V GS V T n,< ⇒ID 0=

V GS V T n,≥ V DS V GS V T n,–< V eff= ⇒

ID µ0 n, CoxWL----- V eff V DS

V DS2

2----------–

=

V GS V T n,≥ V DS V GS V T n,–≥ V eff= ⇒

ID

µ0 n, Cox

2-------------------W

L-----V eff

2 1 λ V DS V eff–( )+( )=

CMOS processes

79

is the threshold voltage, is the electron mobility, is the gate oxidecapacitance per unit area, and and is the width and the length of the transis-tor, respectively. is a parameter known as the output impedance constant,which is roughly proportional to [8]. A phenomenon known as the bodyeffect makes the threshold voltage dependent on the bulk-source voltage accord-ing to

, (5.4)

where is the threshold voltage at zero . The built-in Fermi potential and the body effect constant are process dependent parameters [8].

PMOS transistors

Symbols for PMOS transistors are shown in Fig. 5.2. In Fig. 5.2(a) the four ter-minal symbol is shown, and the corresponding simplified symbol where it isimplied that the bulk terminal is connected to the power supply voltage ( ) isshown in Fig. 5.2(b).

Equations (5.5), (5.6), and (5.7) model a long channel PMOS transistor in thecut-off region, linear region, and saturated region, respectively

, (5.5)

,

, (5.6)

and

(a) (b)

Figure 5.2 (a) PMOS transistor symbol and (b) simplified PMOS transistor symbol.

V T n, µ0 n, CoxW L

λ1 L⁄

V T n, V T n 0, , γ 2ΦF V BS– 2ΦF–( )+=

V T n 0, , V BSΦF γ

V DD

S

D

G B

VSBVSD

VSG

ID

V SG V T p,< ⇒ID 0=

V SG V T p,≥ V SD V SG V T p,–< V eff= ⇒

ID µ0 p, CoxWL----- V eff V SD

V SD2

2----------–

=


80

,

. (5.7)

The threshold voltage for PMOS transistors is negative. Due to the body effectwe get

. (5.8)

Notes on large signal models

The large signal equations presented above are only suitable for long channeldevices. Circuit simulators utilize more elaborate models, including many higherorder effects, to get more accurate results. Higher order effects become more andmore important as device dimensions become smaller and smaller.

5.1.2 Small signal models

As can be seen from the equations in Sec. 5.1.1, MOS transistors are nonlineardevices. In order to find the effect of small variations in currents and voltages weuse linearized models, so called small signal models.

In Fig. 5.3(a) below we show a so called -parameter model of an NMOS tran-sistor. The parameters in the saturated region are given by

, (5.9)

, (5.10)

and

. (5.11)

The corresponding small signal equivalent model for PMOS transistors is shownin Fig. 5.3(b). The parameters are given by

, (5.12)

V SG V T p,≥ V SD V SG V T p,–≥ V eff= ⇒

ID

µ0 p, Cox

2-------------------W

L-----V eff

2 1 λ V SD V eff–( )+( )=

V T p, V T p 0, , γ 2ΦF V SB– 2ΦF–( )–=

g

gm V GS∂∂ID 2µ0 n, Cox

WL-----ID≈=

gds V DS∂∂ID λID≈=

gmbs V BS∂∂ID γ gm

2 2ΦF V BS–------------------------------------≈=

gm V SG∂∂ID 2µ0 p, Cox

WL-----ID≈=

Analog DAC building blocks

81

, (5.13)

and

. (5.14)

5.2 Analog DAC building blocks

Different aspects of the design of analog building blocks are discussed in thissection. An overview of implementation a current source is given in Sec. 5.2.1,and implementation of switches is discussed in Sec. 5.2.2.

5.2.1 CMOS current sources

Current sources are essential building blocks in current-steering DACs, and in theprevious section we have established transistor models that are adequate to dis-cuss the implementation of current sources in CMOS technology. We know fromChapter 3 that the output impedance of the current source, and the matchingbetween the current sources, are critical parameters for the linearity of the DACs.

Single transistor current source

A single transistor PMOS current source is shown in Fig. 5.4(a). The bias voltageis set by a bias circuit, as discussed in Sec. 4.1.2. The ideal current source hasinfinite output impedance, i.e., the output current is independent on the voltageacross the current source. This is desired in current steering DACs since we wantthe output current (from each current source) to be independent on the outputvoltage. In reality the output resistance of the current source is

(a) (b)

Figure 5.3 Small signal equivalent model of (a) an NMOS transistor and (b) a PMOS tran-sistor.

gmvgs gmbsvbs gds

G D

S

vgs vds

id

gmvsg gmsbvsb gds

G D

S

vsg vds

id

gds V SD∂∂ID λID≈=

gmsb V SB∂∂ID γ gm

2 2ΦF V SB–------------------------------------≈=


82

, (5.15)

due to the channel length modulation. Moreover, parasitic capacitance in thedevices, indicated in Fig. 5.4(a), contributes to a capacitive part of the outputimpedance. The total output impedance is

, (5.16)

where the output capacitance and is the for the tran-sistor.

Cascode current source

If the output resistance is not large enough to meet the required linearity, we canuse a cascode current source as shown in Fig. 5.4(b). The output resistance forthis current source is approximately

, (5.17)

where and are small signal parameters for the cascode transistorand is the for the source transistor. The output resistance isincreased, since . The cascode transistor reduces the voltagevariations over the parasitic capacitance , compared with the single transis-

(a) (b)

Figure 5.4 PMOS current sources (a) without and (b) with cascode transistor.

Rout1

gds source,---------------------- ∞<=

Zout1

gds source, sCout+-----------------------------------------=

Cout C p 1,= gds source, gds

VbiasCp,1

Iout

VbiasCp,1

Iout

Cp,2Vcasc

sourcetransistor

cascodetransistor

Rout

gm casc,gds casc,----------------- 1

gds source,----------------------⋅≈

gm casc, gds casc,gds source, gds

gm casc, gds casc,»C p 1,

Analog DAC building blocks

83

tor case. Hence, the influence of on the bandwidth of the current source isreduced. There are, however, also parasitic capacitance in the output node of thecascode transistor. The output impedance is approximately

, (5.18)

where in this case . For higher frequencies where the capacitive partdominates, then for both type of current sources. isroughly a parallel connection between the gate-drain and the drain-bulk capaci-tance for the transistor connected to the output node. The value of the parasiticcapacitance is mainly determined by the width of the transistor. If the width is ofthe same order in both the cascoded and the single transistor case, yielding

, we have not gained very much in the range of frequencies wherethe capacitive part is dominating. A part of the output capacitance is also contrib-uted to by the metal wires connected to the current sources. This part of thecapacitance is unaffected by the choice of current source. In the next section weshow that the cascoding effect can also be achieved with the switch. The conclu-sions are that for higher frequencies we do not gain very much by introducingcascode transistors but we loose in possible output swing since we need to keepall transistors in saturation (the output resistance is severely deteriorated if thetransistors enter the linear region). Therefore, the cascode transistors have beenomitted in the later DAC implementations.

5.2.2 CMOS switches

The switches are also critical building blocks in current-steering DACs. In thissection we will assume that the current sources are of PMOS type. In the case ofNMOS current sources the discussion is similar. Differential PMOS and NMOSswitches are shown in Fig. 5.5(a) and (b), respectively.

(a) (b)

Figure 5.5 CMOS implementations of (a) a differential PMOS switch and (b) a differentialNMOS switch.

C p 1,

Zout1

gds source,gds casc,gm casc,----------------- sCout+

------------------------------------------------------------≈

Cout C p 2,≈Zout 1 sCout( )⁄≈ Cout

C p 1, C p 2,≈

Iin

I+ I

Q+ Q

Iin

I+ I

Q+ Q


84

It is important that the signals controlling the switches are such that the two tran-sistors in the switch are not simultaneously completely turned off, in which casecharge will be assembled at the output node of the current source and give rise tolarge transients once one of the transistors is turned back on.

Assume that the PMOS type differential switch is used. In steady-state, when oneof the transistors is conducting and the other turned off, the conducting switchtransistor acts as a cascode transistor (compare with Fig. 5.4(b)). In order to haveshort switching times and low channel charge injection from the switches it isdesired to use transistors with small area in the switches. A large isrequired to get a good cascoding effect. Since is proportional to ,there is a trade-off between switch area and cascoding effect. Moreover, when theoutput voltage exceeds the absolute value of the threshold voltage, the switchtransistor enters the linear region of operation and the ratio is deterio-rated. Even if the cascoding effect of the switch is limited, it is better to usePMOS switches than NMOS switches. Similarly, NMOS switches are preferredwhen NMOS current sources are used.

5.3 Digital DAC building blocks

Some digital building blocks are required when implementing DACs. In this sec-tion we discuss the implementation of binary-to-thermometer encoders andswitch signal generators, i.e., the circuits used to generate proper signals to con-trol the switches. The latter is an interface circuit between the digital and the ana-log circuits, and is placed in the group of digital circuits since all circuitsimplemented during this work are designed with classical digital circuit tech-niques. All digital gates have been implemented using the complementary staticCMOS logic style [64, 65, 66].

5.3.1 Binary-to-thermometer encoding

Thermometer coded and segmented DAC architectures are discussed in this sec-tion, and it is motivated why they are preferred to binary coded DACs. We alsopresent the binary-to-thermometer encoder architecture that has been used in theDAC implementations presented in the following.

Thermometer coded and segmented structures in general

First consider a binary weighted architecture, i.e., where the weights .In a transition between, e.g., the codes and

, we may during a short moment have some erroneouscode, e.g., controlling the switches due to different rise and falltimes of the digital circuits. This will cause a so called glitch in the transient

gm gds⁄gm gds⁄ W

gm gds⁄

wi 2i 1–=X 0 1 1 … 1 1, , , , ,[ ]=

X 1 0 0 … 0 0, , , , ,[ ]=1 1 1 … 1 1, , , , ,[ ]

Digital DAC building blocks

85

response of the DAC, as shown in Fig. 5.6. This can occur because in the transi-tion there are individual bits making transitions from to , at the same time asthere are other bits making transitions from to .

Next consider a thermometer coded architecture. The corresponding thermome-ter codes for 2-bit, 3-bit, and 4-bit binary codes are given in Fig. 5.7(a), (b), and(c), respectively. The weight for each bit is , and the superscriptindicates the corresponding number of bits in the binary code. The thermometercode is monotone, i.e., in each transition between codes there only exist transi-tions from to or from to in the individual bits, not both. Therefore,glitches as in Fig. 5.6 cannot occur, indicating an advantage for the thermometercode compared with the binary code. Moreover, even if matching errors willcause the weights to deviate from 1, a thermometer coded DAC is guaranteed tobe monotone, i.e., the output if and only if . This isbecause

(5.19)

and all . As discussed in Sec. 4.1.1, a binary coded converter is not neces-sarily monotone.

Figure 5.6 Large glitch due to poor internal timing in a 4-bit binary weighted DAC. Thedesired transition is from 7 to 8.

0 11 0

n

123456789

101112131415

update instant

outp

ut le

vel

Glitch in 4−bit binary weighted DAC

tik wi 1= k

1 0 0 1

Y X1( ) Y X2( )> X1 X2>

Y X1( ) wi

i 1=

X1

∑ wi

i 1=

X2

∑ wi

i X2 1+=

X1

∑+ Y X2( ) wi

i X2 1+=

X1

∑+= = =

wi 0>


86

Other types of codes that falls somewhere between the binary code and the ther-mometer code have also been proposed, e.g., linear and polynomial codes[67, 68], but these are not covered in this thesis. One code, that also falls betweenthe binary and the thermometer code, and is commonly used in DAC design is thesegmented code. An -bit binary code corresponds to a -bit thermome-ter code. Hence, the hardware complexity in the encoding circuitry increasesexponentially with , and becomes excessively large for large . An often used

(a) (b)

(c)

Figure 5.7 Truth tables for (a) 2-3 encoder and (b) 3-7 encoder, and (c) 4-15 encoder.

b1

b0

t32 t

22 t

12

0 0 0 0 00 1 0 0 11 0 0 1 11 1 1 1 1

b2

b1

b0

t73 t

63 t

53 t

43 t

33 t

23 t

13

0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 1

0 1 1 0 0 0 0 1 1 1

1 0 0 0 0 0 1 1 1 1

1 0 1 0 0 1 1 1 1 1

1 1 0 0 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

b3

b2

b1

b0

t154 t

144 t

134 t

124 t

114 t

104 t

94 t

84 t

74 t

64 t

54 t

44 t

34 t

24 t

14

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1

0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1

1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

N 2N 1–( )

N N


87

compromise is to use thermometer code for a few of the MSBs, say of theMSBs, and let the remaining LSBs be binary weighted. This is referred toas a segmented code. Assume a binary weighted input code

, (5.20)

which is encoded into segmented code

, (5.21)

where

, (5.22)

and is thermometer encoded from .This is illustrated in Fig. 5.8(a), where a block diagram of a segmented DAC isshown. The corresponding weights for the segmented codes, , are

. (5.23)

There are also multi-segmented architectures, as indicated in Fig. 5.8(b), wheremore segments of the binary coded input are converted into thermometer code.One example is the doubly segmented DAC presented in Sec. 5.7.

Implementation of binary-to-thermometer encoders

Analyzing the truth tables in Fig. 5.7 we will come up with a regular circuit solu-tion utilizing a tree structure of NAND gates, NOR gates, and inverters, previ-ously reported by Wikner in [69]. This type of encoder has been used in allimplementations described in this chapter. A similar (or possibly identical) solu-tion has been faintly outlined by others [70].

First we consider the 2-3 encoder. It is easily verified from the truth table inFig. 5.7(a) that

,

, and

. (5.24)

KN K–

Xb bN 1– bN 2– … b0, , ,[ ]=

Xs s2K N K– 2–+ … sN K– sN K– 1– … s0, , , , ,[ ]=

sN K– 1– … s0, ,[ ] bN K– 1– … b0, ,[ ]=

s2K N K– 2–+ … sN K–, ,[ ] bN 1– … bN K–, ,[ ]

ws i,

ws i,2i for i 0 N K– 1–,[ ]∈

2N K– for i 2K N K– 2–+ N 1–,[ ]∈

=

t12 b1 b0,( ) b1 b0+=

t22

b1 b0,( ) b1=

t32 b1 b0,( ) b1 b0⋅=


88

(a)

(b)

Figure 5.8 (a) Segmented and (b) multi-segmented current-steering DAC architecture.

bina

ry-t

o-th

erm

omet

eren

code

rde

lay

bina

ry c

ode

MSBs

LSBs

latches,switches,

andcurrent sources

dela

yen

code

rs

latches,switches,

andcurrent sources


89

In Fig. 5.7(b) it is indicated that the truth table of the 2-3 encoder, with inputsand , appears twice in the truth table for the 3-7 encoder. The logic expressiondescribing the 3-7 encoder is

,

, and

, (5.25)

where .

In Fig. 5.7(c) it is indicated that the logic expressions for a 4-bit encoder can beobtained in a similar fashion if a 3-bit encoder is available. For the general -bitencoder we have

,

, and

, (5.26)

where . Rewriting (5.26) yields

,

, and

. (5.27)

Since differential signals are used to control the switches, it is unimportantwhether the outputs from the encoder are the thermometer coded bits or theirinverses, since both types are required. Therefore, if we allow that the outputsfrom even order encoders (i.e., the encoders for which is an even integer) arethe inverted thermometer coded bits, any -bit encoder can be implemented witha tree of NAND gates, NOR gates and inverters. A 2-bit encoder, a general evenorder encoder, and a general odd order encoder are shown in Fig. 5.9(a), (b) and(c), respectively.

The binary-to-thermometer encoder can be physically implemented in variousways. One way is to describe the block in a hardware description language, e.g.,VHDL or Verilog [71], and utilize a synthesis flow on this description to auto-matically generate the circuit. In the implementations presented in this chapterwe have used the full-custom approach.

b0b1

t j3 b2 b1 b0, ,( ) b2 t j

2 b1 b0,( )+ b2 t j2 b1 b0,( )⋅= =

t43 b2 b1 b0, ,( ) b2 b2= =

t j 4+ b2 b1 b0, ,( ) b2 t j2 b1 b0,( )⋅ b2 t j

2 b1 b0,( )+= =

j 1 2 3, , ∈

N

t jN bN 1– … b0, ,( ) bN 1– t j

N 1– bN 2– … b0, ,( )⋅=

t2N 1– bN 1– … b0, ,( ) bN 1–=

t j 2N 1–+N bN 1– … b0, ,( ) bN 1– t j

N 1– bN 2– … b0, ,( )+=

j 1 … 2N 1– 1–, , ∈

t jN bN 1– … b0, ,( ) bN 1– t j

N 1– bN 2– … b0, ,( )+=

t2N 1– bN 1– … b0, ,( ) bN 1–=

t j 2N 1–+N bN 1– … b0, ,( ) bN 1– t j

N 1– bN 2– … b0, ,( )⋅=

NN


90

5.3.2 Switch signal generators

In the following we assume that the switches are PMOS switches, as inSec. 5.2.2. To avoid that both transistors are simultaneously turned off, theswitching signals and should not simultaneously be high [72], but ratherhave nonoverlapping waveforms similar to those in Fig. 5.10. Two different cir-cuits for creating nonoverlapping switching signals are presented in this section.Both have been used in the implementations presented in the following. ForNMOS switches it is instead required that the switching signals are overlapping.These signals can be generated in a similar way as nonoverlapping signals.

The first circuit, which uses digital logic gates, is shown in Fig. 5.11. It isassumed that the inputs are synchronized with flip-flops or similar. In steadystate, and . When there is a transition in the inputs, an outputcannot go high until the other output has reached a low level.

(a)

(b) (c)

Figure 5.9 (a) 2-bit encoder, (b) even order N-bit encoder, and (c) odd order N-bit encoder.The boxes in (b) and (c) represents (N-1)-bit encoders.

b0

b1

t12

t22

t32

b0

bN−2

bN−1

t1N−1

t2

N−1−1

N−1

t1N

t2

N−1−1

N

t2

N−1N

t2

N−1+1

N

t2

N−1

N

b0

bN−2

bN−1

t1N−1

t2

N−1−1

N−1

t1N

t2

N−1−1

N

t2

N−1N

t2

N−1+1

N

t2

N−1

N

Q+ Q–

Q+ D= Q– D=

DAC design strategies and measurement setup

91

The second solution utilizes clocked differential cascode voltage switch (DCVS)[73] latches, and is shown in Fig. 5.12. It is required that the inputs only changetheir values while the clock signal, , is high, i.e., when the clocked transistorsare turned off. This can be ensured by adding a latch at the input which is trans-parent only during the high clock phase. By proper sizing of the transistors, thecrossover point between and can be chosen to avoid having both switchtransistors simultaneously shut off [21].

5.4 DAC design strategies and measurement setup

Some overall design strategies are shared between the current-steering DACimplementations presented in this chapter. To avoid repeating these design strate-gies for each DAC separately, we have compiled them in this section. We alsopresent the measurement setup that has been used.

Figure 5.10 Nonoverlapping switch signals for controlling differential PMOS switches.

Figure 5.11 Implementation of switch signal generator utilizing cross coupled NOR gates.

n n+1 n+2

0

1

Nonoverlapping switch signals

Update instant

Logi

c le

vel

D

D

Q+

Q−

Φ

Q+ Q–


92

5.4.1 Overall layout structure

An overview of a DAC floor plan is shown in Fig. 5.13. Starting from the left wehave the digital inputs entering the digital encoder consisting of binary-to-ther-mometer encoders and delay elements. Once the decoding is performed, the sig-nals are applied to the switch signal generators (denoted latches in Fig. 5.13),whose outputs are used to control the switches. The current sources are placed inthe block in the right part of Fig. 5.13, and the output current wires are placedbetween the array and the switches.

Figure 5.12 Clocked DCVS latch implementation of a switch signal generator.

Figure 5.13 Layout strategy used in the DAC implementations.

D D

F F

Q Q+


latc

hes

& s

wit

ches

enco

ding

& d

elay

output currentsdigital input

DAC design strategies and measurement setup

93

In other design strategies, using so called row-column decoding for thermometerencoding, the switches and some digital logic are placed within the arrays [7].This may cause interference between digital and analog parts, leading to a noisyoutput signal. With the layout strategy used in the implementations presented inthis chapter, the analog and digital parts are separated. Guard rings are usedaround digital as well as analog parts to reduce the substrate noise in the analogparts due to switching in the digital parts. Separate supply voltages are used fordigital and analog circuitry, to reduce the amount of simultaneous switchingnoise [74] in the analog signals.

5.4.2 Clocking strategy

Uncertainties in the timing of the switching signals, known as jitter, cause distor-tion and noise in the DAC output. It is therefore important that the DAC isupdated at well-defined instants in time. In order to achieve that, it is requiredthat the clock net driving the switch signal generators is carefully designed. Aschematic of a clock net with a tree structure that has been used in the implemen-tations is shown in Fig. 5.14. Special care has been given to equalizing thelengths of the wires connected to the output of the inverting buffers in each levelof the tree in the layout. This is in order to have the same capacitive load in eachbranch to avoid skew of the clock signal between the branches.

5.4.3 Measurement setup

The DAC measurements presented in the following sections have been performedusing a measurement system outlined in Fig. 5.15(a). The measurement system iscontrolled by a personal computer (PC) running Matlab. Input data to the DAC is

Figure 5.14 Tree clock network for driving the switch signal generators.


94

delivered from a measurement board with a low voltage differential signalling(LVDS) interface to the DAC. This measurement board is also capable of collect-ing digital data for, e.g., ADC measurements. This feature is not used during theDAC measurements, and is therefore omitted in Fig. 5.15. The peripheral instru-ments, such as power supply, clock generator, oscilloscope, and spectrum ana-lyzer, are connected to the PC via a general purpose interface bus (GPIB). Theinstruments are controlled by a GPIB controller, which in turn is controlled fromMatlab. Measurement data can be collected from the measurement instrumentsover the GPIB, and further analyzed in Matlab.

A printed circuit board (PCB) for DAC measurement is outlined in Fig. 5.15(b).The output currents from the DAC is directed into off-chip resistors. An RF-transformer is used to convert the differential signal to a single-ended signal thatcan be handled by the different measurement instruments. In order to measure theindividual single-ended outputs, the transformer must be removed.

5.5 A 14-bit DAC in 0.35 µm CMOS

In this section we present the first DAC chip manufactured during this work. Abrief overview of the chip is given in Sec. 5.5.1. Measurement results are pre-sented in Sec. 5.5.2.

5.5.1 Chip description

A photo of the chip is shown in Fig. 5.16. The chip was fabricated in a 0.35 µmCMOS process with three metal layers. The total chip area is 7.3 mm2, whereasthe core area is 2 mm2. The DAC is segmented, where the 5 MSBs are encodedinto thermometer code and the remaining 9 LSBs are binary weighted. The cur-rent sources are of PMOS type utilizing a single cascode transistor, and theswitches are of NMOS type. As was mentioned in Sec. 5.2.2, it would have beena better choice to use PMOS switches. This mistake was corrected in the laterimplementations. The strategy used for placement of unit current sources in thearray was aimed at reducing the influence of linearly graded parameter varia-tions. The switch signal generators are of the type shown in Fig. 5.11. A thoroughdescription of the design is given in [75].

5.5.2 Measurement results

Output spectra from differential full-scale single-tone measurements are shownin Fig. 5.17. For the (a) and (b) figures the update frequency is 5 MHz, and thesignal frequencies are approximately 0.6 MHz and 1.6 MHz, respectively. Theupdate frequency in the (c) and (d) figures is 20 MHz, and the signal frequencies

A 14-bit DAC in 0.35 µm CMOS

95

are approximately 2.5 MHz and 6.5 MHz, respectively. A common property forall spectra in Fig. 5.17 is that the dominating spurious tone is the third harmonic,and we observe that the SFDR decreases with increasing signal frequency.

(a)

(b)

Figure 5.15 Setup for DAC measurements. The block diagram in (a) shows the PC con-trolled measurement system, and a PCB used for DAC measurement is outlinedin (b).

PC GPIBcontroller

powersupply

clockgenerator

DAC

oscilloscope

spectrumanalyzer

measurementboard

DAC

loadresistors

RFtransformer

single-endedoutputs

digital input

combinedoutput

analog supplydigital supply

clock


96

Output spectra for half-scale single-tone measurements are shown Fig. 5.18below. The signal and update frequency for each sub figure is the same as in thecorresponding sub figure in Fig. 5.17. Once again we find that the dominatingspurious tone is the third harmonic, and that the SFDR decreases with increasingsignal frequency.

The measurements were carried out for several signal frequencies, and the SFDRwas extracted from the spectra. SFDR is plotted as a function of signal frequencyin Fig. 5.19. Fig. 5.19(a) shows SFDR for the full-scale inputs, whereasFig. 5.19(b) shows SFDR for the half scale inputs.

These measurement results correspond well with the simulation results presentedin Sec. 3.4. This indicates that the models of nonlinear behavior due to parasiticcapacitance that was presented provide good descriptions of the behavior of cur-

Figure 5.16 Chip photo of the 14-bit current-steering DAC implemented in a 0.35 µmCMOS process.

A 14-bit PRDEM DAC in 0.35 µm CMOS

97

rent-steering DACs at higher frequencies. In the later implementations, presentedin Sec. 5.6 and Sec. 5.7, the dynamic properties were improved (compared withthis implementation) by reducing the amount of parasitic capacitance.

5.6 A 14-bit PRDEM DAC in 0.35 µm CMOS

DEM techniques that use randomization to reduce the harmonic distortion causedby component mismatch were presented in Sec. 4.1.3. In the PRDEM techniquethe degree of randomization is lower than in fully randomized DEM techniques,e.g., FRDEM, but the hardware cost is considerably lower. The design, simula-tion and measurement of a 14-bit PRDEM DAC is discussed in this section.

(a) (b)

(c) (d)

Figure 5.17 Single-tone full-scale measurements on 14-bit DAC in 0.35 µm CMOS. For (a)and (b) the update frequency is 5 MHz, and the signal frequencies are approxi-mately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d) the update fre-quency is 20 MHz, and the signal frequencies are approximately 2.55 MHz and6.55 MHz, respectively.

0 0.5 1 1.5 2 2.5

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Output Spectrum, fu = 5 MHz.

Frequency [Hz]

PS

D [d

Bm

/Hz]

0 0.5 1 1.5 2 2.5

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


Frequency [Hz]

PS

D [d

Bm

/Hz]

0 2 4 6 8 10

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


Frequency [Hz]

PS

D [d

Bm

/Hz]

0 2 4 6 8 10

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


Frequency [Hz]

PS

D [d

Bm

/Hz]


98

Comparisons between measurements and simulations using models of mismatchand dynamic errors discussed in Chapter 3 are presented, showing a good agree-ment between simulations and measurements.

5.6.1 Implementation

The PRDEM chip is constructed with four layers of switching. The control sig-nals for the switches are generated off-chip to allow flexibility. The switchingtree is terminated with DAC banks consisting of one 1-bit DAC and one 10-bitDAC, as was discussed in Sec. 4.1.3. The current sources and the currentswitches are both of PMOS type, and no cascodes have been used in the current

(a) (b)

(c) (d)

Figure 5.18 Single-tone, half-scale measurements on a 14-bit DAC in 0.35 µm CMOS. For(a) and (b) the update frequency is 5 MHz, and the signal frequencies areapproximately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d) the updatefrequency is 20 MHz, and the signal frequencies are approximately 2.55 MHzand 6.55 MHz, respectively.

0 0.5 1 1.5 2 2.5

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


Frequency [Hz]

PS

D [d

Bm

/Hz]

0 0.5 1 1.5 2 2.5

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


Frequency [Hz]

PS

D [d

Bm

/Hz]

0 2 4 6 8 10

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


Frequency [Hz]

PS

D [d

Bm

/Hz]

0 2 4 6 8 10

x 106

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


Frequency [Hz]

PS

D [d

Bm

/Hz]


99

sources. A description of the design strategy used is given in [76]. A chip photoof the PRDEM DAC is shown in Fig. 5.16. The core area of the chip is approxi-mately 6.3 mm2.

(a) (b)

Figure 5.19 SFDR vs. signal frequency for (a) full-scale signals and (b) half-scale signals.The upper curve in both figures correspond to the update frequency 5 MHz,whereas the lower curves correspond to the update frequency 20 MHz.

Figure 5.20 Chip photo of current-steering PRDEM DAC.

105

106

107

40

45

50

55

60

65

70SFDR vs. Signal Frequency

Signal frequency [Hz]

SF

DR

[dB

]fu = 5 MHz

fu = 20 MHz

105

106

107

40

45

50

55

60

65



SF

DR

[dB

]

fu = 5 MHz

fu = 20 MHz

DAC bank


100

5.6.2 Simulations and comparison with measurements

Comparisons between measurements and simulations of the PRDEM DAC arepresented in [34] and [35]. This section is a summary of these papers.

Simulation setup and results

In the simulations a Gaussian distributed error current with a standard deviationof approximately 10% has been added to each unit current source. This is a ratherlarge value but it includes all static errors in the DAC, e.g., mismatch betweencurrent sources, mismatch in biasing, gain errors between the DAC banks etc.The input is a full scale sinusoid with frequency and update fre-quency of . The single-ended output, terminated over 50 Ω, isexamined. The parameters used for the state-space model are given inTable 5.1.The output without randomization is shown in Fig. 5.21(a). The SFDR(60.2 dB) is limited by the third harmonic. When introducing switching in thefirst layer (Fig. 5.21(b)) the SFDR is increased to 67.7 dB, an improvement of7.5 dB corresponding to approximately one effective bit, to the cost of a some-what higher noise floor. The SFDR is now limited by the second harmonic. Whenintroducing switching in all four layers (Fig. 5.21(c)) we can see some smallerdifferences compared with Fig. 5.21(b) but the SFDR remains the same, hencewe do not gain any SFDR performance by having more than one switching layer.This can be explained by observing the second harmonic in Fig. 5.21(a), (b) and(c). The second harmonic is almost unaffected by the randomization, because itarises from dynamic errors in the DAC and as soon as the third harmonic, arisingfrom mismatch, is suppressed below the second harmonic we do not gain inSFDR performance by using DEM [69].

DAC model parameter Value

Unit current (nominal) 1.22 µA

Output resistance (unit current source) 1 GΩ

Output capacitance (unit current source) 10 fF

Switch resistance 200 Ω

Load resistance 50 Ω

Load capacitance 100 pF

Table 5.1 DAC model parameters used in the simulations.

f sig 1.25 MHz≈f u 10 MHz=


101

Measurement results

To verify the simulated results, the implemented DAC is measured with the sameupdate frequency, . In Fig. 5.22(a) and Fig. 5.22(b) we comparethe gain in performance between using no randomization and using one switch-ing layer. We find that the SFDR is increased from 60.7 to 67.7 dB, an improve-ment of 7.5 dB which could be predicted from the simulation results. Whenswitching all four layers (Fig. 5.22(c)) we do not gain much in SFDR perfor-mance compared with the results in Fig. 5.22(b).

Comparison of SFDR performance

To see how well the model works for different update frequencies, the simulatedresults were compared with measurement results from the real PRDEM DAC.The update frequency is swept while the ratio between signal frequency andupdate frequency, , is held constant. The simulated and measured

(a)

(b) (c)

Figure 5.21 Simulated spectra using 10MHz update frequency, (a) without randomization,with (b) one switching layer and (c) four layer switching.

0 1 2 3 4 5−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Simulated Spectrum Without DEM

PS

D [d

B/H

z]

Frequency [MHz]

SFDR = 59.6 dB

0 1 2 3 4 5−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Simulated With 1 Layer DEM

PS

D [d

B/H

z]

Frequency [MHz]

SFDR = 67.8 dB

0 1 2 3 4 5−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Simulated With 4 Layer DEM

PS

D [d

B/H

z]

Frequency [MHz]

SFDR = 68.1 dB

f u 10 MHz=

f sig f u⁄ 1 8⁄≈


102

SFDR without randomization are compared in Fig. 5.23(a). The same compari-son with randomization is shown in Fig. 5.23(b). We find from Fig. 5.23(a) andFig. 5.23(b) that the simulated and measured results behaves similarly, which is agood validation of the models used in the simulations.

5.7 A dual 14-bit DAC in 0.25 µm CMOS

Design and measurement results of a 14-bit dual DAC implemented in a 0.25 µmCMOS process is presented in this section. The term dual indicates that twoDACs are implemented on the same chip. The chip can, e.g., be used for evalua-tion of the techniques presented in Sec. 4.2.1, or to realize a single switchinglayer PRDEM DAC.

(a)

(b) (c)

Figure 5.22 Measured spectra, 10MHz update frequency, (a) without randomization, with(b) one switching layer and (c) four layer switching.

0.5 1 1.5 2 2.5 3 3.5 4 4.5−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency [MHz]

PS

D [d

B/H

z]

Measured Spectrum Without DEM

SFDR = 60.7 dB

0.5 1 1.5 2 2.5 3 3.5 4 4.5−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency [MHz]

PS

D [d

B/H

z]

Measured With 1 Layer DEM

SFDR = 67.3 dB

0.5 1 1.5 2 2.5 3 3.5 4 4.5−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency [MHz]

PS

D [d

B/H

z]

Measured With 4 Layer DEM

SFDR = 68 dB

A dual 14-bit DAC in 0.25 µm CMOS

103

5.7.1 Architecture and implementation

The DAC has a doubly segmented architecture where both the seven LSBs andthe seven MSBs are converted into thermometer code controlling the currentswitches. A single PMOS transistor current source and PMOS current switchesare used. The circuit in Fig. 5.12 is used for generation of the switching signals.Distributed biasing (see Sec. 4.1.2) is used to achieve good matching properties.The current source arrays are divided into eight sub arrays having individuallocal bias circuits. The bias currents for the local bias circuits are generated witha global bias circuit consisting of a multiple output cascoded NMOS current mir-ror, which is shared between the two DACs to obtain good mutual matching. Aplot of the DAC chip is shown in Fig. 5.24.

Current source arrays and the binary-to-thermometer encoder described inSec. 5.3.1 are examples of regular circuit structures. The regularity has been uti-lized in this implementation for automated design. Some sub cells, like a currentsource, a switch and logic gates, have been designed by hand, whereas practicallyall other parts of the design have been based on scripts. This has greatly reducedthe time required for the design. Similar approaches are used by others [77].There is a trend of increased use of design automation for analog and mixed sig-nal circuits [78], which will likely continue in the future.

5.7.2 Measurement results

One reason for implementing two converters on the same chip is, as mentioned,to have a test chip for the techniques presented in Sec. 4.2.1. At this point, how-ever, the DACs have only been measured one at a time, mainly due to the lack ofproper test equipment. SFDR for full-scale signals is plotted as a function of sig-

(a) (b)

Figure 5.23 Simulated and measured SFDR performance for different update frequencieswith (a) no randomization, and (b) switching in all layers.

1 5 10 30

53

56

59

62

65Simulated and measured SFDR without DEM

Sampling Frequency [MHz]

SF

DR

[d

B]

9

10

Nu

mb

er o

f b

its

MeasuredSimulated

1 5 10 30

53

56

59

62

65

68

71

74

Simulated and measured SFDR with DEM

Sampling Frequency [MHz]

SF

DR

[d

B]

9

10

11

12

Nu

mb

er o

f b

its

MeasuredSimulated


104

nal frequency in Fig. 5.25. For the cases when the update frequency is 5 and10 MHz, SFDR is higher than 73 dB for a range of signal frequencies up to3 MHz. This can be regarded as a good result, even if an SFDR of at least 86 dBis required for 14 effective bits. The linearity is deteriorated when the update fre-quency is increased to 25 MHz. This phenomenon is not yet explained, andrequires more study.

A more adequate measure for DMT applications is the MTPR, which is definedin Sec. 2.3.2. For this purpose we use an ADSL-like input, which is quantizedvalues of

, (5.28)

Figure 5.24 Chip plot of the dual current-steering DAC.

X n( ) XDC K a j 2πnj ∆ f⋅

f u------------- φ j+

sin⋅j 1=

255

∑⋅+=

Summary of implemented DACs

105

where for and otherwise. The frequency spacingand the update frequency . The phases are

random and the scaling factor and the dc level are chosen such that thewhole input range of the DAC ( ) is used. The measured signal spec-trum is shown in Fig. 5.26. The MTPR, limited by the noise floor, is approxi-mately 71 dB. This is a good result, even compared with commercial DACs forDSL applications, e.g., AD9764 [33] from Analog Devices, Inc.

5.8 Summary of implemented DACs

The DAC implementations presented in this chapter are summarized in Table 5.2.The DAC with the highest performance is clearly the dual DAC presented inSec. 5.7. The modeling of nonideal behavior presented in Chapter 3 has providedan insight in what parameters are most important and allowed an improvementfrom one circuit implementation to the next.

Figure 5.25 Measured SFDR as a function of signal frequency.

106

107

50

55

60

65

70

75



SF

DR

[dB

]

fu = 5 MHz

fu = 10 MHz

fu = 25 MHz

a j 0= j 142= a j 1=∆ f 4.3125 kHz= f u 10 MHz= φ j

K XDC0 214 1–,[ ]


106

Figure 5.26 MTPR measurement result.

0.35 µm DAC 0.35 µm PRDEM DAC 0.25 µm dual DAC

Number of bits 14 14 14

Core area 2 mm2 6.3 mm2 4 mm2 (totally forboth DACs)

Supply voltage 3.3 V 3.3 V 2.7 V

Unit current 1.22 µA 1.22 µA 1.22 µA

Segmentation 5 bits5+5 bits in each DAC

bank7+7 bits in each

DAC

Peak SFDR 64 dB62 dB without DEM

72 dB with DEM78 dB

SFDR @ 1MHz signal

58 dB60 dB without DEM

67 dB with DEM

77 dB,

Table 5.2 Summary of implemented DACs.

missing tone

f u 5 MHz=

107

6 ConclusionsThe thesis covered selected topics in the areas modeling, error correction tech-niques and implementation of CMOS DACs. The main focus was on the linearityproperties of current-steering DACs for telecommunication applications.

The application of DACs in DSL environments was outlined. The requirementson high linearity in the DAC was illustrated by examining the influence of non-linear distortion on QAM constellations. The ideal DAC was presented, as wellas some performance measures commonly used for characterizing communica-tion DACs.

Different sources of nonlinear behavior in current-steering DACs were discussed.The static errors dominate the low-frequency behavior, whereas the high-fre-quency behavior is dominated by dynamic errors. Mismatch between circuit ele-ments is one of the main sources of static nonlinear behavior. An analysis of theinfluence of linearly graded matching errors on the performance of current-steer-ing DACs with a certain layout strategy was made. This layout strategy is knownto have poor properties when it comes to suppressing matching errors, but wasuseful in the example. The source of nonlinear behavior that was focused on inthis work was the parasitic capacitance in the transistors and the wires. The phe-nomenon was first modeled with a state-space model in Matlab. Results fromsimulations using this model were presented to illustrate the effect of the noni-deal components included in the model. A model with relatively low computa-tional complexity was developed. This model is suitable for on-chipimplementation for use in error correction/compensation techniques.

Various methods for improving the linearity of DACs were discussed. Some ofthe methods, like DEM and the differential DAC architecture, rely on redundantcoding to improve the linearity. In DEM the distortion caused by mismatch is, insome sense, transformed into noise. To gain in the overall SNDR, oversampling

Conclusions

108

and filtering of out-of-band noise are required. Other methods, like distributedbiasing and a proposed calibration technique, aim at reducing the mismatchbetween the output currents from the current sources. Two ideas utilizing modelsof the dynamic nonlinearity caused by nonzero output capacitance in the currentsources were proposed. Both ideas aimed for enhanced linearity at higher signalfrequencies. The first method utilized a feedback loop similar to delta-sigmamodulation, and was denoted distortion shaping. The second method was a typeof predistortion. The simulations showed promising results, and an initial mea-surement of the distortion shaping method indicates that the models used aregood enough to be practically useful. More measurements, and possibly modelmodifications, are, however, required to draw any further conclusions.

Three different implementations of current-steering DACs in CMOS were pre-sented. The required building blocks were discussed separately, and overalldesign considerations were presented. The first two DACs were fabricated in a0.35 µm CMOS process. One of these DACs utilizes the PRDEM technique forenhanced static linearity. The third converter was fabricated in a 0.25 µm CMOSprocess. Distributed biasing of current sources was used in this implementationto reduce the matching errors between the current sources. Knowledge from thebehavioral level modeling was utilized to improve the performance from one cir-cuit implementation to the next. Measurement results show close resemblancewith the simulation results using the behavioral level models presented in thisthesis. The simulations and measurements on the PRDEM DAC are especiallyinteresting, since they illustrate the limited efficiency of DEM when dynamicerrors dominate, besides validating the behavioral level modeling.

109

References[1] T. Starr, J.M. Cioffi, and P.J. Silverman, Understanding Digital

Subscriber Line Technology, Prentice Hall PTR, Upper Saddle River, NJ,USA, 1999, ISBN 0-13-780545-4.

[2] W.Y. Chen, DSL Simulation Techniques and Standards Development forDigital Subscriber Line Systems, Macmillan Technical Publishing,Indianapolis, IN, USA, 1998, ISBN 1-57870-017-5.

[3] D.J. Rauschmayer, ADSL/VDSL Principles, Macmillan TechnicalPublishing, Indianapolis, IN, USA, 1999, ISBN 1-57870-015-9.

[4] S. Haykin, Communication Systems, 4th Ed., John Wiley & Sons, NewYork, NY, USA, 2001, ISBN 0-471-17869-1.

[5] A. Bindra, “High-speed wideband DACs permit multicarrier cellularbasestations,” Electronic Design, Dec. 18, 2000.

[6] L. Wanhammar, DSP Integrated Circuits, Academic Press, San Diego, CA,USA, 1999, ISBN 0-12-734530-2.

[7] M. Gustavsson, J.J. Wikner, and N. Tan, CMOS Dataconverters forCommunications, Kluwer Academic Publishers, Boston, MA, USA, 2000,ISBN 0-7923-7780-X.

[8] D.A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley& Sons, New York, NY, USA, 1997, ISBN 0-471-14448-7.

[9] R.J. van de Plassche, Integrated Analog-to-Digital and Digital-to-AnalogConverters, Kluwer Academic Publishers, Boston, MA, USA, 1994,ISBN 0-7923-9436-4.

110

[10] P. Hendricks, “Specifying communication DACs,” IEEE Spectr., vol. 34,no. 7, pp. 58-69, Jul. 1997.

[11] Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1,Maxim Integrated Products, Inc. [Online]. Available: http://dbserv.maxim-ic.com/tarticle/view_article.cfm?article_id=111.

[12] M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems,Krieger Publishing Company, Malabar, FL, USA, 1989, ISBN 0-89464-356-8.

[13] P. Wambaq and W. Sansen, Distortion Analysis of Analog IntegratedCircuits, Kluwer Academic Publishers, Boston, MA, USA, 1998, ISBN 0-7923-8186-6.

[14] B.G. Streetman, Solid State Electronic Devices, Prentice-Hall, EnglewoodCliffs, NJ, USA, 1995, ISBN 0-13-436379-5.

[15] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matchingproperties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5,pp. 1433-1439, Oct. 1989.

[16] A. Van den Bosch, M. Steyaert, and W. Sansen, “An accurate statisticalyield model for CMOS current-steering D/A converters,” Proc IEEEInternational Symposium on Circuits and Systems (ISCAS’00), vol. 4,pp. 105-108, Geneva, Switzerland, May 28-30, 2000.

[17] M.J.M. Pelgrom, H.P. Tuinhout, and M. Vertregt, “Transistor matching inanalog CMOS applications,” Proc. 1998 International Electron DevicesMeeting, pp. 915-918, 1996.

[18] A. Van den Bosch, M. Steyaert, and W. Sansen, “The extraction oftransistor mismatch parameters: the CMOS current-steering D/A converteras a test structure,” Proc IEEE International Symposium on Circuits andSystems (ISCAS’00), vol. 2, pp. 745-748, Geneva, Switzerland, May 28-30,2000.

[19] H. Tuinhout, M. Pelgrom, R. Penning de Vries, and M. Vertregt, “Effectsof metal coverage on MOSFET matching,” Proc. 1996 InternationalElectron Devices Meeting, pp. 735-738, 1996.

[20] K.O. Andersson and J.J. Wikner, “Modeling of the influence of gradedelement matching errors in CMOS current-steering DACs,” Proc.NORCHIP Conference, pp. 399-404, Oslo, Norway, Nov. 8-9, 1999.

111

[21] G.A.M. Van der Plas, J. Vandenbussche, W. Sansen, M.S.J. Steyaert, andG. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,”IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.

[22] C.A.A. Bastiaansen, D.W.J. Groeneveld, H.J. Schouwenaars, H.A.H.Termeer, “A 10-b 40-MHz 0.8-µm CMOS current-output D/A converter,”IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 917-921, Jul. 1991.

[23] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b70-MS/s CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 26,no. 4, pp. 637-642, Apr. 1991.

[24] I. Galton, “Spectral shaping of circuit errors in digital-to-analogconverters,” IEEE Trans. Circuits Syst. II, vol. 44, no. 10, pp. 808-817,Oct. 1997.

[25] J.J. Wikner and N. Tan, “Modeling of CMOS digital-to-analog convertersfor telecommunication,” IEEE Trans. Circuits Syst. II, vol. 46, no. 5,pp. 489-499, May 1999.

[26] J.J. Wikner, CMOS Digital-to-Analog Converters for TelecommunicationApplications, Linköping studies in science and technology, Thesis No. 715,ISBN 91-7219-277-1, Linköping, Aug., 1998.

[27] A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidthlimitations for high speed high resolution current steering CMOS D/Aconverters,” Proc. IEEE International Conference on Electronics, Circuits,and Systems (ICECS’99), pp. 1193-1196, 1999.

[28] K.O. Andersson and J.J. Wikner, “Characterization of a CMOS current-steering DAC using state-space models,” Proc. 43rd Midwest Symposiumon Circuits and Systems (MWSCAS’00), pp. 668-671, Lansing, MI, USA,Aug. 8-11, 2000.

[29] H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI,Addison-Wesley, USA, 1990, ISBN 0-201-06008-6.

[30] L. Ljung, System Identification, Theory for the User, Prentice-Hall, UpperSadle River, NJ, USA, 1999, ISBN 0-13-656695-2.

[31] Control Systems Toolbox for use with Matlab - Reference Version 5,Mathworks Inc., 2001, [Online]. Available: http://www.mathworks.com/access/helpdesk/help/toolbox/control/control.shtml.

[32] A. Bugeja and B.S. Song, “A self-trimming 14-b 100-MS/s CMOS DAC,”IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1841-1852, Dec. 1999.

112

[33] AD9764, Datasheet, Analog Devices, Norwood, MA, USA, 1999.

[34] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,“Models and implementation of a dynamic element matching DAC,” toappear in Kluwer International Journal of Analog Integrated Circuits andSignal Processing, Special Issue: Selected Papers from the NORCHIP2001 Conference.

[35] N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,“Models and implementation of a dynamic element matching DAC,” Proc.NORCHIP Conference, pp. 155-160, Kista, Sweden, Nov. 12-13, 2001.

[36] K.O. Andersson, “Improved current-steering D/A conversion,” Swedishpatent 0000731-0, 2000.

[37] D.W.J. Groeneveld and H.J. Schouwenaars, “A dual 3.4V bitstreamcontinuous calibration CMOS D/A converter with 110 dB dynamic range,”Proc. 2nd IEE International Conference on Advanced A/D and D/AConversion Techniques and their Applications, pp. 42-47, 1994.

[38] C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,”IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-58, Dec. 1998.

[39] M.K. Rudberg, M. Vesterbacka, N. Andersson, J.J. Wikner, “GlitchMinimization and Dynamic Element Matching in D/A Converters”, Proc.IEEE International Conference on Electronics, Circuits, and Systems(ICECS’01), Beirut, Lebanon, Dec. 17-20, 2000.

[40] M. Vesterbacka, M.K. Rudberg, J.J. Wikner, and N.U. Andersson,“Dynamic Element Matching in D/A Converters with RestrictedScrambling,” Proc. IEEE International Conference on Electronics,Circuits, and Systems (ICECS’01), Beirut, Lebanon, Dec. 17-20, 2000.

[41] J.W. Bruce and P. Stubberud, “A comparison of hardware efficientdynamic element matching networks for digital to analog converters,”Proc. 43rd Midwest Symposium on Circuits and Systems (MWSCAS’00),pp. 672-675, Lansing, MI, USA, Aug. 8-11, 2000.

[42] H.T. Jensen and I. Galton, “An analysis of the partial randomizationdynamic element matching technique,” IEEE Trans. Circuits Syst. II,vol. 45, no. 12, pp. 1538-1549, Dec. 1998.

[43] P. Stubberud and J.W. Bruce, “An analysis of dynamic element matchingflash digital-to-analog converters,” IEEE Trans Circuits Syst. II, vol. 48,no. 2, Feb. 2001.

113

[44] N.U. Andersson and J.J. Wikner, “A comparison of dynamic elementmatching in DACs,” Proc. NORCHIP Conference, pp. 385-390, Oslo,Norway, Nov. 8-9, 1999.

[45] J. Steensgaard, “High-resolution mismatch-shaping digital-to-analogconverters,” Proc. IEEE International Symposium on Circuits and Systems(ISCAS’01), vol. 1, pp. 516-519, Sydney, Australia, May 6-9, 2001.

[46] U.K. Moon, G.C. Temes, and J. Steensgaard, “Digital techniques forimproving the accuracy of data converters,” IEEE Commun. Mag., vol. 37,no. 10, pp. 136-143, Oct. 1999.

[47] J. Steensgaard, U.-K. Moon, and G.C. Temes, “Mismatch-shaping serialdigital-to-analog converter,” Proc IEEE International Symposium onCircuits and Systems (ISCAS’99), vol. 2, pp. 5-8, Orlando, FL, USA, Jun.1999.

[48] R.E. Radke, A. Eshraghi, and T.S. Fiez, “A 14-bit current-mode ∆Σ DACbased upon rotated data weighted averaging,” IEEE J. Solid-State Circuits,vol. 35, no. 8, pp. 1074-1084, Aug. 2000.

[49] A. Bugeja and B.S. Song, “A 14-b 100-MS/s CMOS DAC designed forspectral performance,” IEEE J. Solid-State Circuits, vol. 35, no. 12,pp. 1841-1852, Dec. 2000.

[50] M. Waltari, J. Pirkkalaniemi, M. Kosunen, L. Sumanen, and K. Halonen,“A 14-bit, 40 MS/s DAC with current mode deglitcher,” Proc. NORCHIPConference, pp. 242-247, Kista, Sweden, Nov. 12-13, 2001.

[51] R.M. Gray and T.G. Stockham Jr., “Dithered quantizers,” IEEE Trans.Inform. Theory, vol. 39, no. 3, pp. 805-812, May 1993.

[52] B. Brannon, Overcoming Converter Nonlinearities with Dither,Application Note AN-410, Analog Devices, Norwood, MA, USA.

[53] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, “Adifferential DAC architecture with variable common-mode level,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’02),vol. 1, pp. 113-116,Scottsdale, AZ, USA, May 26-29, 2002.

[54] K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner,“Combining DACs for improved performance,” Proc. 4th IEEInternational Conference on Advanced A/D and D/A ConversionTechniques and their Applications, Prague, Czech Republic, June 26-28,2002.

114

[55] K.O. Andersson, “Current Steering DAC,” pending Swedish patent, 2001.

[56] K.O. Andersson, N.U. Andersson, and J.J. Wikner, “Spectral shaping ofDAC nonlinearity errors through modulation of expected errors,” Proc.IEEE International Symposium on Circuits and Systems (ISCAS’01),vol. 3, pp. 417-420, Sydney, Australia, May 6-9, 2001.

[57] D. Anastassiou, “Error diffusion coding for A/D conversion,” IEEE Trans.Circuits Syst., vol. 36, no. 9, pp. 1175-1186, Sep. 1989.

[58] R. Schreier and Y. Yang, “Stability tests for single-bit sigma-deltamodulators with second-order FIR noise transfer functions,” Proc. IEEEInternational Symposium on Circuits and Systems (ISCAS’92), vol. 3,pp. 1316-1319, 1992.

[59] K. Morris and P. Kennington, “Power amplifier linearisation usingpredistortion techniques,” IEE Colloquium on RF and MicrowaveComponents for Communication Systems, Digest no. 1997/126, pp. 6/1-6/6, 1997.

[60] S. Andreoli, H.G. McGLure, P. Banelli, and S. Cacopardi “Digitallinearizer for RF amplifiers,” IEEE Trans. Broadcast., vol. 43, no. 1,pp. 12-19, Mar. 1997.

[61] H.W. Kang, Y.S. CHo, and D.H. Youn, “On compensating nonlineardistortions of an OFDM system using an efficient adaptive predistorter,”IEEE Trans. Commun., vol. 47, no. 4, pp. 522-526, Apr. 1999.

[62] K.J. Riley, D.M. Hummels, F.H. Irons, and A. Rundell, “Dynamiccompensation of digital to analog converters,” Proc. 16th IEEEInstrumentation and Measurement Technology Conference (IMTC’99),vol. 2, pp. 1310-1315, 1999.

[63] K.O. Andersson and J.J. Wikner, “Digital-to-analog converter having errorcorrection,” pending Swedish patent, 2002.

[64] J.M. Rabaey, Digital Integrated Circuits - a Design Perspective, Prentice-Hall, Upper Saddle River, NJ, USA, 1996, ISBN 0-13-394271-6.

[65] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design aSystems Perspective, Addison-Wesley, USA, 1993, ISBN 0-201-53376-6.

[66] S.M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysisand Design, McGraw-Hill, USA, 1996, ISBN 0-07-038046-5.

115

[67] J.J. Wikner and M. Vesterbacka, “D/A conversion with linear-codedweights,” Proc. 2000 IEEE Southwest Symposium on Mixed-Signal Design(SSMSD’00), pp. 61-66, San Diego, CA, USA, Feb. 28-29, 2000.

[68] M. Vesterbacka, K.O. Andersson, N.U. Andersson, and J.J. Wikner,“Using different weights in DACs,” Proc. 4th IEE InternationalConference on Advanced A/D and D/A Conversion Techniques and theirApplications, Prague, Czech Republic, June 26-28, 2002.

[69] J.J. Wikner, Studies on CMOS Digital-to-Analog Converters, Linköpingstudies in science and technology, dissertation no. 667, ISBN 91-7219-910-5, Linköping, Sweden, Apr. 2000.

[70] A. Van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit1-GSample/s current-steering CMOS D/A converter,” IEEE J. Solid-StateCircuits, vol. 6, no. 3, pp. 315-324, Mar. 2001.

[71] K. Skahill, VHDL for Programmable Logic, Addison-Wesley, USA, 1996,ISBN 0-201-89573-0.

[72] J. Bastos, A.M. Marques, M.S.J. Steyaert, W. Sansen, “A 12-bit intrinsicaccuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33,no. 12, pp. 1959-1969, Dec. 1998.

[73] K. Bernstein, et. al., High Speed CMOS Design Styles, Kluwer AcademicPublishers, Kluwer Academic Publishers, Boston, MA, USA, 1999,ISBN 0-7923-8220-X.

[74] X. Aragones, J.L. Gonzalez, and A. Rubio, Analysis and Solutions forSwitching Noise Coupling in Mixed-Signal ICs, Kluwer AcademicPublishers, Boston, MA, USA, 1999, ISBN 0-7923-8504-7.

[75] O. Andersson, Mismatch Modeling and Design of CMOS Current-SteeringDigital-to-Analog Converters, M.Sc. thesis, Linköping, Nov., 1999.

[76] N.U. Andersson and J.J. Wikner, “A Strategy of Implementing DynamicElement Matching in Current-Steering DACs,” Proc. 2000 IEEESouthwest Symposium on Mixed-Signal Design (SSMSD’00), pp. 51-56,San Diego, CA, USA, Feb. 28-29, 2000.

[77] J. Vandenbussche, G. Van der Plas, W. Daems, A. Van den Bosch,G. Gielen, M. Steyaert, and W. Sansen, “Systematic design of high-accuracy current-steering D/A converter macrocells for integrated VLSIsystems,” IEEE Trans. Circuits Syst II, vol. 48, no. 3, pp. 300-309, Mar.2001.

116

[78] G.E.G. Gielen, “New methods and tool for analog IP use in mixed-signalintegrated systems,” Proc. NORCHIP Conference, pp. 5-9, Kista, Sweden,Nov. 12-13, 2001.

studies on performance limitations in cmos dacs - andersson

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