stm32h2x and h73x expanding stm32h7 family with higher … · 5 x 16-bit lp timers 12 x 16-bit tim...

STM32H2x and H73x Expanding STM32H7 Family with higher frequency

Delta STM32H74x/5x and STM32H7Ax/Bx

V1.0

The following slides present an overview of the architecture of the new variants of the STM32H7 family.

1

Architecture Overview

2

1. L1 Data cache = 32Kbyte

Instruction cache = 32Kbyte

2. OTFDEC1/2 are only available

on STM32H73x devices

Explanation on best usage

of this architecture to achieve

high performance available in AN4891

The schematic shows the architecture of the STM32H72/73 lines.The main differences with STM32H74/75 microcontrollers are highlighted in red.Only one bank Flash is available compared to the dual bank flash of STM32H74/75 lines. Two OCTOSPI interfaces support most of the serial external memories.The On-the-fly decryption engine, available in crypto devices (STM32H73), allows the on-the-fly decryption of encrypted content that is then stored in external OCTOSPI memories.The STM32H72/73 offers 192 Kbytes of RAM split in three 64-Kbyte blocks, those blocks can be connected either to AXI or ITCM.More explanations on STM32H72/73/74/75 architecture and performance are available in application note AN4891.

2

STM32H72x/73x3 x power domains, SMPS and LDO,

compatible with the STM32H74x/75x on common packages

1xUSB OTG HS (w/ FS PHY and ULPI)

6xSPI (incl 4xI2S), 5xI²C, 1xTT/FD-CAN + 2xFD-CAN,

5xUART+ 1xULP UART, 5xUSART, Ethernet, MDIO,

HDMI-CEC, SWP, Parallel camera interface

2 x 16-bit ADC + 1x12-bit ADC

2 x Comp, 2 x Op.Amp

1 x Dig. temperature sensorCrypto/Hash

TRNG, anti

tamper, ROP, PC-

ROP, Security

services SFI+SFU

(via RSS*)

FMC (SDRAM, NOR, NAND)

Connectivity

SecurityAnalog

Memory Interfaces

Graphic

Timers including:

4 x 32-bit advanced timers

5 x 16-bit LP timers

12 x 16-bit TIM

2 x W/D

Math Accelerator (Cordic+FMAC)

Timers/Digital

I/OsUp to 133 I/Os

Cortex-M7

550MHz

DP-FPU

MPU

ETM

2 x 32KB Cache

Master DMA, 2 x

DMA and BDMA

Embedded memories

1MB Flash

Single BankSYST.RAM

368KB byte RAM (320

AXI, 32 D2, 16 D3)

ChromART

TCM128KB RAM DTCM

Up to 256KB RAM ITCM (shared with AXI,

Granularity : 64KB)

4KB Bckup RAM

4KB Debug RAM

2 x Octo-SPI w/ On-The-Fly-Decrypt (*)

2xSD/SDIO/MMC

Debug

ETF (buff. 2KB),

DAP

BackupRTC, Back-up

Reg

Power Supply

LDO, SMPS,

USB reg, backup

2 x SAI, DFSDM (8ch./4filters),

4xI2S (Mux w/ SPI),

SPDIF-Rx, 2 x 12-bit DAC

Audio

DMATFT LCD Controller

Key features Performance

RAM re-map ECC on all memories

Multiple high perf ADC

Graphic

Security

Math accelerators

Memory interfaces

Connectivity

Power supply scheme(SMPS or LDO.

Except QFN68-SMPS only)

STM32 DNA (Compatibility, packages,

Ecosyst)

Extended Temp range

support 125C (option**)

(*) : on STM32H73x CPN (Crypto) (**) : CPN in “3” (Ex STM32H725ZGT3)

difference with

STM32H74/75

STM32H7x5 only

The size of the RAMs are globally decreased compared to the STM32H74/75 line.To increase processing performance, the size of both data and instruction caches have been increased from 16 Kbytes to 32 Kbytes. Thanks to the shared RAM, the ITCM, accessible at CPU max frequency, can be increased from 64 Kbytes to 128, 192 or 256Kbytes. Two accelerators have been added: The Cordiccoprocessor accelerates certain mathematical functions, mainly trigonometric ones, and the FMAC accelerator performs arithmetic operation on vectors.The product is available with three different Flash sizes: 1Mbytes, 512 Kbytes and 128 Kbytes configuration.

3

H72/73 vs H7A/7B vs H74/75 features

STH32H74x/75x STH32H7Ax/7Bx STH32H72x/73x

Core

ARM Cortex-M7, DPMPU, FPU,

L1 16KB-D/16KB-I

ARM Cortex-M4, SPMPU, FPU, ART

ARM Cortex-M7, DPMPU, FPU,

L1 16KB-D/16KB-I

-

ARM Cortex-M7, DP FPU, MPU,

L1 32KB-D/32KB-I

-

Operating range

1.62 to 3.6 V and

Tj –40 to +125 ºC

Upto +140ºC with SMPS

VOS1 limited to 125°C

Vcore @VOS0:

Tj limited to 105C,

VDD min 1.7V

No SMPS

1.62 to 3.6 V and Tj –40 to +130 ºC

Vcore @VOS0:

Tj limited to 105C

VDD min 1.7V

1.62 to 3.6 V and

Tj –40 to +125 ºC

Up to 140ºC with SMPS

VOS1 up to 140°C

Vcore @VOS0:

Tj limited to 105C

VDD min 1.7V LDO

VDD min 2.2V SMPS

ARM M7 Frequency / DMIPS480MHz / 1027DMIPS in VOS0

400MHz / 856DMIPS in VOS1





AXI and AHB max frequency 240MHz 280MHz 275MHz

APB max frequency 120MHz 140MHz 137.5MHz

GPIO Up to 168 Up to 168 Up to 133

Em

bed

ded

Mem

ori

es

FLASH 2M 2M 1M

SRAM On AXI 512KB 1024KB 320KB (inc. 192KB shared with ITCM)

SRAM On AHB (D2 Domain) 288KB 128KB 32KB

SRAM On AHB (D3 Domain) 64KB 32KB 16KB

ITCM / DTCM 64KB / 128KB 64KB / 128KB256KB (inc. 192KB shared with AXISRAM) /

128KB

Backup SRAM 4KB 4KB 4KB

RAMECC ECC for all SRAMs ECC only on ITCM, DTCM and L1 cacheECC for all SRAMs (disabled in TCM above

520MHz)

This and the following tables, show a comparison between the STM32H72/73, STM32H7A/7B and STM32H74/75 lines. The main differences are indicated in pink.When the internal temperature does not exceed 105°C, the CPU can run at a frequency up to 550 MHz. At higher temperature, up to 140°C, the CPU can run up to 480 MHz.To reach 550 MHz, the LDO can be used in the same way as for STM32H74/75 devices, but the STM32H72/73 microcontrollers can also use the SMPS regulator instead to improve power efficiency.The STM32H72/73 line has only one bank of flash.The total size of the RAMs connected to the

AXI bus matrix can reach 320 KBytes if the whole 192-KByte memory space shared with ITCM is dedicated to AXI RAM.The size reduction comparisons for the RAMs connected to the AHB bus matrix located in D2 and D3 domain are shown in this table.The RAM error code correction (ECC) is available on all L1 cache, TCM, AXI and AHB RAM. Note that, when the CPU is running above 520 MHz, the ECC on TCM RAM needs to be disabled.

4



Exr.

Mem

. FMC 1 1 1

x-SPI 1x QuadSPI 2x OctoSPI/OTFDEC 2x OctoSPI/OTFDEC

Clo

ck

ma

na

g. Int. Oscillators HSI / RC / CSI / LSI 64 MHz / 48 MHz / 4 MHz / 32kHz 64 MHz / 48 MHz / 4 MHz / 32kHz 64 MHz / 48 MHz / 4 MHz / 32kHz

Ext. Oscillators HSE / LSE 4-50 MHz / 32.768 kHz 4-50 MHz / 32.768 kHz 4-50 MHz / 32.768 kHz

PLLs 3 3 3

Reset

an

d

Po

wer

Ctr

l

Power Domain 3 2 3

SMPS

Low Power modes sleep, stop, standby, vbat sleep, stop, retention, standby, vbat sleep, stop, standby, vbat

STM32H72/73 products embed also up to two OCTOSPI interfaces. An I/O manager supports the multiplexing of two external OCTOSPI memories on a single memory interface. For STM32H73, information protection data can be stored encrypted in the external OCTO SPI memory. When read, those data can de decrypted on the fly.The three power domains are kept identical to STM32H74/75 devices.

H72/73 vs H7A/7B vs H74/75 featuresSTH32H74x/75x STH32H7Ax/7Bx STH32H72x/73x

Tim

ers

Basic / General Purpose / PWM /

RTC2 / 10 / 2 / 1 2 / 10 / 2 / 1 2 / 10 / 2 / 1 + 2 32-bit

High Res / Low Power / Systick 1 / 5 / 2 0 / 3 / 1 0 / 5 / 1

Dis

pla

y /

Gra

ph

ics TFT LCD controller 1 1 1

MIPI-DSI / GFX-MMU/JPEG codec 1 / 0 / 1 0 / 1 / 1 0 / 0 / 0

Chrom-ART Accelerator™ (DMA2D) 1 1 1

DM

A MDMA / Basic DMA / Dual port

DMA1 / 1 / 2 1 / 2 / 2 1 / 1 / 2

Co

mm

un

icati

on

in

terf

ace

USART / UART / LPUART 4 / 4 / 1 5 / 5 / 1 5 / 5 / 1

I2C 4 4 5

SPI / I2S 6 / 3 6 / 4 6 / 4

SAI 4 2 2

SPDIFRX 4 inputs 4 inputs 4 inputs

SWPMI 1 1 1

MDIO 1 1 1

SDMMC 2 2 2

FDCAN / TT-CAN 1 / 1 1/ 1 2 / 1

USB OTG 2 (1HS/FS, 1FS) 1 (HS/FS) 1 (HS/FS)

ETHERNET 1 0 1

HDMI-CEC 1 1 1

DCMI (camera) / PSSI 1 / 0 1/1 (PSSI shares same interface w. DCMI) 1/1(PSSI shares same interface w. DCMI)

Two general-purpose 32-bit timers have been added, the specific high-resolution timer is no more present and only one systick timer is present resulting from the single-CPU architecture.To enhance display and graphic features, TFT LCD controller and Chrom-ART accelerator are still present. MIPI-DSI and JPEG decoder are not available.One UART, one USART, one I2C and one FDCAN have been added. One I2S has been added to one SPI interface, and the parallel synchronous slave interface (PSSI) feature have been added to the Digital camera interface.The number of Serial Audio Interfaces (SAI)

has been reduced to two, one USB Full speed has been removed, keeping only one USB that can be configured in High Speed or Full Speed mode.

6



An

alo

g

16-bit ADC 3 (up to 20 channels) 2 (up to 20 channels) 2 (up to 20 channels)

12-bit ADC (ADC3) 0 0 1 (up to 19 channels)

12-bit DAC 2 channels 1*2 channels + 1*1 channel 2 channels

Comparator 2 2 2

OP amplifier 2 2 2

Temperature Sensor (connected to

ADC)1(ADC3) 1 (ADC2) 1 (ADC3)

Digital Temperature sensor (DTS) 0 1 1

DFSDM 1 (8 ch / 4 filters) 2 (8 ch / 8 filters, 2 ch / 1 filter) 1 (8 ch / 4 filters)

Co

pro FMAC - -

CORDIC - -

Secu

rity

AES / HASH / / /

RNG 1 (seed for NIST standard DRBG module) 1 (NIST certifiable) 1 (NIST certifiable)

OTFDEC 0 2 2

OSPI memory encryption 0 2 2

RDP, WRP, ROP, PC-ROP

Passive Tamper / Active Tamper Up to 3 / - Up to 3 / Up to 2 Up to 2 / -

Security services, RSS, secure only

area

Deb

ug

wth

dg SWD / JTAG / ETM / / 4KB / / 4KB / / 2KB

Watchdog 4 2 2

STM32H72/73 devices embed the same two 16 bits analog to digital converters (ADC) located in D2 power domain. The ADC located in D3 domain has been replaced by a 12bits ADC. The internal temperature can be measured thanks to a sensor connected by default to ADC3 or through a digital sensor to avoid the ADC usage. Two accelerators have been added: The Cordic coprocessor accelerates certain mathematical functions, mainly trigonometric ones, and the FMAC accelerator performs arithmetic operation on vectors.The Random Number Generator, RNG, is a NIST SP 800-90B compliant entropy source.The two embedded On The Fly Decryption

units, OTFDEC, allow the on-the-fly decryption of content stored in external OCTOSPI memories. The procedure to use encrypted data is described in a dedicated application note, AN5281.The OTFDEC feature is only available for STM32H73 crypto devices.The STM32H72/73 are single-CPU core devices, so only one independent watchdog and one window watchdog are included.

7

G01 – Domain 2

(FCPU/2)

GO1 – Domain 3 (Max @ Fmax/2)

OcSPI1OTFD1

Debug subsystem

APB4 (Max @ Fmax/4)

GO2

APB1

Max @ Fmax/4

M0

CTRLCTRL CTRL

FPU

CPU

(500 MHz)

DPU

DCUICU

STB

BIU

NVIC DBG

MPU

TCU

PFU LSU

SQ

AHBD

AHBS

CTI

AHBP

WIC

128kSRAM

RAMITF

(0x0000:0000 -0x0FFF:FFFF)

(0x4800:0000 -0x4FFF:FFFF)

(0x4000:0000 -0x47FF:FFFF)

(0x5800:0000 -0x5FFF:FFFF)

DMA2 USB1ETH1

ETM

64-bit AXI4

32-bit AHB-Lite

32-bit APB3

32/64-bit TCM

8/32-bit ATB

FMC

RTC & backup

I2C2

I2C3

FDCAN2

HDMI-CEC

DAC1&2

UART7

I2C1

UART5

UART4

USART3

USART2

SPDIF-RX1

SPI3/I2S3

TT-FDCAN1

UART8

SPI2/I2S2

LPTimer1

Timer14

Timer13

Timer12

Timer7

Timer6

Timer5

Timer4

(0x4000:7C00-0x4000:7FFF)

(0x4000:7800-0x4000:7BFF)

(0x4000:7400-0x4000:77FF)

(0x4000:6C00-0x4000:6FFF)

(0x4000:A400-0x4000:A7FF)

(0x4000:A000-0x4000:A3FF)

(0x4000:5C00-0x4000:5FFF)

(0x4000:5800-0x4000:5BFF)

(0x4000:5400-0x4000:57FF)

(0x4000:5000-0x4000:53FF)

(0x4000:4C00-0x4000:4FFF)

(0x4000:4800-0x4000:4BFF)

(0x4000:4400-0x4000:47FF)

(0x4000:4000-0x4000-43FF)

(0x4000:3C00-0x4000:3FFF)

(0x4000:3800-0x4000:3BFF)

(0x4000:2400-0x4000:27FF)

(0x4000:2000-0x4000:23FF)

(0x4000:1C00-0x4000:1FFF)

(0x4000:1800-0x4000:1BFF)

(0x4000:1400-0x4000:17FF)

(0x4000:1000-0x4000:13FF)

(0x4000:0C00-0x4000:0FFF)

(0x4000:0800-0x4000:0BFF)

APB

Bridge

APB2

Max @ Fmax/4

SPI1/I2S1

SPI4

Timer17

SPI5

SAI1

Timer15

Timer16

(0x4001:5800-0x4001:5BFF)

(0x4001:5000-0x4001:53FF)

(0x4001:4800-0x4001:4BFF)

(0x4001:4400-0x4001:47FF)

(0x4001:4000-0x4001:43FF)

(0x4001:3400-0x4001:37FF)

(0x4001:3000-0x4001:33FF)

APB

Bridge

USART6

USART1

Timer8/PWM2

(0x4001:1400-0x4001:17FF)

(0x4001:1000-0x4001:13FF

Ext.IT WKUP

SysCfg

RCC

APB

Bridge

Timer1/PWM1

(0x4001:0400-0x4001:07FF)

Timer3

Timer2

(0x4000:0400-0x4000:07FF)

(0x4000:000-0x4000:03FF)

DMA1

LPTimer5

VREF

(0x4001:0000-0x4001:03FF)

(0x4001:0000-0x4001:FFFF)

(0x4000:0000-0x4000:FFFF)

DMA1

(0x4000:0000-0x4000:FFFF)

(0x4001:0000-0x4001:FFFF)

SAI4

(0x4001:7800-0x4001:7FFF)

(0x4000:8800-0x4000:8BFF)

(0x4000:9000-0x4000:93FF)

DMA

Mux2

SPI6/I2S6

S2_64

1M

Flash

(0x1000:0000 -0x1FEF:FFFF)

(0x2400:0000 - 0x2401:FFFF)

Max @ Fmax/2

High Frequency Domain

(Fmax = 550MHz)

(0x2000:0000 -0x2001:FFFF)D1_AHB_AHBS

D1_AHB_AHBP

D1_AHB_AHB34_MEMD3 D1_AHB_AHB4_MEMD3

(0x5800:0000 -0x5BFF:FFFF)D3_AHB_AHB4

D3_AHB_MEMD3

D1_AXI_FLASH_L0

D1_AXI_FMC

D1_AXI_OcSPI1

D1_AXI_MEMD1

D2_AHB_AHB4_MEMD3

D2_AHB_MEMD2_L0

D2_AHB_MEMD2_L1

(0x2000:0000 -0x2FFF:FFFF)(0x5000:0000 -0x57FF:FFFF)

D2_AHB_ART

D2_AHB_AHB1

D2_AHB_AHB2

D1_AHB_AHB12_MEMD2

(0x9000:0000 -0x9FFF:FFFF)

(0x8000:0000 -0x8FFF:FFFF)

(0xC000:0000 -0xDFFF:FFFF)

(0x0800:0000 -0x080F:FFFF)

(0x5200:0000 -0x5FFF:FFFF)

(0x3800:0000 -0x3FFF:FFFF)

(0x6000:0000 -0xDFFF:FFFF)

(0x3800:0000 -0x3FFF:FFFF)

(0x5800:1C00 -0x5800:1FFF)

(0x5800:2400 -0x5800:27FF)

(0x5800:2800 -0x5800:2BFF)

(0x5800:2C00 -0x5800:2FFF)

(0x5800:3000 -0x5800:33FF)

(0x5800:3800 -0x5800:3BFF)

(0x5800:3C00 -0x5800:3FFF)

(0x5800:5400 -0x5800:57FF)

(0x5800:0000 -0x5800:03FF)

(0x5800:0400 -0x5800:07FF)

(0x5800:0C00 -0x5800:0FFF)

(0x5800:1400 -0x5800:17FF)

DFSDM

SWP

OPAMP

(0x4001:0000-0x4001:FFFF)

(0x4000:0000-0x4000:FFFF)

D2_AHB_APB2

D2_AHB_APB1

SDMMC DMA2D

APB3Max@Fmax/4

(0x5200:2000 -0x5200:2FFF)

(0x5200:4000 -0x5200:4FFF)

(0x5200:5000 -0x5200:5FFF)

Graphics

(0x5000:0000 -0x57FF:FFFF)

(0x5800:0000 -0x5FFF:FFFF)(0x3800:0000 -0x3FFF:FFFF)

(0x4000:0000 -0x4FFF:FFFF)

RNG

HASH

3DES/AES

CAMITF

(0x4802:1800 -0x4802:1BFF)

(0x4802:1400 -0x4802:17FF)

(0x4802:1000 -0x4802:13FF)

(0x4802:0000 -0x4802:03FF)

LPUART1

I2C4

LPTimer2

LPTimer3

COMP1&2

LPTimer4

TAMPER VT

GPIOA~H/J~K

CRC

PowerControl

(0x5802:0000 -0x5802:2BFF)

(0x5800:0000 -0x5800:FFFF)

(0x5802:4400 -0x5802:47FF)

(0x5802:4800 -0x5802:4BFF)

(0x5802:4C00 -0x5802:4FFF)

(0x5802:5400 -0x5802:57FF)

(0x5802:5800 -0x5801:5BFF)

(0x3000:0000 -0x37FF:FFFF)

D1_AHB_AHB3

STM32H72x/73x ARCHITECTURE

RAMITF

RAMITF

(0x3880:0000 -0x3880:0FFF)

(0x1FF2:0000 -0x1FF2:0FFF)

(0x0000:0000 -0x0003:FFFF)

DMA

Mux1

(0x4002:0800 -0x4002:0BFF)

(0x4000:8400-0x4000:87FF)USBCR

MDIOS

HSEM

WDGLS_D1

RTC&Backup

APB

Bridge

LTDC(0x5000:1000-0x5000:1FFF)

(0x5000:0000-0x5000:FFFF)

4x64 4x64 4x64 8/(16)x64S5_64 S6_64S3_32 S 4_64

DAP

(0x5C00:0000 -0x5C01:FFFF)

Trace subsystem

TPIU

CTI

ETF

(0x5000:0000 -0x50FF:FFFF)

(0x5100:0000 -0x510F:FFFF)GPVGPV

ADC 1-2 (16bits)

(0x4002:2000-0x4002:23FF)

RAMITF

RAMITF

DBG

MCU

APB

ICN

ITM

DAPBUS

ROM table

System ROM

table 2

System ROM

table 1

AP0

AP1

AP2

Funnel

SWO

(0x4000:9400-0x4000:97FF)

RAMITF(0x4000:A800-0x4000:CFFF)

SD/

MMC

2

DB-SD/MMC2(0x4802:2800 -0x4802:2BFF)

WinWDG_D1(0x5000:3000-0x5000:3FFF)

DB-OcSPI1

DB-SD/MMC1

(0x5200:6000-0x5200:6FFF)

(0x5200:8000-0x5200:8FFF)

TempSensor

(0x5800:4800 -0x5800:4BFF)

(0x5800:4000 -0x5800:43FF)

(0x5800:6800 -0x5800:6BFF)

(0x5802:6400 -0x5802:67FF)

AXI2AHB

(0x1FF0:0000 -0x1FF1:FFFF)

AXI2AHB

Changes STM32H74x/75x versus

STM32H72x/73x

512k

SRAMNew IP or HW in STM32H72x/73x

S 1_32

FLITF

32K32K

(1)

(0x1000:0000 -0x1000:3FFF)

(0x3000:4000 -0x3000:7FFF)

(0x3800:0000 -0x38FF:FFFF)(0x3800:0000 -0x3800:3FFF)

OcSPI2OTFD2D1_AXI_OcSPI2(0x7000:0000 -0x7FFF:FFFF)

OcSPI

IO mgr

(0x5200:B800 -0x5200:BBFF)

(0x5200:BC00 -0x5200:BFFF)

(0x5200:A000 -0x5200:AFFF)

(0x5200:B400 -0x5200:B7FF)

DB-OcSPI2(0x5200:B000-0x5200:B3FF)

ADC 3 (12bits)(0x5802:6000 -0x5802:63FF)

(0x1000:4000 -0x1000:7FFF)

(0x3000:0000 -0x3000:3FFF)

(0x6000:0000 -0x6FFF:FFFF)

USART10

UART9

(0x4001:1C00-0x4001:1FFF)

(0x4001:1800-0x4001:1BFF

FMAC(0x4802:4000 -0x4802:43FF)

I2C5(0x4000:6400-0x4000:67FF)

CORDIC(0x4802:4400 -0x4802:47FF)

Timer23(0x4000:E000-0x4000:E3FF)

Timer24(0x4000:E400-0x4000:E7FF)

FDCAN3(0x4000:D400-0x4000:D7FF)

TSGEN + Funnel removed

DBGMCU register for dual core removed

PSSI(0x4802:0400 -0x4802:07FF)

192kSRAM

RAMITF(0x2402:0000 - 0x2404:FFFF)D1_AXI_MEMD2

(1)Up to 192KB to be shared with ITCM

64kB granularity

MDMA

SyncUp

(0x4000:0000 -0x4FFF:FFFF)

8

FLASH 2MB to 1MB

L1 cache 2x16KB to 2x32KB

System RAM size updated

TIM23 24 added

QSPI to OcSPI subsys updated

1xFDCAN added

UART9 / USART10 added

D3 ADC changed from 16 to 12bits

FMAC & CORDIC addedETM 4kB to 2kB

I2C5 added

SPI6/I2S6 updated

CM4/ART removed

WinWDG_D2 removed

WDGLS_D2 removed

3 down to 2 D2 SRAM layers

HRTIMER removed

DSI removed

USB2 removedJPEG removed

D2 SAI2/SAI3 removed

GPIO I removed

The presentation shows in green the implementation of the IPs added to STM32H74/75 devices. They will be detailed in the next slides.

8

STM32H72x/3x D1 domain, CPU

9

FLASH 2MB to 1MB



TIM23 24 added


1xFDCAN added




I2C5 added

SPI6/I2S6 updated

CM4/ART removed

WinWDG_D2 removed

WDGLS_D2 removed


HRTIMER removed

DSI removed



GPIO I removed

The size of L1 data and instruction cache closely connected to the core have been doubled to 32 Kbytes.The ITCM size is flexible. On top of fixed 64 bytes, 192 Kbytes Of RAM can be connected either to ITCM or AXI SRAM.The CPU and those close RAMs can run up to 550 MHz.The size of RAM dedicated to the debug trace is reduced from 4 Kbytes to 2 Kbytes.

9

(0x5

20

0:1

00

0 -

0x5

20

0:1

FF

F)

(0x5

20

0:0

00

0 -

0x5

20

0:0

FF

F)

(0x5

20

0:7

00

0 -

0x5

20

0:7

FF

F)

(0x0

00

0:0

00

0 -

0x0

00

3:F

FF

F)

(0x2

00

0:0

00

0 -

0x2

00

1:F

FF

F)

D1

_A

HB

_A

HB

S

M1

_3

2

M3_

64

M5_

64

M6

_6

4M

7_6

4

M2_

32

M4

_6

4M

8_6

4

STM32H72x/3x D1 domain, AXI

10

FLASH 2MB to 1MB



TIM23 24 added


1xFDCAN added




I2C5 added

SPI6/I2S6 updated

CM4/ART removed

WinWDG_D2 removed

WDGLS_D2 removed


HRTIMER removed

DSI removed



GPIO I removed

Only one flash memory bank is connected to the AXI matrix.Two slave ports of AXI matrix are used for OCTOPSPI instead of one for the Quad SPI on STM32H74/75 devices. On crypto STM32H73x devices, the OCTOSPI is connected to AXI through the On The Fly Decryption (OTFDEC), it can be activated or not.

10

G01 – Domain 2

(FCPU/2)

APB1

Max @ Fmax/4

(0x0000:0000 -0x0FFF:FFFF)

(0x4800:0000 -0x4FFF:FFFF)

(0x4000:0000 -0x47FF:FFFF)

(0x5800:0000 -0x5FFF:FFFF)

DMA2 USB1ETH1

I2C2

I2C3

FDCAN2

HDMI-CEC

DAC1&2

UART7

I2C1

UART5

UART4

USART3

USART2

SPDIF-RX1

SPI3/I2S3

TT-FDCAN1

UART8

SPI2/I2S2

LPTimer1

Timer14

Timer13

Timer12

Timer7

Timer6

Timer5

Timer4

(0x4000:7C00-0x4000:7FFF)

(0x4000:7800-0x4000:7BFF)

(0x4000:7400-0x4000:77FF)

(0x4000:6C00-0x4000:6FFF)

(0x4000:A400-0x4000:A7FF)

(0x4000:A000-0x4000:A3FF)

(0x4000:5C00-0x4000:5FFF)

(0x4000:5800-0x4000:5BFF)

(0x4000:5400-0x4000:57FF)

(0x4000:5000-0x4000:53FF)

(0x4000:4C00-0x4000:4FFF)

(0x4000:4800-0x4000:4BFF)

(0x4000:4400-0x4000:47FF)

(0x4000:4000-0x4000-43FF)

(0x4000:3C00-0x4000:3FFF)

(0x4000:3800-0x4000:3BFF)

(0x4000:2400-0x4000:27FF)

(0x4000:2000-0x4000:23FF)

(0x4000:1C00-0x4000:1FFF)

(0x4000:1800-0x4000:1BFF)

(0x4000:1400-0x4000:17FF)

(0x4000:1000-0x4000:13FF)

(0x4000:0C00-0x4000:0FFF)

(0x4000:0800-0x4000:0BFF)

APB

Bridge

APB2

Max @ Fmax/4

SPI1/I2S1

SPI4

Timer17

SPI5

SAI1

Timer15

Timer16

(0x4001:5800-0x4001:5BFF)

(0x4001:5000-0x4001:53FF)

(0x4001:4800-0x4001:4BFF)

(0x4001:4400-0x4001:47FF)

(0x4001:4000-0x4001:43FF)

(0x4001:3400-0x4001:37FF)

(0x4001:3000-0x4001:33FF)

APB

Bridge

USART6

USART1

Timer8/PWM2

(0x4001:1400-0x4001:17FF)

(0x4001:1000-0x4001:13FF

Timer1/PWM1

(0x4001:0400-0x4001:07FF)

Timer3

Timer2

(0x4000:0400-0x4000:07FF)

(0x4000:000-0x4000:03FF)

(0x4001:0000-0x4001:03FF)

(0x4001:0000-0x4001:FFFF)

(0x4000:0000-0x4000:FFFF)

DMA1

(0x4000:0000-0x4000:FFFF)

(0x4001:0000-0x4001:FFFF)

(0x4001:7800-0x4001:7FFF)

(0x4000:8800-0x4000:8BFF)

(0x4000:9000-0x4000:93FF)

D2_AHB_AHB4_MEMD3

D2_AHB_MEMD2_L0

D2_AHB_MEMD2_L1

(0x2000:0000 -0x2FFF:FFFF)(0x5000:0000 -0x57FF:FFFF)

D2_AHB_ART

D2_AHB_AHB1

D2_AHB_AHB2

(0x3800:0000 -0x3FFF:FFFF)

(0x6000:0000 -0xDFFF:FFFF)

DFSDM

SWP

OPAMP

(0x4001:0000-0x4001:FFFF)

(0x4000:0000-0x4000:FFFF)

D2_AHB_APB2

D2_AHB_APB1

RNG

HASH

3DES/AES

CAMITF

(0x4802:1800 -0x4802:1BFF)

(0x4802:1400 -0x4802:17FF)

(0x4802:1000 -0x4802:13FF)

(0x4802:0000 -0x4802:03FF)

DMA

Mux1

(0x4002:0800 -0x4002:0BFF)

(0x4000:8400-0x4000:87FF)USBCR

MDIOS

ADC 1-2 (16bits)

(0x4002:2000-0x4002:23FF)

RAMITF

RAMITF

(0x4000:9400-0x4000:97FF)

RAMITF(0x4000:A800-0x4000:CFFF)

SD/

MMC

2

DB-SD/MMC2(0x4802:2800 -0x4802:2BFF)

(0x1000:0000 -0x1000:3FFF)

(0x3000:4000 -0x3000:7FFF)(0x1000:4000 -0x1000:7FFF)

(0x3000:0000 -0x3000:3FFF)

USART10

UART9

(0x4001:1C00-0x4001:1FFF)

(0x4001:1800-0x4001:1BFF

FMAC(0x4802:4000 -0x4802:43FF)

I2C5(0x4000:6400-0x4000:67FF)

CORDIC(0x4802:4400 -0x4802:47FF)

Timer23(0x4000:E000-0x4000:E3FF)

Timer24(0x4000:E400-0x4000:E7FF)

FDCAN3(0x4000:D400-0x4000:D7FF)

PSSI(0x4802:0400 -0x4802:07FF)

STM32H72x/3x D2 domain

11

FLASH 2MB to 1MB



TIM23 24 added


1xFDCAN added




I2C5 added

SPI6/I2S6 updated

CM4/ART removed

Removed WinWDG_D2 & WDGLS_D2


HRTIMER removed

DSI removed

USB2 removed

JPEG removedD2 SAI2/SAI3 removed

GPIO I removed

In D2 domain, two 32bit timers , one FDCAN and one I2C have been added on APB1 bus.One USART and one UART have been added to APB2 bus.The two accelerators CORDIC and FMAC and the PSSI have been added to AHB2 bus

11

4k

SR

AM

AP

B

Brid

geD

FT

RE

G

16

k

SR

AM

STM32H72x/3x D3 domain

12

FLASH 2MB to 1MB



TIM23 24 added


1xFDCAN added




I2C5 added

SPI6/I2S6 updated

CM4/ART removed

Removed WinWDG_D2 & WDGLS_D2


HRTIMER removed

DSI removed

USB2 removed

JPEG removedD2 SAI2/SAI3 removed

GPIO I removed

In D3 domain, the 16 bit ADC has been replace by lowpower 12 bit ADC. The SPI6 has now a I2S featureincluded.

12

13

PWR Supply

Internal power supervisor:

For power-on: VPOR max: 1.71V (see datasheet)

For power-down: VPDR max: 1.68V

Below 1.71V the internal power supervisor needs to be switched

off setting the PDR_ON pin to VSS and an external power

supervisor needs to be used.

Note: PDR_ON pin is not available in all packages.

In such cases the internal power supervisor can’t be switched

off with consequence of a minimum VDD supply of 1.71V

See RM0468

System supply configuration for SMPS devices

VDD: 1.62V – 3.6V (typical 3.3V)

System supply configuration for devices without SMPS

The slide explains how to supply the device, the different possible configurations, the internal generated supplies and the different power modes.The STM32H72/73 line has the same power supply scheme and power modes as STM32H74/75 line. The STM32H725/735/730 lines embed also a Switch Mode Power Supply (SMPS) step down converter to improve power efficiency. All STM32H72x/73x devices embed a Low Drop Output (LDO) regulator except for the 68-pin package which embeds only the SMPS. To provide the core supply, several system supply configurations are possible.The digital power can be supplied either by the internal linear voltage regulator, the embedded SMPS step down converter or directly by an external supply voltage in regulator bypass mode. The SMPS step down converter can also be cascaded with the linear voltage regulator.

13

It’s important to connect the device according to these schematics to insure a correct power-up of the device.For devices not supporting the SMPS feature, only the LDO regulator is available. In this case two configurations are possible and the VDDLDO regulator supply is directly provided through VDD without a dedicated package pin.

13

Power scale extension

Power Scale CPU max

frequency

( MHz)

VOS0 & ECC disabled on

TCM

550

VOS0 520

VOS1 480

VOS2 300

VOS3 170

Power scale Vcore source Maximum Tj Minimum VDD

SMPS 2,2

LDO 1,7

SMPS supplies LDO 3

external (Bypass) 1,62

140 2,2

1,62

LDO 1,62

SMPS supplies LDO 2,3


SMPS 140 1,62

LDO 1,62



SMPS 140 1,62

LDO 1,62



SMPS 140 1,62

125 2

105 1,62

125 3

105 2,3

external (Bypass) 125 1,62

VOS3125

SVOS4/SVOS5

LDO

SMPS supplies LDO

VOS2125

VOS0 105

VOS1

SMPS

125

The STM32H72/73 line domain usage of some power scale has been increased compared to STM32H74/75 line.SMPS use is available for VOS0. In this domain, the CPU can reach its highest speed, which also means the highest dynamic current consumption. Using the SMPS instead of LDO reduces the power consumption; reducing the power consumption helps reduce the internal temperature, which in turn reduces the internal leakage in a virtuous circle.In VOS1, the SMPS can be used with a junction temperature up to 140°C, which is possible only from VOS2 for STM32H75. It means that for this high temperature the maximum CPU speed is 480 MHz for the STM32H72/73 line instead of 300 MHz for the STM32H75 line.SVOS4 and SVOS5 can be used 125°C instead of

14

105°C, which eases the usage of those low power modes at high temperature.The maximum frequency in VOS3 is decreased from 200 MHz to 170 MHz.

14

Consumption

15


RU

N(L

DO

/SM

PS

) 550 MHz - - 145 / 81 mA

480 MHz 148 / - mA - 125 / 72 mA

400 MHz 110 / 58 mA - 90 / 47 mA

280 MHz 71 / 35 mA 70 / 34 mA 58 / 29 mA

60 MHz 16 / 7.5 mA 12.5 / 5.5 mA 13.5 / 6.5 mA

LP

mo

de

(LD

O/S

MP

S) D1/D2/D3 stop (CD/SRD

Dstop2)

SVOS3 2.8 / 1.0 mA 0.115 / 0.046 mA 1.15 / 0.25 mA

SVOS5 1.3 / 0,36 mA 0.09 / 0.032 mA 0.5 / 0.05 mA

D1/D2/D3 standby (CD/SRD standby) 2,0 µA 2,2 µA 2.5 µA

VBAT 0.03 µA 0.03 µA 0.02 µA

This table shows typical consumption for LDO slash SMPS for voltage supply of 3.3V. Comparison of line 550 MHz and 480 MHz shows that STM32H72/73 line reaches a higher performance with a slight consumption decrease using LDO. This becomes a huge decrease when using SMPS.

15

Bank swapping for external memory

16

TYPE

-

CACHE

attribute

me

mo

ry Write through

write back

write allocate

de

vic

e

Modifications regarding internal RAM memories and peripherals imply a modification of the memory mapping.Due to the presence in default mapping of OCTOSPI2 in place of FMC’s SDRAM Bank1, the STM32H72/73 line does not propose the remap of the FMC’s SRD bank2. Only the FMC’s SDRAM bank1 can be remapped.

16

Releasing Your Creativity

17www.st.com/STM32H7

community.st.com@ST_World/STM32

Thank you!

17

stm32h2x and h73x expanding stm32h7 family with higher … · 5 x 16-bit lp timers 12 x 16-bit tim...

Documents