(A) 240 V (B) 120 V

(C) 60 V (D) 30 V

Signature of Invigilator Signature of Examiner Marks Obtained:

IIB. Tech II MidTerm Examinations: Objective Exam

Answer the following Questions. Each question carries mark.

NAME: ROLL NO.

4. The condition for crictically damping in series RLC circuit

(A) R=2LC (B) R= 4 L/C (C) R^2 =4 L/C (D) R^2 =4 LC[ ]

5. A series RC circuit having R=15 ohms and L= 0.2F , a constant voltage of 15V is applied at t=othe expression for i(t) is [ ](A) 1.5e^(-t/3) (B) 15 e^(-t/3) (c) 1.e^(-t/3) (D) e^(-3t)

6. The time constant of the circuit having R=5ohms L=0.2H is

(A) 2sec ( B) 1sec (C) 0.04 sec (D) 2.5Sec

[ ]7. Max power transfer occur at

(A) 50% efficiency (B) 100% efficiency (C) 20% efficiency (D) 25% efficiency[ ]

8. Reciprocity theorem is applicable to(A) linear network only ( B) Bi-lateral network only (C) linear/ bilateral networhonly (D) neather of the two

[ ]9. mutual inductance is a property associate with

(A) only one (B) two or more coil (C) two or more coil with magnetic (D) none[ ]

11. For the below fig the polarity of the mutual voltage is

[ ][ ]

(A) Positive (B) Negative ( C) none

12.The Laplace-transformed equivalent of a given network will have (8/5) F capacitor replaced by [ ](A) 8/5 S (B) 5/8 S (C) 8/5S (D) 5/8S

10. The effictive value of an triangular wave of alternative quaninty for peak value a is

(A) a/2 (B) a (C) a/v3 (D) av3

Time: 20 Minutes Subject: Max Marks: 10 S.T.L.D Branch:E.E.EAY 2014-2015

1. The modulus of a 4-bit Ring Counter is (a) 4 (b) 8 (c) 16 (d) 15

2. The modulus of a 4-bit Johnsons Counter is (a) 4 (b) 8 (c) 16 (d) 15

3. How many 21 MUXS required to implement 10241 MUX(a) 10 (b) 11 (c) 1023 (d) 1024

4. The Output Y of a 2-bit Comparator is logic 1 whenever the 2-bit input A is greater than 2-bit inputB .The Number of combinations for which the logic 1 is -(a) 4 (b) 5 (c) 10 (d) 6

5. To count from 0 to 1024 how many number of flip-flops are required(a) 11 (b) 10 (c) 12 (d) 1023.

6. A 4 bit ripple counter and a 4 bit synchronous counter are made by flips flops having a propagation delayof 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and Srespectively, then(a) R=10ns, S=40ns (b) R=40ns, S=10ns (c) R=10ns ,S=10ns (d) R=40ns, S=40ns

7. The frequency of the pulse at z in the network shown in fig is -

11. The circuit shown in fig. P4.3.11 is

(A) a MOD2 counter

(B) a MOD3 counter

(C) generate sequence 00, 10, 01, 00.....

(D) generate sequence 00, 10, 00, 10, 00 ......

12. The counter shown in fig. P4.3.12 is a

(A) MOD8 up counter

(B) MOD8 down counter

(C) MOD6 up counter

(D) MOD6 down counter

13. The counter shown in fig. P4.3.13 counts from

(A) 0 0 0 to 1 1 1 (B) 1 1 1 to 0 0 0

(C) 1 0 0 to 0 0 0 (D) 0 0 0 to 1 0 0

14. Themod-numberoftheasyncr

shown in fig. P4.2.13 is

(A) 24 (B) 48

(C) 25 (D) 36

15. The frequency of the pulse at z in the network

shown in fig. P4.3.15. is

(A) 10 Hz (B) 160 Hz

(C) 40 Hz (D) 5 Hz

16. The three-stage Johnson counter as shown in fig.

P4.2.16 is clocked at a constant frequency of fc from the

starting state of Q Q Q2 1 0 101. The frequency of output

Q Q Q2 1 0 will be

Chap 4.3Sequential Logic Circuits

Page

218

J

C

Q

Q K

CLK

J

B

Q

Q K

J

A

Q

Q K

1

1

Fig.P4.3.12

D11

X

YQ1

Q1

D2 Q2

Q2

(B)

D11

X

YQ1

Q1

D2 Q2

Q2

(C)

D11 1

X

YQ1

Q1

D2 Q2

Q2

(D)

T

A B

Q

Q

CLK

T Q

Q

CLK

Fig.P4.3.11

CLR

JC

C

C K

JB

B

B K

JA

A

A KCLR CLR

Fig.P4.3.13

All J.K. input are HIGH

J Q0

K CLR

J Q1

K CLR

J Q2

K CLR

J Q3

K CLR

J Q4

K CLR

Fig.P4.3.14

Fig.P4.3.15

J1 Q1

Q1K1

J0 Q0

Q0K0

J2 Q2

Q2K2

CLK

Fig.P4.3.16

GATE EC BY RK Kanodia

www.gatehelp.com

(a) 10 HZ (b) 160 HZ (C) 5 HZ (d) 40 HZ

8. The ripple counter shown in figure is made up of negative edge triggered J-K flip-flops. The signal levelsat J and K inputs of all the flip flops are maintained at logic 1. Assume all the outputs are cleared justprior to applying the clock signal module no. of the counter is:-

NOTES

Chap 8Analog and Digital

Electronics

Page 504

MCQ 8.98*

The ripple counter shown in figure is made up of negative edge triggered J-K flip-flops. The signal levels at J and K inputs of all the flip flops are maintained at logic 1. Assume all the outputs are cleared just prior to applying the clock signal.

module no. of the counter is:

(A) 7 (B) 5

(C) 4 (D) 8

MCQ 8.99*

In Figure , the ideal switch S is switched on and off with a switching frequency 10f kHz= . The switching time period is T t t s.ON OFF = + The circuit is operated in steady state at the boundary of continuous and discontinuous conduction, so that the inductor current i is as shown in Figure. Values of the on-time tON of the switch and peak current ip . are

(a) 7 (b) 5 (c) 8 (d) 4

9. How many 38 decoders required to implement 416 decoder(a) 3 (b) 2 (c) 4 (6)

10. The type of Flip-Flop used in a shift Registers is (a)SR Flip-Flop (b) D Flip-Flop (c) T Flip-Flop (d) JK Flip-Flop

11. The number of T flip-flops required to generated a periodic sequence 0 2 5 6 3 4 0 is(a)2 (b) 4 (c) 3 (d) 2

12. A Flip-Flop is a Multi-vibrator(a) Mono-Stable (b)Astable (c) both (d) Bi-stable

1

[ ][ ]

[ ]

[ ][ ][ ]

[ ]

[ ]

[ ]

[ ][ ][ ]

1

2

3

4

5

6

7

8

9

10

11

12

10-Bit

Ring Counter4-Bit Parallel

Counter

Mod-25

Ripple Counter4-Bit Johnson

Counter

w x y z

160 kHZNOTES

Chap 8Analog and Digital

Electronics

MCQ 8.98*

13. Number of parity bits required for 13-bits data word is (a)5 (b) 3(c) 4 (d)2

14. In Hamming Code Sequence number of parity bits are 6 for a range of data bits(a)58-120 (b) 25-57 (c) 12-126 (d) 5-11

15. In T Flip-Flop ,the output toggles when input T is (a) 0 (b) 0 or 1 (c) 1 (d) dont care

16. The Characteristic Equation Q(t+1) for SR Flip-Flop is

17. The Characteristic Equation Q(t+1) for JK Flip-Flop is

18. The Characteristic Equation Q(t+1) for T Flip-Flop is

19. The Characteristic Equation Q(t+1) for D Flip-Flop is

20. Race Around Condition will happen in Flip-Flop

2

[ ][ ][ ]

13

14

15

1. (a) Design a 4 bit binary UP/DOWN ripple counter.

(b) Draw the neat diagram of 4-bit Johnson counter and draw the relevant output wave forms.

2. Complete the timing diagram for the circuit given below.SYNCHRONOUS (CLOCKED) SEQUENTIAL CIRCUITS 257

3. Complete the timing diagram for this circuit.

T D

CLK

Q Q

T

CLK

Q

4. Design a circuit that implements the state diagram

1/1 S0 S1

S21/1

1/0

0/0

0/1

0/1

5. Design a circuit that implements the state diagram

S0

0/0

1/0

S40/0

1/1

S3

S2

S1

0/1 0/1

1/1

0/11/0

1/0

3. (a) Draw the neat diagram of locked JK flip-flop using NAND gates and give its truth table.

(b) Give the excitation table for T flip-flop,SR flip-flop,JK flip-flop.

4. (a) Design 32:1 multiplexer using 16:1 multiplexers.

(b) Implement the following combinational circuit using 4 to 16 line decoder.Y1 = m(2,3,9).Y2 = m(10,12,13).Y3 = m(2,4,8).Y4 = m(1,2,4,7,10,12).

5. (a) List the PLA program table for combinational circuit that squares a 3-bit number.

(b) What is ROM ?Describes using the block diagram, what size ROM would it take to implement binary multiplierthat multiplies two binary numbers.

1

II B.TECH II MID TERM EXAMINATIONS : DESCRIPTIVE EXAM AY:2014-2015 SET-1

TIME :90 MIN SUBJECT ::STLD BRANCH :EEE MAX.MARKS::30

ANSWER ANT THREE OF THE FOLLOWING QUESTIONS.

1. (a) Design and implement MOD-6 synchronous counter using JK flip-flop.

(b) Draw the logic diagram of 4-bit shift register.Explain how Shift-left and Shift-Right operations are performed.

2. Complete the timing diagram for the circuit given below.SYNCHRONOUS (CLOCKED) SEQUENTIAL CIRCUITS 257

3. Complete the timing diagram for this circuit.

T D

CLK

Q Q

T

CLK

Q

4. Design a circuit that implements the state diagram

1/1 S0 S1

S21/1

1/0

0/0

0/1

0/1

5. Design a circuit that implements the state diagram

S0

0/0

1/0

S40/0

1/1

S3

S2

S1

0/1 0/1

1/1

0/11/0

1/0

3. (a) Draw the neat diagram of locked JK flip-flop using NAND gates and give its truth table.

(b) Give the excitation table for T flip-flop,SR flip-flop,JK flip-flop.

4. (a) Design 32:1 multiplexer using 16:1 multiplexers.

(b) Implement the following combinational circuit using 4 to 16 line decoder.Y1 = m(2,3,9).Y2 = m(10,12,13).Y3 = m(2,4,8).Y4 = m(1,2,4,7,10,12).

5. (a) List the PLA program table for combinational circuit that squares a 3-bit number.

(b) What is ROM ?Describes using the block diagram, what size ROM would it take to implement binary multiplierthat multiplies two binary numbers.

2

II B.TECH II MID TERM EXAMINATIONS : DESCRIPTIVE EXAM AY:2014-2015 SET-2

TIME :90 MIN SUBJECT ::STLD BRANCH :EEE MAX.MARKS::30

ANSWER ANT THREE OF THE FOLLOWING QUESTIONS.

STLD-MID-2 (2).pdfSTLD