Stave Hybrid/Module Status

ATLASATLASATLASATLAS

Modules

Stave Module Building

2

Seven sites making progress with hybrid and module assembly/bonding/testingHybrids

indicates proficiency indicates in process of becoming proficient

Plan on 2-3 months for Glasgow to make electrical modules

ATLASATLASATLASATLAS Stave Hybrid/Module Status• Since AUW meeting:

– More hybrids assembled/bonded/tested (Cambridge, Freiburg, Liverpool, Santa Cruz)

– More modules assembled/bonded/tested (Freiburg, Liverpool)

– Noise sources understood at Cambridge, LBL, Santa Cruz, Freiburg

– Two more stavelets in process• Modules for US stavelet from UCSC/LBL

• Modules for UK stavelet from Liverpool/Cambridge

– Glasgow has full tooling set, starting mechanical trials

– DESY wire bonding restricted until new machine can be purchased

• Working through hybrid/modules aspects for using 130 nm ASICs (next slides)– 4 row bonding test pieces

– Hybrid/module layout

3

Cambridge module

Santa Cruz module

4 row bonding test pieces

• AL on glass pieces which mimic proposed bond pads on ABCn130 and new sensors

• Can be spaced relative to each other to see if planned bonding is ok and how tight placement tolerances need to be

• Each wafer allows 14 samples of each design

4 designs:• ABCn layout with 200m long pads• ABCn layout with 117 m long pads• Sensor Pads (no DC pads)• Sensor Pads (with DC pads)

Sensors

Two variants test how much extra length needed for DC probe pad influenece bonds

ABCn

Two variants test if extra bond pad length is needed for 2 bonding attempts

Status

• Glasgow currently fabricating 10 wafers

• First 2 (diced) expected to be in Liverpool for the start of next week

• Will distribute on request to rest of community

Doubling trigger speed/bandwidth• Ashley has been working on a first layout of the hybrid for the 130

nm ASIC set– Trying to determine if certain bonding pad locations make things easier and

determine “minimum” sizes of ABCn/HCC with respect to bonding

• During the ITK-SC meeting on triggers, it was suggested that doubling bandwidth to allow for 200 kHz triggering would be useful– As suggested by Mitch, we can active this by doubling the data links on

hybrid (5 chips per link) and HCC, and doubling the data output speed from the HCC to the EOS(SCA/GBT)

• This allows able the ABCn to run at the currently planned speeds

– To keep redundancy of data links, this requires connection of the 1st,5th,6th,10th in the chain to the HCC (data/Xon)

ABC130 Hybrid – Hypothetical layout

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My assumptions•Sensor geometry: 97.54mm x 97.54mm•ABC130: 7.5mm x 6mm•HCC: 5mm x 5mm (this may shrink a bit)

•2.5 mm x 3.5 mm minimum for straight bonding

Hybrid Detail•Hybrid: 16mm x 97.5mm

•Sits within the area of the sensor•No overhang of sensor edges

•Ideally 3 layer build (top – down)•Layer 1: Component + trace•Layer 2: Trace + VDD•Layer 3: Ground

•4 layer build might be easier for manufacture

•Would be narrower so material increase would be minimal

•Typically 100µm track & gap•Two data loops

•5 x ABC130 per data loop•Readout each end of a

column for redundancy16mm

48.75mm

64.75mm

Data Loop 0

Data Loop 1

Data I/O (Service side)

Power Entry

0

1

2

3

4

5

6

7

8

9

A.Greenall (18/01/2012)

Data/Xon• Ash found you could double the

links without increasing the number of layers, changing track/gap or via sizes, etc. by moving the data/Xon bond pads to the back corners of the ASIC and widening the hybrid to take on the extra traces to the HCC– Data/Xon would be linked on hybrid

• Added benefit of removing chip-to-chip bonds so only 2 sides of ABCn bonded to hybrid

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Chip 5 Chip 6

Multidrop bus (clock, cmd, trigger)

Data/Xon

Would it be ok to move the locations of data/Xon from the sides to the bottom of the ASICs?

Chip Detail

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FE bonds only (4 rows of 64)

Token and

Data (2

pairs)

Token and

Data (2

pairs)

BCO, L1, Com

, Clk, Reset (5 pairs)

Ground, Power, Chip ID

Old

FE bonds only (4 rows of 64)

Token and

Data (2 pairs)

Token and

Data (2 pairs)

BCO, L1, Com

, Clk, Reset (5 pairs)

Ground, Power, Chip ID

New Proposal

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ABC130 Hybrid – Power entry endA

BC

13

01

AB

C1

30

0

•Common bus termination – as yet unconnected•With 3 layer build not easy to do

•3 proposals:1.Use top layer to connect to common bus

•Vias would be within the ABC130 0 chip land.2.Use embedded termination within the ABC130

•ASIC designers believe this isn’t an issue3.Go to 4 layer build

•We propose going with embedded termination in the ASICs as it can be disabled

A.Greenall (18/01/2012)

Would people be ok with termination of hybrid multi-drop buses in chip instead of using discrete components?

ABCN13 Module Wire-bonding

For the module group

• The standard module is really nice. One hybrid type for SS and LS, two module assembly plate (SS and LS).

• Either symmetric layout forces two hybrid types, 2 HCC types and 2 pickup tools

• So I prefer the standard, but causes restrictions on bus cables, module mounting and EOS possibly.

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ABC130 Hybrid – Layer DetailLayer 1 Layer 2 Layer 3

GroundVDD

9mm

Common bus to ALL

asics(BCO, COM, DRC, L1 &

RES)

ABC130 data paths to

HCC

NTC

A.Greenall (18/01/2012)