statistical gate delay calculation with crosstalk alignment consideration andrew b. kahng, bao liu,...
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Statistical Gate Delay Calculation with Crosstalk Alignment Consideration
Statistical Gate Delay Calculation with Crosstalk Alignment Consideration
Andrew B. Kahng, Bao Liu, Xu Xu
UC San Diego
http://vlsicad.ucsd.edu
OutlineOutline
SSTA Background
Problem formulation
Method: theory and implementation
Experiment
Summary
Background: VariabilityBackground: Variability Increased variability in nanometer VLSI designs
Process: OPC Lgate CMP thickness Doping Vth
Environment: Supply voltage transistor performance Temperature carrier mobility and Vth
These (PVT) variations result in circuit performance variation
p1
p2
PVT Parameter Distributions
d1
d2
Gate/net DelayDistribution
Background: Timing AnalysisBackground: Timing Analysis
Min/Max-based
Inter-die variation
Pessimistic
Corner-based
Intra-die variation
Computational expensive
Statistical
pdf for delays
Reports timing yield
CLK
DQ combinationallogic
FF FF
max
max
min
Background: SSTABackground: SSTA Represent signal arrival times as random variables
Block-based Each timing node has an arrival time distribution Static worst case analysis Efficient for circuit optimization
Path-based Each timing node for each path has an arrival time distribution Corner-based or Monte Carlo analysis Accurate for signoff analysis
B
CA
D
I1
gate delay pdfs
Arrival time pdfArrival
time pdf
Multiple-Input SwitchingMultiple-Input Switching
Simultaneous signal switching at multiple inputs of a gate leads to up to 20%(26%) gate delay mean (standard deviation) mismatch [Agarwal-Dartu-Blaauw-DAC’04]
Gate delay
Prob
abil
ity
Crosstalk Aggressor AlignmentCrosstalk Aggressor Alignment
We consider an equally significant source of uncertainty in SSTA, which is crosstalk aggressor alignment induced gate delay variation
MIS
CAA
Problem FormulationProblem Formulation Given
Coupled interconnect system Gate input signal arrival time distributions
Find Gate output signal arrival time distributions
We present signal arrival times in polynomial functions of normal distribution random variables
E.g., for first order approximation of two input signal arrival times, their skew (crosstalk alignment) is given in normal distribution random variables with correlation taken into account
xi = fi(r1, r2, …)ri ~ N(i, 3i)
x1 ~ N(1, 31) x2 ~ N(2, 32) x’=x2-x1 ~ N( ’=2-1, 3’=3(1
2+22+corr)1/2)
OutlineOutline
SSTA Background
Problem formulation
Method: theory and implementation
Experiment
Summary
Driver Gate Delay as a Function of Crosstalk AlignmentDriver Gate Delay as a Function of Crosstalk Alignment
16X inverters driving 1000um global interconnects in 70nm technology
Driver Gate Delay as a Function of Crosstalk AlignmentDriver Gate Delay as a Function of Crosstalk Alignment
More complex than the timing window concept
Can be computed by simulation or delay calculation
Approximated in a piece-wise quadratic function:
d x t
a a x a x t x t
d t x t
b b x b x t x t
d t x
2 0
0 1 22
0 1
0 1 2
0 1 22
2 3
1 3
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Closed-Form Driver Gate Delay DistributionClosed-Form Driver Gate Delay Distribution
For a normal distribution crosstalk alignment x’
P D g
erft
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erft
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Transform probabilities via inverse functions
Closed-Form Driver Gate Output Signal Arrival Time DistributionClosed-Form Driver Gate Output Signal Arrival Time Distribution
For a normal distribution crosstalk alignment x’
P y e F y t a a F y t a a
e F y t b b F y t b b
P x y d erft y d
erf
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21 3 0 1 1 2 0 1
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1 2 1 0
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1 1 20 2 1 2
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Consider correlation via conditional probabilities
Statistical Gate Delay Calculation for Coupled Interconnect LoadStatistical Gate Delay Calculation for Coupled Interconnect LoadInput: Coupled interconnects
gate input signal arrival time distributions
process variations
Output: Gate output signal arrival time distributions
1. Driver Gate delay calculation for sampled crosstalk alignments
2. Approximate driver gate delay in a piece-wise quadratic function of crosstalk alignment
3. Compute output signal arrival time distribution by closed-form formulas
4. Combine with other process variations
Extension to Multiple Aggressors Extension to Multiple Aggressors
In general, superposition does not apply for multiple aggressors because of driver output resistance variation
We need to Extract empirical functional relationships between
driver gate delay and aggressors
Compute gate output signal arrival time distributions
Superposition applies for long interconnects with large drivers of small output resistance
Extension to Multiple Variations Extension to Multiple Variations
Correlated variation sources Reduce the number of variations, via PCA
Extract empirical functional relationships between gate delay and variations
Compute gate output signal arrival time distributions
Independent variation sources Applying Superposition for improved efficiency
total = i i
2total = i
i
Implementation Implementation
STA-SI goes through an iteration of timing window refinement for reduced pessimism of worst case analysis
SSTA-SI goes through an iteration of signal arrival time pdf refinement with reduced deviations
Runtime AnalysisRuntime Analysis
Driver gate delay calculation for N sampled crosstalk alignment takes O(N) time, where N = min(t3-t0, 6 of crosstalk alignment) / time_step
Fitting takes O(N) time
Computing output signal arrival time distribution takes constant time, e.g., updating in an iterative SSTA
OutlineOutline
SSTA Background
Problem formulation
Method: theory and implementation
Experiment
Summary
Experiment SettingExperiment Setting
16X inverter drivers
Coupled global interconnects in 70nm Berkeley Predictive Technology Model
Extracted coupled interconnects of 451 resistors and 1637 ground and coupling capacitors in 130nm industry designs
70nm L (um) W(um) S(um) T(um)
global 1000 0.45 0.45 1.20
intermediate 200 0.14 0.14 0.35
local 30 0.10 0.10 0.20
Driver Gate Delay DistributionDriver Gate Delay Distribution
For a pair of 1000um coupled global interconnects in 70nm BPTM technology, with 10, 20, 50 and 100ps input signal transition time, and crosstalk alignment in a normal distribution N(0, 10ps)
Driver Gate Delay Standard Deviation due to Varied Gate LengthDriver Gate Delay Standard Deviation due to Varied Gate Length
For a pair of 1000um coupled global interconnects in 70nm BPTM technology, with 10, 20, 50 and 100ps input signal transition time, and wire width variation in a normal distribution N(0, 15%)
Driver Gate Delay with Gate Length and Crosstalk Alignment VariationsDriver Gate Delay with Gate Length and Crosstalk Alignment Variations
16X inverter drivers of coupled 70m BPTM global interconnects
1. No variation
2. Gate length variation
3. Crosstalk alignment variation
4. Superposition results of both variations
5. SPICE results of grounding coupling capacitors and both variations
6. Our results of both variations
-0.0956.22124.4126.2956.2756.2056.2656.24-1050
2.202.48139.25.812.431.312.11-
1.762.45141.35.812.411.252.11--0.1347.72154.7121.7247.7847.7147.7547.74020
1.882.39147.45.812.351.152.10--0.1442.66181.4120.2342.7242.6542.6742.66100
6-4%65-4%54321’Tr
Driver Gate Delay with Gate Length and Crosstalk Alignment VariationsDriver Gate Delay with Gate Length and Crosstalk Alignment Variations Superposition of gate length and crosstalk alignment
variations matches within 2.20% of SPICE Monte Carlo results
Assuming no crosstalk alignment (e.g., grounding all coupling capacitors) results in 159.4%(147.4%) mismatch in mean (standard deviation) of driver gate delay variation
Driver Gate Output Signal Arrival Time DistributionDriver Gate Output Signal Arrival Time Distribution
For a pair of 1000m coupled global interconnects in 70nm BPTM technology, with 10, 20, 50 and 100ps input signal transition time, and crosstalk alignment in a normal distribution N(0, 10ps)
Driver Gate Output Signal Arrival Time DistributionDriver Gate Output Signal Arrival Time Distribution
% diff ModelSPICEModelSPICE
-2.03 1.72173.8 53.83177.4 52.9274.13 23.0774.3 23.19200 200
0.71 –2.16113.7 24.43112.9 24.9761.85 15.8761.38 16.03100 100
-1.65 3.8677.3 12.6678.6 12.1952.74 8.4252.83 8.8650 50
3 Tr(ps)
Output Delay
Test case 2: coupled interconnects in a 130nm industry design
Test case 1: 1000m interconnects of 70nm BPTM technology
% diff ModelSPICEModelSPICE
-1.36 –0.93297.8 65.87301.9 66.49198.73 2.51198.87 2.52200 200
-2.57 1.61291.8 33.49299.5 32.96197.68 1.52198.01 1.5100 200
-1.03193.6 16.24195.4 16.4168.84 0.8169.67 0.8150 50
3 Tr(ps)
Output Delay
OutlineOutline
SSTA Background
Problem formulation
Method: theory and implementation
Experiment
Summary
SummarySummary
SSTA must consider SI effects!
We take crosstalk aggressor alignment into account in statistical gate delay calculation We approximate driver gate delay in a piecewise
quadratic function of crosstalk aggressor alignment We derive closed-form formulas for driver gate delay and
output signal arrival time distribution for given input signal arrival times in polynomial functions of normal distributions
Our experiments show that neglecting crosstalk alignment effect could lead to up to 159.4% (147.4%) mismatch of driver gate delay means (standard deviations), while our method gives output signal arrival time means (standard deviations) within 2.57% (3. 86%) of SPICE results
Thank you !Thank you !