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Statistical Design for Digital Circuits:Statistical Static Timing Analysis (SSTA)
Ulf SchlichtmannInstitute of Electronic Design Automation
Technische Universitaet MuenchenMunich, Germany
Special Session:DFM/DFY Design for Manufacturability and Yield –
influence of process variations in digital, analog and mixed-signal circuit design.
2
Outline
Motivation
Key Concepts and Challenges– Statistical Cell Delay Modeling
– Statistical Timing Propagation
Design Flow Integration and Outlook
3
STA Basics
D Q
CP
FF1
CLK
D Q
CP
FF2LOGIC
Clock Path
Data Path
Timing Check
Timing Checks:Setup time checkHold time check
4
Traditional Variation Sources
Variations
Manufacturing Operating Environment
die-to-die (wafer-to-wafer, lot-to-lot) - Voltage- TemperatureLeff, Tox, Vth, C, R, etc.
Leff
Leff
Leff
Leff
Die A
Die B
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Corner-Based Static Timing Analysis
Longest paths: worst case (WC) operating conditions (Setup)
delaytmax2tmin2
BC WCPDF
tmax1
tmax2
tmin1
tmin2delaytmax1tmin1
BC WCPDF
Shortest paths: best case (BC) operating conditions (Hold)
6
Variation Sources Today
Variations
Manufacturing Operating Environment
die-to-die(D2D)
within-die(WID) Global
- Voltage- Temperature
Local- IR Drop
- Hot Spot
- Crosstalk
Leff
Leff
Leff
Leff
Die A
Die B
7
Variation TrendsProcess variations continue to increase
Within-die variations become more significantLeff
Tox
Vth
15%
30%
45%
60%
Year1997 1999 2002 2005 2006
3σ/nominal
15%
30%
45%
60%
Year1997 1999 2002 2005 2006
Within-die/total
3σ parameter total variation relative to nominal value
Percentage of total variation accounted for by within-die variations
[Nassif, CICC 2001]
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Within-Die EffectsWithin-die variations can affect the delay of paths differently
e.g. data path becomes slower / clock path becomes faster
delaytmax2tmin2
WCPDF
tmax1
tmax2
delaytmax1tmin1
WCPDF
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STA – Dealing with variations
Increase number of corners
OCV-factor (on-chip variation)
Statistical STA
D Q
CP
FF1
clk
D Q
CP
FF2LOGIC( tDATA )
Corner-Based Design (BC / WC):all timing values are scaled
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Advantages of SSTA
Proper consideration of statistical variations instead of performance loss due to excessive „guardbanding“
Tradeoff between performance and yield
3σ SSTA-prediction
STA-WC prediction
Normalized critical path-delay1.00.80.6 1.2 1.4
Performance Gain
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Basic Flow of SSTA
Leff
Leff
vth
Random Vector),...,,( 21 npppP =
r
Par
amet
er S
pace
Per
form
ance
Spa
ce
Statistical Physical Parameters
delay
pdf Random Vector),...,(
1
∑∑∈∈
=npathi
ipathi
i XXYr
Statistical Circuit Performance
Statistical Propagation
delay
delay
Random Variablei Cell ofDelay X i :
Statistical Cell Library
Statistical Modeling
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Key Problem in Performance SpaceProcess parameters can be assumed to be normal
BUT: Delay as a nonlinear function of normal distributed process parameters is NOT normal
Normal distribution of gate delay only valid for small parameter variations
Leff [nm]Vth [V]
jpdf
Gate delay
normalnon-normal
Gate delay
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The normal distribution assumption
Most SSTA algorithms rely on normal distributed gate delay
+ distribution is captured by mean µ and sigma σ
+ operations on random variables become easy
- inaccurate for large process parameter variations
MCNormal distribution assumption
Delay [ps]
Distributions of Inverter Delay
[Zhang et al., DAC 2005]
Higher order models start to appear
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Path- and block-based approaches
g1 g3 g5
g2g4
g1 g3 g5
g2g4
Path-based Block-based
Enumerate all combinational paths i = 1 … nFor each path i : determine PDF of path delay di
Distribution of circuit delay d: d = max(d1, d2, …, dn)
Start at PIs, proceed in levelizedfashion to POs / FF inputs ol
For each gate gi: if PDFs of all inputs are known, determine PDF of output arrival time tout
Distribution of circuit delay d: d = max(tout (o1), tout(o2), …, tout(on))
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Propagation of Random Variables
■ Two basic operations for propagating random variables:
sum operation simple in case of joint-normal density fX,Y :
maximum operation introduces complexity in SSTA – solutions only presented for joint-normal density fX,Y
∫ ∫∞− ∞−
⎟⎠⎞
⎜⎝⎛=
=z z
YXZ dydxyxfzF
YXZ
),()(
),max(
,
Sum:
XY
ZX
YZ
Maximum:
)(),(2)()()()()(
222 YYXCovXYXYXYX
σσσµµµ
++=+
+=+
∫ ∫∞
∞−
−
∞−⎟⎟
⎠
⎞
⎜⎜
⎝
⎛=
+=
dydxyxfzF
YXZyz
YXZ ),()( ,
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Sources of correlation
Both contain d1
■ Reconvergent paths (path sharing)
d1
■ Spatial correlations short distance→similar variation
■ Correlated variables are not independent !
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independent path delays fi:
E.g. 100 paths with a probability each of 0.99:
p = 0.99100 = 0.36 !!!
Correlation affects Circuit YieldPDF fi for each path delay
path1: g1, g3, g5 with f1
path2: g1, g4, g5 with f2
path3: g2, g4, g5 with f3
Probability pi, that delay of pathi meets timing targetCircuit Yield p, assuming:
g1 g3 g5
g2g4
∏=i
ippperfectly correlated fi:p = min (pi)E.g. 100 paths with a probability each of 0.99:
p = 0.99
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Block-based vs. Path-based …
??Applicability+-Run-Time-+Accuracy
Path-based Block-based
Path-based: SSTA as postprocessor after STA
STA SSTADesign, libraries,…
e.g.: n critical paths
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Verification of SSTA resultsStandard: Comparison to Monte Carlo– Results always look very good– But: inputs into MC matter!
Linear delay modelNo load / slope dependency
MonteCarlo
SSTAalgorithm
neglects correlationsassumes normal distrib.etc.
Both results containdelay model assumptions!
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Statistical Design – Where are we?Is SSTA productionworthy yet?– IBM reports productive use of EinsTimer– Major EDA vendors announce SSTA features– Startups focus on SSTA
BUT …
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Statistical Design – Where are we?Input data:– Trustworthy? Correlations?– IDM vs Foundry
Basic approaches:– Path-based: preselection of paths risky– Block-based: accuracy unclear
Delay modeling and propagation:– Load / slope consideration– Interconnect modeling
Production testing:– At-speed testing required– How many paths to test?
22
Statistical Design – Where are we?Even with analysis, we’re only at the beginning.Deterministic STA:– Research since 1982– Widespread industrial adoption since mid-90s
Statistical analysis / optimization of analog circuits– Research since 1970s – Industrial adoption starting 1990s– Commercial availability since 2000s
From statistical analysis to statistical optimization.
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AcknowledgementsWalter Schneider and the TUM SSTA teamH. Kinzelbach, A. Lang, H. Endres, A. Huber (Infineon Technologies AG)