United States Patent [19] Coffron

[1 1] 4,370,728 [45] Jan. 25, 1983

[54] STATIC STIMULUS TESTER FOR MICROPROCESSOR SYSTEMS

[75] Inventor: James W. Coffron, Palo Alto, Calif.

[73] Assignee: Creative Microprocessor Systems, Los Gatos, Calif.

[21] App]. No.: 111,830 [22] Filed: Jan. 14, 1980

[51] Int. Cl.3 ..................... .. G06F 11/00; G06F 11/20 [52] US. Cl. .................................................. .. 364/900

[58] Field of Search 364/200 MS File, 900 MS File

[56] References Cited PUBLICATIONS

uScope 820 Microprocessor System Console, Intel Cat alogue Sheet #9800495B.

,uScope 820 Microprocessor System Console, Opera tor's Handbook @1977, i978.

Primary Examiner-Gareth D. Shaw Assistant Examiner-John G. Mills Attorney, Agent, or Firm—Ronald E. Grubman

[57] ‘ ABSTRACT

The present invention provides a device which takes the place of the microprocessor in a microprocessor based system, and which provides the user with manual control and monitoring of the logic level of each sepa rate input or output pin corresponding to the same pin of the single chip microprocessor of the system under test.

5 Claims, 7 Drawing Figures

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4,370,728 1

STATIC STIMULUS TESTER FOR MICROPROCESSOR SYSTEMS

BACKGROUND OF THE INVENTION

This invention is concerned generally with testing of microprocessor systems, and more particularly, with a device for controlling and monitoring the microproces sor in the system. With the rapidly escalating use of microprocessors in

electronic systems of all kinds, the testing and debug ging of such systems has become a major concern. In the prior art, it is known to use “signature analysis“ at various points in the system. This can be accomplished with a device such as the Model 5004A by Hewlett-Pac kard Company, which compares a known “good” bit stream against the empirical bit stream measured at selected test points in the system. Although some infor mation is obtained through the signature analysis, de tailed information about the system operation is not revealed. The use of logic state analyzers such as the Model

1661A by Hewlett-Packard Company provides more information about the system under test. These analy zers provide passive monitoring of the hardware and measurement of logic levels on the system data bus, address bus and control bus lines. Although information about the system is received, control of the system is not obtained through such devices. The de?ciency of logic state analyzers related to

control has been remedied by the use of in-circuit emu lators such as the ICE-8O (8080 in-circuit emulator) from Intel Corporation, which are microprocessor based test systems which perform exactly like the mi croprocessor component system under test. Generally, the emulation of the microprocessor is accomplished on a small computer system, so that the user has some control over data entry and output into the system under test. However, detailed control of each micro processor pin is still not possible.

In yet another level of sophistication of the in-circuit emulator, a "stand in" for the microprocessor has been developed which enables the user to single step through the normal sequencing of the microprocessor in the system under test. Even with the use of these stand in testers, it is still a problem with the testing of micro processor systems in that control of the microprocessor is limited to the single “machine cycle." That is, the microprocessor can only be “frozen" or stopped in certain very speci?ed electrical cases.

SUMMARY OF THE INVENTION

In accordance with the illustrated preferred embodi ments, the present invention provides a device which takes the place of the microprocessor in a microproces sor-based system, and ‘which provides the user with manual control and monitoring of the logic level of each separate input or output pin corresponding to the same pin of the single chip microprocessor of the system under test. Thus, a device according to the invention allows the user to manually control any signal within the system that the system microprocessor would nor mally control, statically adjusting the logic levels of each signal line without regard to order or past history of the system. The user can therefore verify the opera tional status of any part of the system, whether or not the system, as a whole, is operational. Feedback loops of the system can be broken, and intermediate points of

5

25

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50

60

2 the loop directly accessed. Individual pins can be elec trically stimulated and monitored to locate a “stuck" bit. Additionally, the user can exercise selected commu nications paths in the system, while monitoring the signal integrity at all points.

DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram of a statis stimulus tester (SST).

FIG. 2 is a view of the front panel, ofthe static stimu— lus tester, including keyboard and display. FIG. 3 is a schematic diagram of the controlling

microprocessor used in the SST. FIG. 4 is a schematic diagram ofa ROM and a RAM

used in the SST. FIG. 5 is a schematic diagram of the keyboard and a

part of the display of the SST. ' FIG. 6 is a schematic diagram of additional sections

of the display for the SST. FIG. 7 is a schematic diagram of the I/O interface

bus of the SST which connects the SST to the system under test.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A device according to the invention will sometimes be referred to hereinafter as a Static Stimulus Tester, or “SST." In FIG. 1, there is shown a microprocessor (MP) 11 used in the SST, which may be, e.g., the model number 8080 available from the Intel Corporation, Sun nyvale, Calif. Processor 11 is accessed by the user through a keyboard 13, to be described in more detail hereinafter. Information from the processor is displayed on a display 15, which may be of the “hexadecimal" tYPE- .

Interconnection with the system under test is made via a series of pins, or "Control I/O Ports” 17, which correspond in number and physical arrangement with the pins of the microprocessor in the system under test. In operation, that processor is removed from the system under test, and Control I/O Ports 17 connected in its stead, preferably through a connecting cable 18. The operating system for the SST is stored in a sys-~

tem ROM (read-only memory) 19 which may be e.g., an Intel 2708 EPROM. The information stored in ROM 19 directs the action of internal microprocessor 11 in com municating with keyboard 13, display 15, and Control {/0 Port 17. A system RAM 21, such as an Intel 2ll4, provides temporary storage of data for use by internal microprocessor 11. RAM 21 is also used to store tempo rary programs that are entered as keystrokes on key board 13 in a manner similar to that employed in pro grammable calculators.

Referring now specifically to FIG. 2, there is shown, in more detail, a keyboard 13 which is speci?cally adapted for testing systems involving the Intel 8085 microprocessor. The keyboard will have a different set of keys if the SST is to replace a different microproces sor in the system under test, the arrangement of which will be evident to those skilled in the art after reading the totality of the present specification.

In FIG‘. 3, microprocessor 11 is shown in more detail including a microprocessor chip 23, an 8228 system controller 25, and a pair of 74LS367 address bus buffers 27 and 29. A number of logic gates are also included to provide the correct chip select and write enable signals to the SST system.

4,370,728 3

ROM 19 and RAM 2] are shown in more detail in FIG. 4 including the particular interconnections 31 between processor 11 and the various 2708 ROM chips.

In FIG. 5 are shown keyboard 13 and display 15 which includes four alphanumeric display elements 33, 35, 37 and 39 ofthe HP 5082-7340 type, available from Hewlett-Packard Company, Palo Alto, Calif. FIG. 6 shows additional indicators used as part of

display 15 such as a number of LED’s 34, 36, and 38, used to prompt the user as the SST executes functions in normal system operation.

FIG. 7 shows Control I/O Port 17, including inter connections 41 to/from processor 11, and interconnects cable 43 to/from the system under test. The invention will be best understood by means of an

operational example. In particular, it will be assumed that the system to be tested involves the Intel 8085 microprocessor, which is to be replaced by the SST for system test purposes. As noted above, the keyboard of FIG. 2 is appropriate for such a system, and the differ ent labels of that keyboard will be referred to in this example. In this particular example, the SST will be used to read data from the ROM or RAM of the system under test. To understand how the SST performs this function, it is helpful to know how the 8085 micro processor, itself, executes this function. This informa tion is known by those skilled in the art, but will be summarized here for completeness. To read data from memory, the 8085 microprocessor executes the follow ing general sequence of events. All terms refer to [/0 pins of the 8085 itself:

(I) System address is set to the location of memory to be read. ‘

(la) AIS-A8 the upper address byte is set. (lb) A7—A0 are set on the data lines of the 8085 mi

croprocessor. (2) The ALE bit is set to a logical l. (3) The ALE bit is set to a logical 0. (With the ALE

returning to a logical 0, the lower byte of address is latched into the address latch in an 8085 system.)

(4) [/0 memory line (IO/M) is set to a logical O indi cating a memory operation.

(5) RD signal is set to a logical 0. At this point, data from the address location of mem

ory is on the system data bus. The 8085 microprocessor strobes this data into an internal register. To perform this same general function with the SST,

the following sequence of events are performed: (1) The user removes the’ 8085 microprocessor from

the system under test and installs SST cable 18 of FIG. 1 into the vacated socket.

(2) The user presses the key labeled ADR on SST keyboard 13. The SST will respond by blanking display 15, and turning on a light-emitting diode (LED) to indicate that four address nibbles are required before proceeding. These four nibbles will uniquely define a 16-bit address.

(3) The user now enters four digits via the keyboard. For example, the user may enter the hexadecimal num bers A B C D.

(4) The user now presses the key labeled ENTER, whereupon the following occurs: the 16 bits de?ned by the word ABCD are set to the proper control output ports; the 8-bit word AB is strobed into a latch 45 while the 8-bit word CD will be set into another latch 47. The SST now turns on an indicator LED 49 (labeled “COM" in FIG. 2) and waits for another user input. This completes the ?rst step in the electrical‘ sequence

5

45

65

4 to read data from memory; namely, set the system ad dress bus. When the ENTER key is pressed, the SST will automatically take the ALE line to a logical l and the ALE line to a logical 0. This will latch the CD address that was on the data bus into the address latch of the system under test (the address latch must be pres ent in any 8085 microprocessor system). Thus, at this point, the address is effectively presented to the system memory. It can be noted that the address is set statically on the address bus of the system under test, so that the user can electrically verify the logic conditions of the address bus line using Direct Current or Static measure ment techniques.

(5) The next operation the user will perform is to press the key labeled lO/M. When the user presses this key, the SST will light another indicator LED 51, 52 (labeled “WAIT" and “D1“ in FIG. 2), an indication to the user that one digit must be entered. The SST is waiting for a O or 1 to be entered via the keyboard. The user will press the key labeled 0 and next. press the ENTER key. When these two operations are complete, the IO/M line output from the 8085 microprocessor is now set to a logical 0 indicating a memory operation to be performed. Next, the user will press the key labeled RD. The SST will wait for a l or 0 to be entered. The RD control bit C2 of latch 53 (FIG. 7) is set to a logical 0. This action will set the RD signal of the system under test to a logical 0.

After this step is complete, the data from the system under test of the designated memory location should be present on the data bus of that system. To read the data bus with the SST, the user presses the key labeled RBUS. When this key is pressed, the following will occur: 1

(1) 1c 47 of FIG. 7 is disabled. (2) IC 55 of FIG. 7 is clocked by SST processor 11 of

FIG. 1. (3) Processor 11 on the SST reads the data clocked

into IC 55 (this being the data that was present on the data bus of the system under test.)

(4) Processor 11 will write the data read from IC 55 to the SST display 15. In this way, the user can visually verify the logical condition of each bit on the data bus of the system under test. The above-described “MEMORY READ" function

is performed in response to user activation of a particu lar set of keys on the keyboard. Other functions are activated by different keys to be described immediately below. Upon activation of a key, processor 11 interro gates a "Command Jump Table” in ROM 19 to locate the ROM address of the routine corresponding to the key-defined function. Processor 11 then executes this function routine and any other routine which is called in the process of executing the function routine. For a system under test in which the microprocessor

is an 8085 by Intel Corp, the program listing of the "Command Jump Table” and the routines required to execute the keyboard commands is included herein as Appendix “A". The SST operation resulting from this preferred keyboard and set of programs is summarized below where reference is made to the key labels (which are identical to the labels in the “Command Jump Ta ble,” unless otherwise noted. ADR The ADR key, or address key, will put the SST into

a mode where it is waiting for the user to enter 4 hexa decimal digits to be used as a 16 bit address for the microprocessor system under test.

4,370,728 5

DATA The DATA key puts the SST into a mode where the

microprocessor is waiting for the user to enter two hexadecimal digits to be used as 8 bits of data to be placed on the data bus of the system under test. REO The REO is short for Reset Output. When this key is

pressed the SST will wait for the user to enter a logical l or a logical O on the keyboard, to be placed on the reset output line. SOD This is the abbreviation for Serial Data Output. When

this key is pushed the SST will wait for the user to enter a logical 1 or a logical 0 very similar to the reset out function, REP This is the abbreviation for REPEAT. When the

REPEAT key is pushed, the SST will repeatedly re execute the last key entered, prior to the REPEAT key. DEF This is the abbreviation for DEFINED FUNC

TION. This key is pushed to de?ne a function, e.g., when the user desires to write his own program for the SST. The program itself is entered via keystrokes, much as the programs are entered into a programmable calcu lator. CE The abbreviation is short for CLEAR ENTRY,‘

which clears the keyboard and awaits new data to be entered. HLDA This is the abbreviation for HOLD ACKNOWL

EDGE. When this key is pushed the SST goes into a‘ mode awaiting entry of a l or a 0, to be placed on the hold acknowledge line.

This is the abbreviation for WRITE. When this key is hit the SST will wait for the user to enter a l or a 0, to be placed on the write enable output line. INTA This is an abbreviation for INTERRUPT AC

KNOWLEDGE. When this key is hit the SST will await entry of a l or a 0, to be placed on the interrupt acknowledge line. IO/M (referred to as IO&M in the listing) This is an abbreviation for the 1/0, or Memory line.

When this key is hit the SST goes into a mode waiting for the user to enter a l or a 0, to be placed on the 1/0 or memory output line. LDA This is the abbreviation for LOAD A REGISTER

WITH MEMORY DATA. When this key is pressed the SST will go into a mode awaiting entry of 4 hexa decimal digits to be entered as the address. After the 4 digits have been entered the SST will automatically control all the bits necessary to read data back from memory at the address speci?ed. STA This is the abbreviation for STORE A REGISTER

INTO MEMORY. When this key is pressed the SST will await entry of 4 hexadecimal digits specifying a unique memory address. After the address is entered the SST will then wait for two more hexadecimal digits to be speci?ed, as data to be written to the unique memory address. After this data has been entered, the SST will automatically perform all the necessary control to write those 8 bits of data into the memory of the system under test.

6 RESET This is the abbreviation for RESET. When this key is

pressed the SST will execute the internal program which is the same program executed when power is ?rst turned on to the system. RAM This is the abbreviation for RANDOM ACCESS

MEMORY TEST. When this key is pressed the SST awaits entry of 4 hexadecimal digits to be entered to specify a starting address for the test to be run. After the starting address is entered, the SST will then wait for 4

‘ more hexadecimal digits to specify an ending address. When the ending address has been entered the SST will automatically perform a functional test on the system RAM between the address limits that were speci?ed. ROM This is the abbreviation for READ ONLY MEM

ORY TEST. When this key is pressed the SST will go into a mode waiting for 4 hexadecimal digits to be en tered. These hexadecimal digits are a starting address for the ROM test to be run. After the 4 digits have been entered the SST will automatically compare a test ROM plugged into the SST front panel against the

‘ ROM of the system under test speci?ed at the starting 25

35

45

65

address the user entered. CLK This is the abbreviation for CLOCK. When this key

is pressed the SST will wait for a l or a 0 to be entered, to be outputed on the clock line. RD This is the abbreviation for the READ LINE. When

this key is pressed the SST will wait for a l or a 0 to be entered. The l or 0 will be outputed on the read line. F 1, F2, F3 These three are user de?nable functions. When this

key is pressed the SST will go into a mode waiting for the user to enter in a series of keystrokes to be executed as a program. After the keystrokes have been entered, .the keystrokes corresponding to any of the keys labeled F1, F2 or F3 will be executed each time the user presses that key. ALE This is the abbreviation for ADDRESS LATCH

ENABLE. When this key is pressed the SST will go into a mode waiting for a logical l or a logical O to be entered, to be outputed on the address latch enable line.

501 This is the abbreviation for the STATUS 0 and 1

LINES on the 8085 microprocessor. -When this key is pressed the SST will go into a mode waiting for any number 0, l, 2, or 3 to be entered, which will be out puted on the two lines 0 and I. IN This is the abbreviation for INPUT DATA to the

accumulator. When this key is pressed the SST will await entry of two hexadecimal digits which specify an address of an input port. After the address has been speci?ed by the user, the SST will automatically per form all the control necessary to execute an input in struction. The data from the input port speci?ed will be displayed on the SST. OUT This is the abbreviation for OUTPUT ACCUMU

LATOR TO OUTPUT PORT. When this key is pressed the SST will await entry of two hexadecimal digits. These hexadecimal digits will specify the address of the output port. After the address has been entered the SST will then wait for the user to enter two more

digits which will specify 8 bits of data to be written to the speci?ed output port. After the data has been en tered the SST will execute all the control necessary to write the data to the output port speci?ed. RBUS This is the abbreviation for READ DATA BUS.

When this key is pressed the SST will automatically strobe the data on the system data bus, and display the

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data on the 4 digit display located on the front panel of the SST.

ENTER (referred to as ENTR in the listing)

5 This is an abbreviation for ENTER DATA. When this key is pressed the data that is displayed on the SST 4 digit display will be entered into the SST and used as data for the command being executed.

APPENDIX "A"

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ADDRESS LOh SYTE (NOT USED) ADDRESS HIGH BYTE DATA INPUT DATA OUTPUT I ADDRESS LOH DISPALY HSB _

DISPLAY LSB DISPLAY CONTROL CONTROL BYTE ONE CONTROL BYTE Th0 KEYBOARD STATUS LIGHTS

“DRH EOU BFFFDh ADATI EOu BFFFBn ADATO E00 ""70! AHSB Euu OFFEFH ALSB EOU BFFDFH ADISP Euu OFFBFH ACNTt enu 0FF7F|1 ACNTZ Enu DFEFFH AKYBD EDU OFDFFH ASTAT EOU OFBFFH O

n NUMBER OF MEMORY PORTS

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SO 0008 I SI 0000 KTIHE EOU IOO NUMBER OF OEBOUNCE LOOPS O2 BBB! NINIT EOU 14 NUMBER OF INITAILIZE OYTES S3 BOOB a 64 OBOE : KEY CODES SO GOOD 1 66 000B CREP EOU 5 87 OOOO CDEF EDU 6 OS OUOO OLDA EDD 12 SO GOOD CFI EOU I9 9O 0050 CF2 EDU 2O 91 DOOO CF3 EDD 21 92 0500 a D3 0000 I DA Dian .RI‘RI'OOIIOOOO'OOID'I.ililtl?illiiil'iillII‘IIIO'IIO‘OIIOIII 95 QDEB I a DO GOOD 1 VARIABLES ‘ v

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Ill 5000 t 101 I191 ORG VARAB IO2 1191 DO PKEY DB 0 PREVIOUS KEY VALUE _ 193 1192 DO LKEY O6 0 SAVED KEY VALUE 1B4 “93 IO REG} OO 0 SP REGISTER 105 1194 O0 OB LPNTR OR I LOOP COMMAND POINTER 105 M95 O0 00 L! DR 0 CFUN POINTER I57 1198 a I08 119! I INITAILIZE REOUI RED VARAIBLES ID’ 1195 ' III H9O IO 7 ‘HASK DO I SAVED SCAN MASK HI 1199 DO KHODE DO I KEYBOARD HOOE FLAB H2 AIDA FF RHODE DD OFFH Y REPEAT FLAG 113 I19! a I14 1195 ' I OUTPUT DATA BUFFER 115 H98 0 I15 I I9! IO OADRL O! O ADDRESS LOA’ I17 119C l0 OADRH OB O ADDRESS YIIOH HS 1190 II IDATA OS 0 DATA I8 I19 119E OB OOATA OO 6 DATA OUT 120 “OF l0 OHSB OO O "58 OF HEX DISPLAY I21 IIAO DO OLSO DO I LS5 OF HE! DISPLAY 122 an: no 0015? O8 0 DISPLAY CONTROL I23 HA2 8U OCNTI DO I CONTROL BYTE OAE 12A HA3 OB OCNT2 DB 0 CONTROL BYTE TAO 125 j 1A4 um OKYSD D5 0 KE-YEOARO :26 11A: 00 OSTAT 0a 5 arms LIGHTS 1-27 HAS A I?! IMO A FUNCTION KEY DEF INITION AREA 129 IIAO A . ISO HA6 KFI OS 20! I31 126E KFZ OS 20B 152 1356 KFS OS 260 ISO ISFE I I34 IOFE t 135 ISFE tlililttlltit'ttlt!tlllltlitliiiniitllliittiiiii'itliltit... I36 ISFE - t a I37 ISFE n POKER FAIL; RESET ROUTINE A ISO ISFE t n :39 {SEE n“nan:aunt-Annual’.tonnntnnvnaunninnnnnnnnnnnacnn I40 ISFE a I‘I IBFE I I‘? 0900 ORG IOOOH 14S D000 31 9O 11 RESET LXI SP¢STACK GET STACK POINTER 1A4 D003 21 56 IO ' LII l'hOINIT GET INIT ADDRESS 14.‘: B006 11 98 11 LII D'SHASK BET BUFFER ADDRESS 146 0009 BE 0E HVI CENINIT LENGTH 1.7 0005 CO A3 03 CALL "VAR MOVE IT I45 OBOE 3E O5 HVI AyCOEF RESET FUNCTION KEYS

149 150 151 152 15S :54 155 156 157 150 159 16C 161 162 163 164 165 166 167 160 169 170 171 172 173 174 175 176 177 170 179 1" 101 162 163 16A 165 106 187 186 109 19B 191 192 193 194 195 196 197 198 199 200 201 282 203 204 285 206 2B7 200 209 210 211 212 213 214 215 216 217

0010 0013 0516 0019 001C DDIF D020 0023 0023 0023 0023 0023 B023 0023 0025 0020 0025 0025 0025 0025 0025 002E 0031 0030 0035 0035 0030 0035 0035 0035 0035 0035 0035 0030 0030 D038 EH38 B830 @039 003C DBJF 6041 0044 0345 0045 0047 0347 00A? 0047 004A ISAC IDAF 0052 0053 0056 0356 0056 0035 0056 0056 D005 0656 0356 0055 0356 0055 use we nos? aa e050 FF

32 32 32 CD CD F0 C3

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4,370,728 13 14

218 0059 Di! _ DD 2 ADDRESS LDH 219 005A D6 D5 D ADDRESS HIGH 223 0056 DD . DB D DATA IN (HEANINGLESS HRITE) 221. 005C D0 ~06 2 DATA OUT 222 005D S6 D6 DSBH HSD DF HE! DISPLAY 22S 265E S6 D6 GOSH LSD OF ME! DISPLAY 224 DDSF 6D 06 D DISPLAY CONTROL 225 6060 CS SINT DB DCSH CDNTRDL SYTE ONE 226 0661 U0 SINT2 D6 2 CDNTRDL BYTE THD 227 9662 DD DB 0 KEYBOARD 226 6063 D1. D6 X STATUS LIGHTS 229 026A A 238 I264 va CFUN ARRAYS 231 206A 6 232 6064 EA SIN DB DEAN‘. READ STATUS 233 2666 E2 DD DE2H ALE STRDBE 234 I066 62 DD 062" READ I10 235 DIS? a 236 0667 ED SDUT DB SE98 RRITE STATUS 237 8066 E1" ‘ " ' ‘ DB DElrl ALE STRDDE

23! 8269 A1 SDUT2 DB DAIH WRITE I10 239 ISSA CS 06 SCSH RESET ‘ 24D D666 a '>

241 Nos ca ~ - “sun as new new sums 322g on aczn ALE arena:

H a“ ‘as: - D6 CA2 READ MEMORY

245 DUDE CR SSTA' DD ICDH uRITE STATUS 216 206?‘ C1 D3 ICU-l ' ALE STRDBE 2‘7 U275 61 SSTA2 DB OHH ‘RITE Firm" 24B 0271 CS DB DCSH RESET 249 2972 I 25B 0272 a 26! B872 cnmnnnnncnmn-nuan'nnnnnnun\n“umnnunannnnnnnnmnn'nn 2312 D072 6 a 253 0072 n COMMAND ENTRY STATE 0 254 0272 I - i 255 I072 ntctnnnnnnan-qnnnnnnnnnnnn‘an.nnnnoannonon.1.0.22.1‘... 256 D072 6 257 SD72 n 256 SD72 I 269 D072 6 SET CDHHAND STATUS I" LITES 260 "72 n 261 D272 SE SI CHD HVI A'SCHD SET CDHHAND STATUS 262 SD74 S2 AS {1 STA DSTAT SAVE IN BUFFER.‘ ., 26S SD77 CD 60 OS » CALL DDUT 25‘ DD7A CD El 02 CALL RREY BAIT FDR REY DDUN :65 n70 an OCR A RARE 0 T0 n-l 266 227E l7 RLC TIHES 2 v 267 SD7F 21 SE DD LII HHIHTAD SET JUMP TABLE DASE 268 0562 CD 20 02 CALL ADAHL ADD TD HL 269 D085 6E HDV E'H SET ADDRESS 27.5 0086 23 IN! H NEXT BYTE 27! 0087 66 NOV 0,04 272 0066 21 72 D0 L“ H’ CHD SET RETURN ADDRESS 275 S665 E6 XCHG PLACE IN HL 274 DDDC D6 - PUSH D PUT RETURN IN STACK 275 0060 E9 PCHL JHP INDIRECT 276 DOSE a 277 DOSE o CDHHAND JUMP TABLE 276 665E I 279 0065 C4 D0 JHTAB DH ADR l-ADDRESS 250 0590 D5 D6 DH DATA I-DATA 291 DDR2 DC 20 DH RED 2-RESET DDT 262 DDR4 E1 DD DH SOD S-SERIAL DATA DUT 266 I296 EE D! . DH REP AvREPEAT 284 0998 S0 01 DH DEF S-DEFINE FUNCTION 26S DDQA DF D1 DH , CE S-CLEAR ENTRY, RST 7 286 IDDC 19 U1 DH HLDA 7-HDLD ACKNDHLEDGE 2S7 DUDE 16 D1 DH HR S'hRITE

280 289 290 291 292 293 294 29:: 296 297 29! 299 SOB 301 302 803 304 305 us 3M 30: 3&9 aw 311 312 31S 314 315 M5 517 31B 319 m 1321 ‘322 323 324 325 325 327 328 329 330 331 332 333 334 335 335 337 33D 33B 3A0 3A1. 3A2 343 304 3A5 346 347 5A8 349 359 35A 352 353 354 355 356

BOAO 0M2 B0“ HMS “A! OBAA “At "A! "B0 0'52 "84 "B6 nan can NBC “bi 00:9 0052 RFC‘ 0M2‘ wt: Rik-C4 mot‘ wt‘ nu 00C‘ 00C‘ DEC‘ 0557 “CA DBCC BEEF JDDI D004 D905 0005

CD CD 3E CD 3E

CO

ODDS, ,

DBD5 ODDS ODDS DDDC OIaDC OODC ODDC ODDE OBEI DOE! DOES HOE!» DOES DUES BOEG IDES DOES DOE? OOEC DOEF ODFZ OOFS OOPS OOFO DUFF ODFO DUFF BDFC DUFF DIOR I105 BIOS

CD CO CO

CO CD 21 CD CD CO CO

CO CD 21. CD CD 2!

51 O1 O1 01 B1 B1 O1 O1 O! O! M 51 O1 01 DO OO B! B2

SE 50

D2 14

S7 65

69

03

O2

O2

DE 02 OO 03 O1 O0

BO 02 OD B3

4,370,728 15

Du Du DH 0w DH Du Du DH '0': OH OH OH Du Du DH Du nu Du

INTA 10in LDA STA RSET RAH ROH CLK RD F1 F2 F3 ALE 801 IN OUT RBUS ENTR

a

n COMMAND CODE 1

O-INTERRUPT ACKNOWLEDGE IB-IO OR MEMORY" H'LOAD A REGISTER IZ-STORE A REGISTER I3'RESET IA-RAF TEST TEA-RON TEST ISICLOCK l7-READ \S-FUNCTION 1 IO-FUNCTION 2 RO-FUNCTION 3 ZI'ADDRESS LATCH ENABLE RZ'STATUS LINES 23-INPUT ZA-DUTPUT RS-REAO BUS RS-ENTER DATA

U

. ADDREss REouEs'r I

‘on cm. cu cm. oou'r "VI A¢HALE can an HVI A,HALE can. cu: RET

SALE

1

I DATA REOUEST

DATA CALL CD2 CALL DDUT RET

I RESET OUTPUT I

RED HVI AMREO JHP 00611’

n

I SERIAL. DATA OUT

SOD HVI A; HSOD JHP DDBIT

n

a INPUT 1:

1N CALL CRST CALL 5A2 LXI H; SIN CALL CFUNS CALL RBUS CALL CRST RET

A

I OUTPUT n

OUT CALL CRST CALL 6A2 LXI Ho SDUT CALL CFUNZ CALL CO2 L11 H|SOUT2

GET 4 NIEBLE ADDRESS UPDATE '

STROBE ALE ONLY

SET 2 NIBBLE DATA UPDATE

saw us;

GET MASK

CONTROL RESET SET <PORT ADDRESS CONTROL FUNCTIONS

READ THE BUS CONTROL RESET DONE

CONTROL RESET GET PORT ADDRESS CONTROL FUNCTIONS

BET DATA CONTROL FUNCTIONS

357 358 35D 36B 361 362 S53 S64 365 366 .567 S68 S69 37?‘ 371 372 373 S74 575

377 378 379 3B0 381 382 363 384 36: 386 387 31:8 359 59v 391 392 393 394 395 3% 397 39!: 399 4M 401 402 no; 4B4 405 406 407 408 609 410 411 412 413 41‘ 415 416 417 41B 419 42m 421 422 425 424 425

I108 0105 “IF MDF l1” 01oF 911D 011B 011! H 1B 1' 1 12 1:1 15 b1 15 $115 111 121 7-1 17 1111‘ 011A 01 1A B1“ 011C 0111’ 011F 011k’ 01 1F B121 2124 $124 10124 B124 5127 1612‘ 21211 0156 0133 0135 [6157 0137 0167 $157 E1311 913D 01416 0143 M46 @149 014C 10140 B140 214D 8140 8145 B145 0145 @105 a 1 4F UHF UHF BHF 015a E150 E1521 D158 0153 21:14 D157 D155 U155 2151'.

CO C9

SE C5

3E C11

3E CS

CD CD 21 CO CO C0 C9

CD CD 21 CD CD 21 CD C9

CA AF 32 C9

65

52 14

26 1A

61 $4

Db 14

99

5C

59

O2

O2

O2

02

D0 D2 M5 D3 01 BB

D0 D2 DO

162 ED O3

11

O1

11

4,370,728 17

CALL CFUN2 an

i

Q CLElR ENTRY t

CE RET n

I

i

H HVI AH‘HLD! JHP DOBIT

I

1: IRITE

MVI ‘nHkR JMP 00511’

n

HOLD ACKNOHLEOGE

l8

DONE

SET FASK

GET MASK

t INTERRUPT ACKNOhLi-OGE I

INT! MVI A,H1I~TA JHP DOBIT

I

n 1/0 OR MEHDFY I

103M hVI AMIOH! JHP OOBIT

I

I LOAD A REGISTER I

LOA CALL CRST CALL CA4

LDAZ LXI H'SLDA CALL CF u~3 CALL RBUS CALL CRST RET

n

I STORE l REGISTER a

STA CALL CRST ClLL 5A4 LXI H|5STl CALL CFUN2 CALL CD2 LXI Hp S5112 CALL CFUNZ RET

' L

: RESET 1

RSET a

t RAN TEST

RET

’

RAM w

n ROM TEST

RET

ROM RET I

1 1: DEFINE ruuc'rlow , .

DEF LDA KHODE ORA A JZ oar: XRA A su move RET '

GET MASK

GET Hi5!

CONTROL RESET GET MEMORY ADDRESS CONTROL FUNCTICNS

READ BUS CONTROL RESET DONE

CONTROL RESET GET HER-DRY ADDRESS CONTROL FUNCTIONS

GET DATA CONTROL FUNCTIONS

DONE _

EXECUT INC '1‘ SET FLAGS NO; DEFINE KEY YES , RE SET MODE

426 427 42s ,

429 4M: 431 432 433 434 435 436 437 436 439 445 441 442 443 444 445 446 447 448 449 45m 451 452 453 454 455 456 457 456 459 450 46: 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 47B 47B 459 481 442 458 4B4 4B5 4B6 4B7 486 459 49B 491 492 493 494 495

015C 015C MISC 0150 M56 8163 6165 M69 616C 0155 0171 8173 I176 I178 I178 017E B161 B164 9167 218A 0150 B190 I195 0196 a!" 0194 “9D 0146 0143 U145 514B 9149 B144 MAC 014?’ I180 5160 M55 M50 6152 0185 H65 0155 0155 0155 018B 01!! I155 81 b8 518E NC! NC! 0151 MC! “C4 “C7 011;? “C7 D167 0159 U1 El: HCC Bltt 415C UICF B102 U104 0195 MD? 510A

AF

21 22 CD CD FE CA FE CA FE CA C3 21 CS 21 C3 21 22 32 CD SA 3C 32 CD 2A FE CA 77 23 FE C2 C9

3E CS

21 CS

21 C3

21 C3

CD 32 E6 47 3E CD 3A

[37 14

A5 24

6E 24

36 24

D3 14

11 Z3 02

O1

B1

81 D1 11 I1 12 O1 13 1 1

33 11

11 O2 11

O1

O1

11 O2

12 B2

13 O2

O3 11

19 4,370,728

20 ' ozrme ruwc'nunnzv new: 4

DEF 1

DEF2

DEF3

DEF4

DEF5 DEFE

DEF7

IRA A STA ODISP LXI h?b SHLD OLSB CALL DDUT CALL RKEY CPI CF1 JZ DEFS CPI CF2 JZ OEF4 CPI CFS JZ DEFS JHF OEFZ LII HMKFI JHP DEFS LXI H|KF2 JHP DEFS LII H, KF3 SHLD LPNTR STA OLSB CALL DDUT LOA OMSB INR A STA OHSB CALL RKEY LHLD LPNTR CPI CREP JZ DEF? HOV H, A IN! CPI JNZ RET

H CDEF OEF6

t READ

HVI JHP

A,HRO DDDIT

4 FUNCTION 1

F1 LXI HvKFI JHP FKEY

a

A FUNCTION 2 I

F2 LXI HoKFZ JHP FKEY

a FUNCTION 3

ALE

4 SO

LII HJFS JHP FKEY

A | "I JHP DDBIT“

a. s: nougs, ‘

CALL GD! STA REG1 ANI 1 HOV B, A HVI A, HSB CALL DBIT LDA REG1

USE 4 015115

GET 4' ZERO DISPLAY UPDATE GET FUNCTION xiv F1 7 YES F2 2 YES

His ONLT ACCEPT FUMITIDN KEYS DEFInE F1

DEF IKE F2

DEF IKE F3 SAVE POINTER PUT KEY IN DISPLAY UPDATE GET COUNT SUPP SAVE GET NEXT KEY GET POINTER SINGLE STEP ‘8 YES no. SAVE KEY BUP'P POINTER new: 1 no. conzuus Yes. oun

GET HASK

GET FUNCTION ADDRESS TREAT AS FUNCTION KEY

GET FUNCTION ADDRESS TREAT AS FUNCTION KEY

GET FUNCTION ADDRESS TREAT AS FUNCTION KE'!

4 ADDRESS LATCH ENABLE

GET "ASK

GET an‘ suE SW1? Ln~ B11 SAVE IN B GET "ASK 5E1 BIT GET DATA AGAIN

A96 497 A93 499 EDD 30! 5B2 503 5E4 505 506 5B7 50!! 509 51B 511 512 513 314 515 516 517 5:3 31D 52B 521 522 523 324 525 526 527 528 329 535 331 532 533 534 335 336 537 533 53D all 541 542 343 544 5A5 5A6 5A7 5A6 5A9 55v 551 352 553 354 55b 556 557 558 559 5625 56A 552 563 364

0100 ulDF MED 0152 “E5 ME! 0129 Oil-.9 MED @159 MED NEE DIEE NEE THEE 01F! MFA MP5 DIFS “F5 MP5 MP7 a1FA MFD “FE BIFF B282 D295 D286 B256 B256 0206 B229 225A 0200 020E 0211 0214 021A B214 6211 82.17 oéu 0210 0220 0223 822A 0224 U221 0224 B227 B229 1022C 8220 2-220 222D R220 @220 2220 B220 0220 B220 B220 2225 vzzF 0232 2233 0234 0234

E6 47 3E CD CD CD

3E 32 21 77 7E 32 CD CD

2A 23 22 7O 32 C3

32 CD 3A CD CD CD

22 3E 32 C9

85

D2 24 ii

mg 1

01 35 5D

DA

AD 30

DB

95

93 35

38 "I

94

33

D3 D3

ll

11

11 DA

11 D2

11

Al

4,370,728 21 22

AMI ‘,2 “ sTiIP NElT BIT HOV B y A SAVE TN 5 "V1 ANTS! GET HA5! CALL DEIT SET D11

_ CALL DDUT UPDATE RET DONE

a

a CLDCK a

CLK "VI A. "CLK GET MASK 1*, » ~ JHP. DDBIT

'

. REPEAT A DEPT“; LDA PKEY GET FEEVIDUS KEY

STA RHDDE SAVE AS FLAG RET DONE

t

\- READ‘BUS . T

RBUS HVI- A|DCH GET BLANKINE CODE STA DDISP SAVE LXI MADATI GET ADDRESS HOV H, A STROEE LATCH HOV A." DET DATA STA DLSO PUT IN DISPLAY CALL DDUT UPDATE RET DONE

' ENTER VALUE _ I

ENTR LHLO OADRL BET ADDRESS IN! H - DUN-P SHLD OADRL AND SAVE HOV AoL GET LON DTTE DTA DDATA DAVE ‘ JHP LOA2 TREAT A3 LDA

n n OODIT! GENERAL BIT COMMAND HANDLER t

00311’ STA REG! SAVE MASK CALL CD1 GET DATA LDA REG! GET MASK ‘CALL DDIT SET BIT CALL DDUT UPDATE RET ‘ DONE

. n FRET: GENERAL FUNCTION KEY HANDLER .

FKET SHLD LPNTR UPDATE LDDP POINTER HVI A11 SET KEYBOARD STA KHDDE LDCAL MODE RET GO TO IT

..'......‘."....'.‘..ti.'...‘""...’"".._'.....I?....".‘ t

I UTILITY SUBRDUTINES '

n ADAHL! I

ADAHL ADD L HDV Ll A JNC ADAH INR H

ADAH RET

vADDS A TO "L RESULT IN HL; NO OTHER REES. AFFECTE

S65 566 567 566 569 57B 571 :72 573 S74 S75 S76 :77 57B 579 58m 551 582 as; 58¢ 56: 586 587 S88 589 59a :9: S92 :93 594 595 596 597 596 599 6GB 601 602 6a; 60A 605 566 607 6B8 6B9 61a 51: M2 613 614 1:15 616 617 618 519 62m 621 622 523 624 625 626 627 625 629 638 631 632 633

B234 0234 0254 e234 U254 B234 B234 2254 B235 0235 B235 8235 B255 B255 B235 D235 0235 B235 0235 6237 823A @230 823E 023E 923E 025E 5240 B243 0246 8249 D2“: 024D 024D 024D 0240 02A!’ 0252 0255 0258 0255 ‘025C NSF B262 0265 new 0269 yaw 2209 U‘Zbi‘v 9-208 @26E 0271 @274 07277 027A 027D 627E 0281 0264 B285 B255 0285 0285 0288 D259 $28!; 52" 9291 0294

3E CD CD :9

‘SE CD CD CD 32 C9

3E CD CD CD !A 7D 32 22 32 S2 (:9

3E CD CD CD CD CD 2A 70 32 22 c9

32 AF 32 32 3E 32 ED

44 85 D4

24 SS 95 DA DE

DC 85 9B 9B 96 D1 A0

A5

02 02

82 D2 D2 11

02 D2 D2 11

11

D2 D2

D2 02 1 1

4,370,728 23 24 ‘minimum:annualn“nnnnnarnanunnotnnnanunAnn-nnnatnmnnn't ! t

n ERRDR RDUTINES ' a

a I

I

I

ERR i

n

RET

ilillilill'iil‘lillltt’lii'liiii?'ll'illl'liillililiiliiiiiii.

I

t GET ADDRESS S DATA BYTES I

A GET ONE DATA NIBBLE c

GDl I'Wl ApSDl CALL DIED CALL DUAL RET

t

t GET THO DATA n

5B2 HVI A | SD? CALL DIED CALL D151 CALL DUAL STA DDATA RET

n

1 GET TND .

6A2 HVI A’ 5A2 CALL DIED CALL D151’ CQLL DUAL LHLD DLSB HOV AIL STA ODATA SHLD DADRL STA DDATA STA DADRH RET

a

I GET FOUR ADDRESS l

BAA "VI A , 5AA CALL D168 CALL D151 CALL D151 CALL D151 CALL DUAL LHLD DLSB HOV AvL STA ODATA SHLD DADRL RET

Q

a SET LITE STATUS! A

0168 STA DSTAT XRA A STA DLSB STA DHSB HVI AIDFH STA DDISP CALL DDUT

GET STATUS BYTE GET 1ST DISIT HAIT FOR ENTER DDNE

NIBBLES

GET GET SET

STATUS BYTE 1ST DIGIT 2ND DIGIT

MUST BE DATA BYTE DONE

ADDRESS ‘NISBLES

BET STATUS BYTE GET 1ST DIGIT GET 2ND DIBIT

GET ADDRESS nDVE TO A SAVE SAVE SAVE AS DATA sAVE AS ADRH DD~£

NISELES

STATUS BYTE 1ST DIGIT 250 01611 3RD D1511’ nu DIBIT

GET GET GET GET SET

GET ADDRESS SAVE IR A SAVE SAVE

GET 1ST DIGIT

SAVE STATUS GET ZERO CLEAR DISPLAY CLEAR DISPLAY

BLANK DISPLAY UPDATE