stage iv : february 18 h 2004 component layout
DESCRIPTION
Presentation #5: Rijndael Encryption. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14). Stage IV : February 18 h 2004 COMPONENT LAYOUT. Overall Project Objective: Implement the new AES Rijndael algorithm on chip. - PowerPoint PPT PresentationTRANSCRIPT
Team W1Team W1Design Manager: Rebecca MillerDesign Manager: Rebecca Miller
1. Bobby Colyer (W11)1. Bobby Colyer (W11)2. 2. Jeffrey Kuo (W12)Jeffrey Kuo (W12)3. Myron Kwai (W13)3. Myron Kwai (W13)4. Shirlene Lim (W14)4. Shirlene Lim (W14)
Stage IVStage IV: : February 18February 18hh 2004 2004
COMPONENT LAYOUTCOMPONENT LAYOUT
Presentation #5: Rijndael Presentation #5: Rijndael EncryptionEncryption
Overall Project Objective:Implement the new AES Rijndael algorithm on
chip
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StatusStatus
Design Proposal Architecture Proposal Size Estimates/Floorplan Gate Level Design
Schematic Design (Fixed)Input/Output Logic to SBOX Changed and TestedTop Level Schematic Verified
Component Layout (90% Done) To be Done
Simulations/Optimizations Everything else…
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Design Decisions & Design Decisions & ProblemsProblems
DECISIONS Change Verilog to match newer input control logic to SBOX
Control Logic will be made of PMOS, can’t be done in Verilog Implemented clock divider using counters Added 3rd SBOXRemoved 5 Rounds of Encryption
PROBLEMSNew SBOX logic and reduced pipeline implementation into Verilog
Accidentally left SBOX lookup in FinalTextOut, looked into ROM twice
Logic In into the SBOXTree Structure – Not so nice in layout
Schematic Simulation yields correct output, but timing issues are causing problems in the pipeline
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OLD FLOORPLAN
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ADDED SBOX #3-Previous design inefficient for small text
-Makes Sense to Give Round Key Generation its own SBOX
- But increased transistor count drastically to ~45k
-The logic and muxes are HUGE
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ELIMINATION- Eliminate 5 rounds
- Eliminate 1 SBOX & control logic
- Reduce transistor count to 27k
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New Schematic (5 Rounds) Mux used in both In and
Out logic, moved outside and shared
Mux used in both In and Out logic, moved outside and shared
module logicandsbox (Out, In); output [7:0] Out; input [7:0] In;reg [7:0] Out;
always @(In)case(In) // synopsys
full_case parallel_case 8'h00: Out=8'h63; 8'h01: Out=8'h7c; 8'h02: Out=8'h77; 8'h03: Out=8'h7b; 8'h04: Out=8'hf2; 8'h05: Out=8'h6b; 8'h06: Out=8'h6f; 8'h07: Out=8'hc5; 8'h08: Out=8'h30; 8'h09: Out=8'h01; 8'h0a: Out=8'h67; 8'h0b: Out=8'h2b; 8'h0c: Out=8'hfe; 8'h0d: Out=8'hd7; 8'h0e: Out=8'hab;
FUNCTIONAL MODEL OF ROM
Case Statements
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Floorplan
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ROM and Control
ROM and Control
Key Expand no pipe
In Logic & Out Logic
In Logic & Out Logic
Round Permutations
Key Expand
Text & Key Output
345 um x 325 um
ROM Schematic
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ROM Control with PMOS
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ROM and Control Logic
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ROM
Control Logic
Control Logic
Round Permutation
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Key Expand
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Key Expand Layout
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SBox Mux Tree In-Logic
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8 x Mux5Previous Logic
SBox Mux Tree In-Logic
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Current Logic
SBox Mux Tree In-Logic
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Current Logic
Tree Structure Difficult to Implement in Layout
• Need to finalize wiring from other modules in order to be more efficient in arranging in-logic
SBox Mux Tree Out-Logic
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Schematic Simulation Schematic Simulation ResultsResults
e0 e0 34 34 e7 e7 8b8b
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Schematic Simulation Schematic Simulation ResultsResults
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COMPONENTSCOMPONENTS AREA ESTIMATE (AREA ESTIMATE (umum22))
Key Schedule Registers & XORs 351 um x 70 um = 24,570 um2
ROM SBOX (2) 50 um x 170 um x 2 = 14,000 um2
Control Logic (352 um x 70 um) – 14,000 um2 = 10,640 um2
Transformation Register & XORs 160 um x 352 um = 56,320 um2
Others Buffers & Wiring 10% = 10,553 um2
TOTALTOTAL 116,083 um2 (~350 um x ~350 um)
PREVIOUS AREA PREVIOUS AREA ESTIMATEESTIMATE
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COMPONENTSCOMPONENTS AREA ESTIMATE (AREA ESTIMATE (umum22))
Key Schedule Registers & XORs 80 um x 40 um x 4 um + 35 um x40 um =
14,200 um2
ROM SBOX and Control Logic (2) 60 um x 250 um x 2 = 30,000 um2
Transformation Register & XORs 70 um x 70 x 4 = 19,600 um2
Add Round Key & Final Text Out
70 um x 15 um x 2 = 2100 um2
Others Buffers & Wiring 10% = 6,590 um2
CURRENT AREA CURRENT AREA DIMENSIONSDIMENSIONS
Total: 345 um x 325 um (taken from current floorplan)
Previous PROBLEMATIC Previous PROBLEMATIC Transistor CountTransistor Count
(Assuming(Assuming 32-bit Implementation) 32-bit Implementation)
Clock Divider 165 Add Round Key 256 Valid Out DFFs (10) 266 SBoxMuxTreeIn (3) 7008 SBoxMuxTreeOut(3) 11976 ROM (3) 7644 Key Expansion (10) 3840 Round Permutation (9)
11952 Final Text Out
256
Total: 47523Total with Buffer Estimate (10%)
52275
Changing the ROM Control to PMOS 4721118-525 Integrated Circuit Design Project
Current Transistor Count with 5 Rounds of Current Transistor Count with 5 Rounds of Encryption Encryption
(Assuming(Assuming 32-bit Implementation) 32-bit Implementation)
Clock Divider 165 Add Round Key 256 Valid Out DFFs (5) 136 SBoxMuxTreeIn (Text) 2336 SBoxMuxTreeIn (Key) 1056 SBoxMuxTreeOut (Text) 3992 SBoxMuxTreeOut (Key) 2038 ROM with New Control Logic (3) 7332 Key Expansion (5) 1920 Round Permutation (4) 5312 Final Text Out 256
Total: 24799Total with Buffer Estimate (10%) 27278
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Alternative ImplementationsAlternative ImplementationsTransistor CountTransistor Count
(Assuming(Assuming 32-bit Implementation) 32-bit Implementation)
Current ~52,275
Minus 1 SBOX & Logic
~37,985 Minus 5 rounds & 1 SBOX and logic
~27,278
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Questions?Questions?
Answers???Answers???
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