The maximum path delay: Tmax = 0.1ps(Tcq) + 4ps(Tinterconnect) + 0.5ps(Ts) .

Hence the minimum frequency: 1/Tmax = 1/ 4.6x10^-12 = 2.1739 x 10^11 Hz

2)

The first path that is from input to reg needs to be less than the clock period, for the value to transfer correctly without being overwritten.

Tip to ff1 = Ti/p delay + Tic delay + Ts-ff1 + Tcq (Tip to ff1 should be less than or equal to minimum clock period) 4ps = 1ps + Tic delay + 1ps + 0.8ps Hence, Tic delay = 1.2 ps

Considering, Tff1-ff2 as the max delay,Tmax = Tcq + Tic-delay + Ts = 1ps + 5ps + 1ps = 7ps (which should be equal to Tmax)Minimum Clock Frequency is: 1/7ps =1.42x10^11 Hz Tmax-clock-period = Tip-delay + Tic-delay + Ts 7ps = 1ps + Tic delay + 1ps Tic delay(i/p -ff1) = 5ps. Tic (ff2-o/p) = 5ps (similarly).

Tmax-delay = Tcq(ff-1) + Tic-delay + Ts = 0.1ps + 4ps + 0.5ps = 4.6ps

Ti/p-reg = 4.5ps

To/p-reg = 4.5ps

Tmin clock period = 2x4.6ps /3(as the falling edge needs to reach at 4.6ps at ff2).

But this is less then Tip-ff1(4.5ps).

Hence Tmin-clk-period = 9.2 ps (To make sure that there is no borrowing of negative delay from the previous delay path having differently edged capture flip-flop)

Tmax = Tcq + Tid + Ts

Tmax = 1ps + 5ps + 1ps = 7ps

Tic-delay(i/p ff1) = 5ps (Tmax Ts Ti/p).

Tic-delay(ff2 -o/p) = 5ps (Tmax Tcq(ff2) To/p).

Tmin-clk = 7ps x 2 = 14 ps (To make sure that there is no borrowing of negative delay from the previous delay path having differently edged capture flip-flop)

Tmax-delay = Tcq(ff-1) + Tic-delay + Ts = 0.1ps + 4ps + 0.5ps = 4.6ps

Ti/p-reg = 4.5ps

To/p-reg = 4.5ps

Tmin clock period = 9.2 ps( To make sure that there is no borrowing of negative delay from the previous delay path having differently edged capture flip-flop)

Please note that I am assuming flops connected to input and output as positive edged.(If I do not assume signal going to any capture flop at output than it makes no sense to calculate Tff2 To/p interconnect delay.(The i/p-ff1 has been considered as input to reg path)

Tclk-min = 6ps

Tclk-min = 2x{Tcq(ff1) + Tic-delay(ff1-ff2) + Ts(ff2)} (As we are having oppositely edged capture and launch flip flop) Tic-delay(ff1-ff2) = (6ps 1.6ps -2ps)/2 = 1.2 ps

Tic-delay(i/p-ff1) = 3ps 1ps 1ps = 1ps

Tic-delay(i/p-ff2) = 3ps 1ps -0.5ps = 1.5ps

The maximum path delay: Tmax = 0.1ps(Tcq) + 4ps(Tinterconnect) + 0.5ps(Ts) .

Hence the minimum frequency: 1/Tmax = 1/ 4.6x10^-12 = 2.1739 x 10^11 Hz.

Ans: Both flops are negative edge triggered.T ic-delay = Tclock Input delay Tsdff1 = 6 1 1 = 4ps

T ic-delay(ff2-o/p) = Tclock Output delay Tcqdff2 = 6 1 0.5 = 4.5psReg to Reg = Tclk Tcqdff1 Tsdff2 = 6 0.8 1 = 4.2ps

Considering, Tff1-ff2 as the max delay,Tmax = Tcq + Tic-delay + Ts = 1ps + 5ps + 1ps = 7ps (which should be equal to Tmax)Minimum Clock Frequency is: 1/7ps =1.42x10^11 Hz Tmax-clock-period = Tip-delay + Tic-delay + Ts 7ps = 1ps + Tic delay + 1ps Tic delay(i/p -ff1) = 5ps. Tic (ff2-o/p) = 5ps (similarly).